JPS6042839A - Method for processing semiconductor wafer - Google Patents
Method for processing semiconductor waferInfo
- Publication number
- JPS6042839A JPS6042839A JP15098683A JP15098683A JPS6042839A JP S6042839 A JPS6042839 A JP S6042839A JP 15098683 A JP15098683 A JP 15098683A JP 15098683 A JP15098683 A JP 15098683A JP S6042839 A JPS6042839 A JP S6042839A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- defect
- heat treatment
- defects
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000007547 defect Effects 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 33
- 239000001301 oxygen Substances 0.000 claims description 33
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 26
- 230000005465 channeling Effects 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract description 93
- 238000010438 heat treatment Methods 0.000 abstract description 31
- 239000012298 atmosphere Substances 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 230000001590 oxidative effect Effects 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000002344 surface layer Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- -1 101′′'fm' Chemical compound 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 150000002926 oxygen Chemical class 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000004904 shortening Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 241000272525 Anas platyrhynchos Species 0.000 description 1
- 238000001444 catalytic combustion detection Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体ウェハの処理方法の改良に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for processing semiconductor wafers.
最近、 ＬＳＩの微細化に伴なってイントリシックケ゛
ツタウェハ（以下ＩＧウェハと称す）が用いられている
。このＩＧウェハは１１図に示す如くウェハ１の表向か
ら所望′ｔｇさまでの表ｒ０１層に欠陥のない無欠陥領
域２が、所望探さ以上の内部に高密度微小欠陥領域３が
、形成された構造になっている。かかるＩＧウェハは内
部に高密度微小欠陥領域）が形成されているため、この
ウェハより半導体装置を製造する際、その熱処理工程中
においてウェハ１の熱欠陥領域２の不純物４を高密度微
小欠陥領域３にゲッタできる（同第１図図示）。また、
縞２図に示す如くＩＧウェハな用いて例えば半導体メモ
リを製造した場′合、ウェハ（基板）１表面の無欠陥領
域２に発生した不要なキャリア５・・・などを高密度微
小欠陥領域３で再結合できる。なお、第２図中の６は基
板１表面に形成されたフィールド酸化膜、７はフィール
ド酸化膜６で分離された島状の基板１領域に薄い酸化膜
８を介して設けられたキャパシ；”（Ｈ’ＩＭである。Recently, with the miniaturization of LSIs, intrinsic silicon wafers (hereinafter referred to as IG wafers) have been used. In this IG wafer, as shown in Fig. 11, a defect-free region 2 without defects is formed in the surface r01 layer from the surface of the wafer 1 to a desired depth, and a high-density micro-defect region 3 is formed inside the surface beyond the desired depth. It has a structure. Since such an IG wafer has a high-density micro-defect region formed inside, when semiconductor devices are manufactured from this wafer, impurities 4 in the thermal defect region 2 of the wafer 1 are removed from the high-density micro-defect region during the heat treatment process. 3 (as shown in Figure 1). Also,
As shown in Fig. 2, when a semiconductor memory is manufactured using an IG wafer, unnecessary carriers 5 generated in a defect-free area 2 on the surface of a wafer (substrate) 1 are transferred to a high-density micro-defect area 3. It can be recombined with . In addition, 6 in FIG. 2 is a field oxide film formed on the surface of the substrate 1, and 7 is a capacitor provided through a thin oxide film 8 in an island-shaped region of the substrate 1 separated by the field oxide film 6. (H'IM.
図中の９は一部がゲート酸化１１１０を介して基板１表
面に位置し、他端が絶縁膜１１を介して前記キャパシタ
電極７上に延出したトランスファゲート電極、１２は層
間絶縁膜である。更に、図中め１３１ｍ１３２゜１３３
は前記キャパシタ電極７、トランスフ、アダート電極９
及び前記基板１の無欠陥領域２に形成されたｎ＋層１４
と夫々接続されたＡＪ配線である。したがって、ＩＧウ
ェハを用いることにより高性能、高信頼性の半導体装置
を得ることができる。In the figure, 9 is a transfer gate electrode whose part is located on the surface of the substrate 1 through the gate oxide 1110, and whose other end extends onto the capacitor electrode 7 through the insulating film 11, and 12 is an interlayer insulating film. . In addition, the inside of the figure is 131 m 132° 133
are the capacitor electrode 7, transfer electrode, add electrode 9
and an n+ layer 14 formed in the defect-free region 2 of the substrate 1.
and the AJ wiring connected respectively. Therefore, by using the IG wafer, a high performance and highly reliable semiconductor device can be obtained.
ところで、上述したＩＱウェハは従来、以下に示す処理
工程により造られている。By the way, the above-mentioned IQ wafer has conventionally been manufactured by the processing steps shown below.
まず、酸素を過剰に含んだ（例えば１０１″’ｆｍ’、
１ ）シリコンウェハ１を用意する（第３ ＵｉｉＬｌ
（ａ）図示）。First, it contains excess oxygen (e.g. 101″'fm',
1) Prepare silicon wafer 1 (3rd UiiLl)
(a) As shown).
つづいて、このウェハ１を８００℃の酸化性雰囲気中で
２〜５時間程度熱処理する。この時、ウェハ１中の過飽
和酸素が析出し、微小欠陥の核１５が発生する（第３図
（ｂ）図示）。次いで、１１００℃の酸化性雰囲気中で
４時間程度熱処理を行なうことによりウェハ１表面付近
の微小、欠陥１５が外部に逃散（アウターディフュージ
ョン）してウェハ１表面層に欠陥のない無欠陥領域２が
、形成されると共に、ウェハ１内部に高密度微小欠陥領
域３が形成されたＩＧウェハを得ることができる（第３
図（ｃ）図示）。Subsequently, this wafer 1 is heat treated in an oxidizing atmosphere at 800° C. for about 2 to 5 hours. At this time, supersaturated oxygen in the wafer 1 is precipitated and micro-defect nuclei 15 are generated (as shown in FIG. 3(b)). Next, heat treatment is performed in an oxidizing atmosphere at 1100° C. for about 4 hours, so that the minute defects 15 near the surface of the wafer 1 escape to the outside (outer diffusion), and a defect-free region 2 with no defects is formed on the surface layer of the wafer 1. , and an IG wafer in which a high-density micro-defect region 3 is formed inside the wafer 1 can be obtained (third step).
Figure (c) shown).
しかしながら、上述した従来の処理方法にあっては゛高
温、長時間の熱処理を必要とするため厚さの小さな無欠
陥領域（たとえば５μｍ）を形成することは困難であっ
た。またウェハに反りが発生し、この反りによりウモハ
１の無欠陥領域２に欠陥が発生する問題がある。また、
その熱処理工程中に汚染不純物（例えばＦｅ 、 Ｃｕ
。However, in the conventional processing method described above, it is difficult to form a defect-free region with a small thickness (for example, 5 μm) because it requires heat treatment at a high temperature and for a long time. Further, there is a problem in that the wafer is warped, and this warp causes defects in the defect-free area 2 of the wafer 1. Also,
During the heat treatment process, contaminating impurities (e.g. Fe, Cu
.
Ａｇ ）がウェハ１に取り込まれる可能性がある。There is a possibility that Ag) may be incorporated into the wafer 1.
更に、熱処理はウェハ１表面の汚染防止を目的として酸
化性雰囲気で行なうため、ウェハ１表面に酸化膜が積層
され、これに伴なってウェハ表面に積層欠陥が新たに生
じるという問題がある。その他、高温、長時間の熱処理
を必要とすることからＩＧウェハの製造コストの高騰化
を招く。また、逆に高温熱処理を行なった後は低温熱処
理を行なう゛方法もある。しかしながら、この場合は低
温処理に長時間要す木。Furthermore, since the heat treatment is performed in an oxidizing atmosphere for the purpose of preventing contamination of the surface of the wafer 1, an oxide film is laminated on the surface of the wafer 1, resulting in the problem that new stacking defects are generated on the surface of the wafer. In addition, high temperature and long-time heat treatment are required, leading to an increase in the manufacturing cost of IG wafers. Conversely, there is also a method of performing low temperature heat treatment after high temperature heat treatment. However, in this case, the tree requires a long time to be treated at low temperatures.
本発明は半導体ウェハへの反り発生を抑制ないし防止し
つつ表面層に無欠陥領域、内部に高密度微小欠陥領域が
形成されたＩＧクエハを低コストで製造し得る処理方法
を提供しようとするものである。The present invention aims to provide a processing method capable of manufacturing at low cost an IG wafer in which a defect-free area is formed on the surface layer and a high-density micro-defect area is formed inside, while suppressing or preventing the occurrence of warpage in the semiconductor wafer. It is.
本発明は半導体ウェハに不純物をＩ ＭｅＶ以上の高エ
ネルギーでイオン注入し、ウエノ１内部に該不純物によ
る微小欠陥を発生せしめることな特徴とするものである
。こうした方法によれば不純物、例えば酸素の濃度の低
いウェハな用いることが可能となり、ウェハ表層の過飽
和酸素又は微小欠陥を退勢（アウトディフュージョン）
させるための高温熱処理を短縮できることによって、表
面層に無欠陥領域、それより内部（１１１１Ｋ。The present invention is characterized in that impurities are ion-implanted into a semiconductor wafer at a high energy of I MeV or higher, and minute defects are generated inside the wafer 1 due to the impurities. This method makes it possible to use wafers with low concentrations of impurities, such as oxygen, and eliminates supersaturated oxygen or minute defects on the wafer surface (outdiffusion).
By shortening the high-temperature heat treatment required to make the surface layer defect-free, the interior (1111K) can be reduced.
高密度欠陥領域が形成され、かつ無欠陥領域中への二次
的な欠陥発生を低減した反り峠の少ないＩＧウェハを量
産的に得ることができる。 ′上記不純物とは、酸素、
炭素、仝集成いはこれらの混合物である。It is possible to mass-produce IG wafers in which high-density defect regions are formed, the occurrence of secondary defects in defect-free regions is reduced, and there are few warpages. 'The above impurities include oxygen,
Carbon, aggregates or mixtures thereof.
上記不純物のイオン注入時における打込みエネルギー（
加速電圧）を上記の如く限定した理由は加速電圧をＩ
ＭｅＶ未渦にすると、高密度微小欠陥領域を形成ずぺぎ
半導体ウェハ内部に十分な量の不純物を注入できなくな
るからである。Implantation energy during ion implantation of the above impurities (
The reason for limiting the accelerating voltage (accelerating voltage) as above is that the accelerating voltage is
This is because if MeV is not vortexed, a sufficient amount of impurities cannot be implanted into the semiconductor wafer without forming a high-density micro-defect region.
なお、このイオン注入にあたりて、半導体ウェハの結晶
軸、例えば（１１ｏ）＞ 、（ＩＪ ２）、（ｚ ００
＞。Note that during this ion implantation, the crystal axes of the semiconductor wafer, for example (11o)>, (IJ 2), (z 00
>.
（Ｊ Ｊ Ｊ＞方向に略平行にイオン注入するチャンネ
リング効果を利用すれば、低加速電圧で不純物を半導体
ウェハの内部に注入できる利点を有する。(By utilizing the channeling effect of ion implantation substantially parallel to the J J J> direction, there is an advantage that impurities can be implanted into the semiconductor wafer at a low acceleration voltage.
次に、本発明の実施例を図面を参照して詳卸１に匝り」
する。Next, the embodiments of the present invention will be explained in detail with reference to the drawings.
do.
実７１１！１例１
まず、不純物として例えば酸素を５×１０Ｉ７（１ｉＦ
２ｙ＃３詮む単結晶シリコンウェハ２１に酸素を加速電
圧２ ＭｅＶ、ドーズｉ １ Ｘ １０” ａｎ−”の
条件でイオン注入した。この時、第４図（ａ）に示す如
くウェハ２１主面から深さ４μｍに酸素濃度のピークを
もつ酸；（８イオン注入層２２が形成された。Fruit 711!1 Example 1 First, for example, oxygen is added as an impurity to 5×10I7 (1iF
2y#3 Oxygen ions were implanted into the single crystal silicon wafer 21 under conditions of an acceleration voltage of 2 MeV and a dose of i 1 x 10''an-''. At this time, an acid ion-implanted layer 22 having an oxygen concentration peak at a depth of 4 μm from the main surface of the wafer 21 was formed as shown in FIG. 4(a).
次いで、８００℃の酸化性雰囲気中で２時間熱処理を施
した。この時、酸素イオン注入層２２において過飽和酸
素が析出し、微小欠陥２３・・・が高ｍ−塵で生成され
た。同時に、高密度の微小欠陥２３・・・が生成された
以外の領域にも過飽和１夜累の析出による微小欠陥２３
・・・が散在して生Ｊ反された（第４図（ｂ）図示）。Next, heat treatment was performed for 2 hours in an oxidizing atmosphere at 800°C. At this time, supersaturated oxygen was precipitated in the oxygen ion-implanted layer 22, and micro defects 23 were generated with high m-dust. At the same time, microdefects 23 due to the precipitation of supersaturation overnight are also present in areas other than those where high-density microdefects 23 have been generated.
. . . were scattered and raw (as shown in Fig. 4(b)).
次いで、１１００℃の酸化性雰囲気中で２時間熱処理を
施した。この時、ウェハ２１表層に散在した微小欠陥２
３・・・がアウトデフニージョンして微小欠陥が消滅し
た。同時に、ウェハ２１内部の高密度の微小欠陥２３・
・・が周辺に散在した微小欠陥２３・・・をとり込みな
がら集積された。その結果、第４図（、）に示す如く表
面層にス１（（欠陥領域２４が、それより深い内部に高
密度微小欠陥領域２５が、形成されたＩＧウェハが製造
された。Next, heat treatment was performed for 2 hours in an oxidizing atmosphere at 1100°C. At this time, micro defects 2 scattered on the surface layer of the wafer 21
3... was out-deflated and the micro defects disappeared. At the same time, the high density of micro defects 23 and 23 inside the wafer 21
... were accumulated while incorporating minute defects 23 ... scattered around. As a result, an IG wafer was manufactured in which a defect region 24 was formed in the surface layer and a high-density micro-defect region 25 was formed deeper inside, as shown in FIG.
しかして本実施例１によれば、単結晶シリコンウェハ２
１に酸素を所定の加速電圧でイオン注入してウェハ２１
の内部に高濃度の酸素注入層を形成することにより、シ
リコンウェハ２〕として酸素濃度がＩ Ｘ １０ ”
（ｆｌＩｅ＋”と低いものを使用できる。このため、低
温熱死］■においてシリコンウェハ２１の表層には微小
欠陥２３・・・は散在して生成され、かつ高密度微小欠
陥、ｆｉｌ（域を形成すべき領域には微小欠陥２３・・
・を高密度で生成できるので、ウェハ２１表層の微小欠
陥２３・・・をアウトデフニージョンすると共に、内部
の微小欠陥２３・・・を集積するための高温熱処理工程
を短縮できる。その結果、高温熱処理工程を短縮できる
ことにより、ＩＧウェハの反り発生を抑制でき、ひいて
は反り発生に伴なう無欠陥領域２４への欠陥発生を著し
く抑制できる。また、酸素をイオン注入すること、ウニ
ノー２１のイ１（酸素濃度化及び高温熱処理時間の短縮
化によって、従来法では困難であった極めて薄い無欠陥
領域（例えば５〜１０μｍ以下、又はそれ以下）の形成
が可能となる。更に、高温炉を用いる高温熱処理時間を
短縮できることにより、炉壁から拡散した不純物による
二次汚染を抑制できる。However, according to the first embodiment, the single crystal silicon wafer 2
Oxygen is ion-implanted into the wafer 21 at a predetermined acceleration voltage.
By forming a high-concentration oxygen injection layer inside the silicon wafer 2, the oxygen concentration becomes I x 10''.
(flIe+" can be used. Therefore, in the low-temperature heat death] (2), micro defects 23 are generated scattered on the surface layer of the silicon wafer 21, and high density micro defects, fil (areas) are formed. Micro defects 23 in the desired area...
can be generated at a high density, it is possible to out-define the micro defects 23 on the surface of the wafer 21 and shorten the high-temperature heat treatment process for accumulating the internal micro defects 23. As a result, the high-temperature heat treatment step can be shortened, thereby suppressing the occurrence of warping of the IG wafer, and furthermore, the occurrence of defects in the defect-free region 24 due to the occurrence of warpage can be significantly suppressed. In addition, by ion-implanting oxygen and increasing the oxygen concentration and shortening the high-temperature heat treatment time (i.e., by increasing the oxygen concentration and shortening the high-temperature heat treatment time), we can achieve an extremely thin defect-free region (for example, 5 to 10 μm or less, or less), which is difficult to achieve with conventional methods. Furthermore, by shortening the high-temperature heat treatment time using a high-temperature furnace, secondary contamination due to impurities diffused from the furnace wall can be suppressed.
同様な埋山によりウニノ・２１表面への酸化膜の成長膜
厚を尚くできるため、厚い酸化膜成長によるウェハ２ノ
表面（無欠陥領域２４）への積層欠陥の発生を抑制でき
る。Since the thickness of the oxide film grown on the surface of the wafer 21 can be reduced by similar burying, the occurrence of stacking faults on the surface of the wafer 2 (defect-free region 24) due to the growth of a thick oxide film can be suppressed.
したがって、無欠陥領域２４中の不純物のダック効果に
ｆｌＪｔｓか２不要キヤリアの高密度微小欠陥領域２５
での再結合性に優れ、牛導体メモリやＣＣＤ等の基板に
適したＩＧウニノーを量産的に得ることができる。Therefore, due to the duck effect of impurities in the defect-free region 24, flJts or 2 unnecessary carriers in the high-density micro-defect region 25
It is possible to mass-produce IG UNINO, which has excellent recombinability and is suitable for substrates such as conductor memories and CCDs.
実施例２
不純物として例えば酸素を５Ｘ１０１フイＭ＋＋＋３＠
む単結晶シリコンウェハに酸素イオンの入射方向を該ウ
ェハの〈１１０＞結晶軸に対し±０．３°以内に軸合せ
した後、同酸素イオンを加速′Ｅｌｉ、圧ＩＭｅＶ 、
ドーズ値Ｉ Ｘ １０１６ｃｔｎ−２の条件でチャン坏
リングイオン注入した以外、実施例１と同：ｌｊＡな方
法でＩＧウェハを製造した。Example 2 For example, oxygen is added as an impurity to 5X101F M+++3@
After aligning the incident direction of oxygen ions to a single-crystal silicon wafer to within ±0.3° with respect to the <110> crystal axis of the wafer, the oxygen ions are accelerated at 'Eli, pressure IMeV,
An IG wafer was manufactured in the same manner as in Example 1, except that Chang-ring ions were implanted under the condition of a dose value of I.times.10.sup.16 ctn-2.
しかして、本実施例２によれば、チャンネリングイオン
注入により酸素をウェハにドーピングさせるため、低い
打込エネルギーでウェハ内に高密度微小欠陥領域を形成
できる。According to the second embodiment, since the wafer is doped with oxygen by channeling ion implantation, a high-density micro-defect region can be formed in the wafer with low implantation energy.
実施例３
まず、不純物として例えば酸素を５Ｘ１０”イ１ｔＶｔ
３）ｒｔ３ 含む単結晶シリコンウェハ２１に酸素イオ
ンの入射方向を該ウェハ２ノのく１１０〉結晶軸に対し
±０．３°以内に軸合ぜした後、同削素イオンを加速電
圧ＩＭａｖ、ドーズｉ １ ×１０ ’ ６ａｎ ２の
条件でチャンネリングイオン注入を行なった。Example 3 First, for example, oxygen is added as an impurity at 5×10” and 1tVt.
3) After aligning the incident direction of oxygen ions to the single-crystal silicon wafer 21 containing rt3 within ±0.3° with respect to the crystal axis of the wafer 2, the oxygen ions are accelerated at an acceleration voltage IMav, Channeling ion implantation was performed at a dose of i 1 ×10 ′ 6 an 2 .
この１１．＋ｉ、第５ Ｆ２；Ｉ （ａ）に示す如、く
ウェハ２１主面から深さ５μｍＫ酸素濃度のピークをも
つ酸素イオン注入ＪＶｊ２２が形成された。This 11. +i, 5th F2;I As shown in (a), oxygen ion implantation JVj22 having a peak oxygen concentration was formed at a depth of 5 μm from the main surface of the wafer 21.
次いで、１１００℃の酸化性雰囲気中で２時間熱処理を
施した。どの時、ウェハ２１ 表面Ｉ）過飽和酸素がア
ウトデ、イフユージョンすると共に、酸素イオン注入さ
れたウェハ２１の領域に微小欠陥の核２６・・・が生成
された（第５図（ｂ）図示）。Next, heat treatment was performed for 2 hours in an oxidizing atmosphere at 1100°C. When the surface of the wafer 21 (I) supersaturated oxygen is out and fused, micro defect nuclei 26 are generated in the region of the wafer 21 into which oxygen ions have been implanted (as shown in FIG. 5(b)).
次いで、ウェハ２１を８００℃の酸化性雰囲気中で２時
間熱処理を施した。この時、ウェハ２１内部の高密度の
微小欠陥の核を中心にして微小欠陥２３・・・が生成さ
れ、かつウェハ２１表面には核がないため、第５図（ｃ
）に示す如く表面層に無欠陥領域２４が、それより深い
部分に高密度微小欠陥領域２５が形成され、ＩＱウェハ
が製造された。Next, the wafer 21 was heat-treated in an oxidizing atmosphere at 800° C. for 2 hours. At this time, micro-defects 23... are generated around the high-density micro-defect nuclei inside the wafer 21, and since there are no nuclei on the surface of the wafer 21, as shown in FIG.
), a defect-free region 24 was formed in the surface layer and a high-density micro-defect region 25 was formed in a deeper part, and an IQ wafer was manufactured.
し、かして、本実施例３によれば実施１例１と同様、無
欠陥領域２４中の不純物のｒ２夕効果に俊れ、かつ不要
キャリアの高密度微小欠陥領域２５での再結合性に優れ
たＩＧウェハなＭ性的に得ることができる。However, according to the third embodiment, as in the first embodiment, the r2 effect of impurities in the defect-free region 24 can be suppressed, and the recombination property of unnecessary carriers in the high-density micro-defect region 25 can be improved. It is possible to obtain an IG wafer with excellent M properties.
なお、上記実ｈｍ例１〜３での低温熱処理工程は７００
〜９００℃の温度範囲で行なえばよ＜、。In addition, the low temperature heat treatment process in the above actual hm examples 1 to 3 was performed at 700
It should be done in a temperature range of ~900℃.
高温熱処理工程は１０５０〜１２ｏｏ℃の温度範囲で行
なえばよい。°また、実施例３の場合では低温熱処理を
代りにＬＳＩ等の素子製造プロセスの熱工程（例えば９
００’Ｃ程度）を利用して微小欠陥の核を中心にして微
小欠陥を形成してもよい。The high temperature heat treatment step may be performed at a temperature range of 1050 to 12 oo<0>C. °In the case of Example 3, the low-temperature heat treatment is replaced by a thermal step (for example, 9
00'C) to form microdefects around the core of the microdefect.
実施例４
まず、不純物として例えば酸素を５ Ｘ １０１７饅へ
３含む単結晶シリコンウェハ２１に酸素イオンの入射方
向を該ウェハ２１のく１１ｏ〉結晶軸に対し±０．３°
以内に軸合ぜした後、同酸系イオンヲ加速電圧Ｉ Ｍａ
Ｖ ％’ ｌ’ −ｉ ｉ Ｉ Ｘ ｌ”０”ｏｒｒ
”の条件でチャンネリングイオン注入を行なった。Example 4 First, the direction of incidence of oxygen ions on a single-crystal silicon wafer 21 containing, for example, oxygen as an impurity at 5×1017 points is set at ±0.3° with respect to the crystal axis of the wafer 21.
After aligning the axes within the same acid ion acceleration voltage I Ma
V %'l' -i i I X l"0"orr
Channeling ion implantation was performed under the following conditions.
この、時、“扁６図（ａ）に示す如く、ウェハ２１主面
から深さ５μｍに酸素濃度のピークをもつ酸素イオン注
入層２２が形成された。At this time, as shown in FIG. 6(a), an oxygen ion-implanted layer 22 having an oxygen concentration peak at a depth of 5 μm from the main surface of the wafer 21 was formed.
次いで、８００℃の酸化性雰囲気中で２時間熱処理を施
した。この時、酸素イオン注入層２２において過飽和酸
素が析出し、微小欠陥２３が高密度で生成された。同時
に、高密度の微小欠陥２３・・・が生成された以外の領
域にも過飽和酸素の析出による微小欠陥２３・・・が散
散して生成された（第６図（ｂ）図示）。Next, heat treatment was performed for 2 hours in an oxidizing atmosphere at 800°C. At this time, supersaturated oxygen was precipitated in the oxygen ion-implanted layer 22, and micro defects 23 were generated at a high density. At the same time, minute defects 23 due to the precipitation of supersaturated oxygen were scattered and generated in areas other than the areas where the high-density minute defects 23 were generated (as shown in FIG. 6(b)).
次いで、シリコンウェハ２１主面に波長１．０６μｍ、
出力０．１ ｍＪ／ノ臂ルパルス以上ＡＧレーデビーム
を走査しながら照射した。この時、ウェハ２１主面に近
い部分の散在した微小欠陥がアウトディフュージョンし
て微小欠陥が消滅した。Next, a wavelength of 1.06 μm was applied to the main surface of the silicon wafer 21.
Irradiation was performed while scanning the AG radar beam with an output of 0.1 mJ/arm pulse or more. At this time, the scattered micro defects near the main surface of the wafer 21 were outdiffused and disappeared.
同時に、ウェハ２ノの主面より深い部分の高密度の微小
欠陥２３・・・が周辺に散在した微小欠陥２３・・・を
とり込みながら集積された。なお、主面とは反対側のウ
ェハ２１の微小欠陥２３・・・は散在した状態でそのま
ま残った。その結果、第６図（ｃ）に示す如く主面層に
無欠陥領域２４が、それより深い内部に一定の厚さをも
つ高密度微小欠陥領域２５が、形成されたＩＧウニノー
が製造された。At the same time, high-density micro-defects 23 . . . in a portion deeper than the main surface of the wafer 2 were integrated while incorporating micro-defects 23 . . . scattered around the wafer 2 . Note that the minute defects 23 on the side opposite to the main surface of the wafer 21 remained as they were in a scattered state. As a result, as shown in FIG. 6(c), an IG Uninow was manufactured in which a defect-free region 24 was formed in the main surface layer, and a high-density micro-defect region 25 with a certain thickness was formed deeper inside. .
しかして本実施例４によれば微小欠陥２３０アウトデイ
フユージヨンをレーザビームの照射により行なうため、
ＩＧウニへの反り発生笠を実施例１の方法に比べて一層
防止できる。また、ウェハ２１主面のみを加熱できるた
め、一層薄い無欠陥領域を制御性よく形成できる。更に
、高温炉中での熱処理工程を省屹できるため、炉壁の不
純物からの二次汚染や酸化膜の成長による無欠陥領域へ
の積層欠陥の発生を顕著に抑制できる。したがって、芙
施例１でイケられたＩＧウェハに比べて格段に優れたＩ
ＧウェハをＪｉ１産的に得ることができる。However, according to the fourth embodiment, since the out-diffusion of the micro defect 230 is performed by irradiation with a laser beam,
The warping of the IG sea urchin can be further prevented compared to the method of Example 1. Further, since only the main surface of the wafer 21 can be heated, a thinner defect-free region can be formed with good controllability. Furthermore, since the heat treatment step in a high-temperature furnace can be saved, it is possible to significantly suppress secondary contamination from impurities on the furnace wall and the occurrence of stacking faults in defect-free regions due to the growth of oxide films. Therefore, compared to the IG wafer produced in Example 1,
G wafers can be obtained efficiently.
なお、上記実施例４ではウェハな低温熱処理した後レー
ザビームを照射したが、これに限定されない。例えばレ
ーザビームの照射後に低温熱処理を施してもよい。レー
デビームを低温熱処理工程として用いてもよく、或いは
低温、高温の熱処理工程を全てレーザビームを用〜′・
て行なってもよい。また、レーデビームとして出力Ｑ、
１ ｍＪ／ ノ”ルスのものを用いたが、ｏ、ｏｉ〜
０．３ｍＪ／／？ルづ程度のＹＡＧレーザビームを用い
れば現様な効果を発揮できる。更にＹＡＧレーザビーム
に代ってＣＯ２レーザビームの他のレーザビーム、エレ
クトロンビーム等のエネルギービームを用いてもよい。Note that in Example 4, the wafer was subjected to low-temperature heat treatment and then irradiated with a laser beam, but the present invention is not limited thereto. For example, low-temperature heat treatment may be performed after laser beam irradiation. A laser beam may be used for the low-temperature heat treatment process, or a laser beam may be used for both low-temperature and high-temperature heat treatment processes.
You may do so. In addition, the output Q as a radar beam,
1 mJ/no'rus was used, but o, oi ~
0.3mJ//? The current effect can be achieved by using a YAG laser beam of about 1000 yen. Further, instead of the YAG laser beam, other laser beams such as a CO2 laser beam, or energy beams such as an electron beam may be used.
実施例５
レーデビームの照射の代りに出力２０ ｋＷの赤外線閃
光ランプからのフラッシュ光（波長４０００〜４０００
０Ｘ）を照射した以外、実施例４と同様な方法によりＩ
Ｃウニノーを製造した。Example 5 Flash light from an infrared flash lamp with an output of 20 kW (wavelength 4000-4000
I was prepared in the same manner as in Example 4 except that 0
C Unino was produced.
しかして、実施例５の方法によれば実施例４と同＠な侵
れすこゲッタ効果等を有するＩＧウェハをより簡単かつ
量産的に得ることができる。Therefore, according to the method of the fifth embodiment, an IG wafer having the same erosive getter effect as that of the fourth embodiment can be obtained more easily and in a mass-produced manner.
なお、上記実施例５ではウニノ１を低温熱処理した後フ
ラッシュ光を照射したが１．これに限定されない。例え
ばフラッシュ光の照射後に低温熱処理を施してもよい。Note that in Example 5, Unino 1 was irradiated with flash light after being heat-treated at a low temperature, but 1. It is not limited to this. For example, low-temperature heat treatment may be performed after irradiation with flash light.
また、フラッシュ光を低温熱処理工程として用いてもよ
く、或（１は低温、高温の熱処理工程を全てフラッシュ
光で行なってもよい。Furthermore, flash light may be used as the low-temperature heat treatment step, or (1) both low-temperature and high-temperature heat treatment steps may be performed with flash light.
実施例６
まず、シリコンウェハ２１表面に酸化膜２７を形成し、
この酸化膜２２に開口部゛２８を形成した後、該開口部
２８から露出するウェハ２）を種結晶として全面に単結
晶シリコン層を成長させ、更にこのシ四コン層をノリー
ニングして酸素を５ Ｘ １０”＠／ｃｍ”含む単結晶
シリコンパターン２９を形成した。次いで、この単結晶
シリコンパターン２９の実施例４と同様な処理を施して
主面層に無欠陥領域２４が、それより内部に高密度微小
欠陥領域２５が形成されたインドリシックｒ２タリング
シリコン層を有するＳＯＩを製造した（第７図図示）。Example 6 First, an oxide film 27 is formed on the surface of a silicon wafer 21,
After forming an opening 28 in this oxide film 22, a single-crystal silicon layer is grown on the entire surface using the wafer 2) exposed through the opening 28 as a seed crystal, and this silicon layer is further annealed to remove oxygen. A single crystal silicon pattern 29 having a size of 5×10”@/cm” was formed. Next, this single crystal silicon pattern 29 is subjected to the same treatment as in Example 4 to form an indolithic r2 taring silicon layer in which a defect-free region 24 is formed on the main surface layer and a high-density micro-defect region 25 is formed inside it. An SOI having the following properties was manufactured (as shown in FIG. 7).
しかして、本実施例６によればゲッタ効果等の優れ、三
次元集積回路の基板として適したＳＯＩを量産的に得る
ことができる。According to the sixth embodiment, it is possible to mass-produce SOI which has excellent getter effects and is suitable as a substrate for three-dimensional integrated circuits.
なお、上記実施例６ではＳＯＩウェハを対象として処理
を行なったが、シリコンウェハ上に単結晶シリコン層を
成長させたもの、或いは５ｏｓ（５ｌｌｉｃｏｎ ｏｎ
５ａｐｐｈｉｒｅ） ウェハ等にも同様に適用できる
〇
また、上記各実施例ではイオン注入する不純物として酸
素を用いたが、炭素、窒素或いは酸素と炭素などの混合
物を用いても同様な効果を発揮できる。In Example 6 above, the SOI wafer was treated, but the process was performed on a silicon wafer in which a single crystal silicon layer was grown, or on a 5os (5llicon on silicon) wafer.
5apphire) Can be similarly applied to wafers, etc.Although oxygen was used as the impurity for ion implantation in each of the above embodiments, the same effect can be achieved by using carbon, nitrogen, or a mixture of oxygen and carbon.
以上詳述した如く、本発明によれば半導体ウェハへの反
り発生を抑制ないし防止しつつ表面層に無欠陥領域、内
部に高密度微小欠陥領域が形成され、半導体メモリやＣ
ＣＤ等の基板に適した工Ｇウェハを低コストで製造し得
る処理方法を提供できる。As described in detail above, according to the present invention, a defect-free region is formed in the surface layer and a high-density micro-defect region is formed inside the semiconductor wafer while suppressing or preventing the occurrence of warpage in the semiconductor wafer.
It is possible to provide a processing method that can manufacture engineered wafers suitable for substrates such as CDs at low cost.
第１図はＩＧウェハを示す断面図、第２図はＩＧウェハ
より製造された半導体メモリを示す断面図、第３図（、
）〜（ｅ）は従来法によるＩＧウニへの製造工程を示す
断面図、第４図（、）〜（Ｃ）は本発明の実施例１にお
けるＩＧウウニ飄の製造工程を示す断面図、第５図（、
）〜＜Ｃ）は本発明の実施例３にオｄけるＩＧウニノー
の製造工程を示す断面図、第６図（、）〜（ｅ）は実施
例４におけるＩＣウニノ・の製造−〒程を示す断面図、
第７図レエ実施例６により得られたイントリシックダッ
クリンダシ１ノコフ層を有するＳＯＩの断面図である。
２１・・・単結晶シリコンウニノ・、２２・・・酸素イ
オン注入層、２３・・・微小欠陥、２４・・・無欠陥領
域、２５・・・高密度微小欠陥領域、２９・・・単結晶
シリコンパターン。
第１図
２
第２図
第３図
第４図
第５図
第６図
第７図Figure 1 is a sectional view showing an IG wafer, Figure 2 is a sectional view showing a semiconductor memory manufactured from the IG wafer, and Figure 3 (
) to (e) are cross-sectional views showing the manufacturing process for IG sea urchin according to the conventional method. Figure 5 (,
) to <C) are cross-sectional views showing the manufacturing process of IG Unino in Example 3 of the present invention, and Figures 6(,) to (e) are cross-sectional views showing the manufacturing process of IC Unino in Example 4 A cross-sectional view showing,
FIG. 7 is a cross-sectional view of an SOI having an intrinsic ducklindash one-nocoff layer obtained by Raye Example 6; 21... Single crystal silicon unino, 22... Oxygen ion implantation layer, 23... Micro defect, 24... Defect free region, 25... High density micro defect region, 29... Single crystal silicon pattern. Figure 1 Figure 2 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7
Claims (1)
高エネルギーでイオン注入し、ウェハ内部に該不純物に
よる微小欠陥を発生せしめることを特徴どする半導体ウ
ェハの処理方法。 （２） 不純物をチャンネリング効果を利用して半４ノ
体ウェハにイオン注入せしめることを特徴とする特許請
求の範囲第１項記載の半導体ウェハの処理方法。 （３）不純物が酸素、炭素又は留累のいずれかのもので
あることを特徴とする特許請求の範囲第１項記載の半導
体ウェハ・の処理方法。 （４）十４リイトウエハが単結晶シリコンからなること
を特徴とする特許請求の範囲第１項記載の半導体ウェハ
の処理方法。 （５）半導体ウェハが絶縁物上に形成された単結晶シリ
コン層からなるものであることを特徴とする特許請求の
範囲第１項記載の半導体ウェハの処理方法。[Claims] (]) Processing of a semiconductor wafer characterized by ion-implanting impurities into the wafer at high energy of I MeV or higher to generate minute defects due to the impurities inside the wafer. Method. (2) A method for processing a semiconductor wafer according to claim 1, characterized in that impurities are ion-implanted into a semi-quaternary wafer by utilizing a channeling effect. (3) A method for processing a semiconductor wafer according to claim 1, wherein the impurity is any one of oxygen, carbon, or residue. (4) The method for processing a semiconductor wafer according to claim 1, wherein the 14-light wafer is made of single crystal silicon. (5) The method for processing a semiconductor wafer according to claim 1, wherein the semiconductor wafer is made of a single crystal silicon layer formed on an insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15098683A JPS6042839A (en) | 1983-08-19 | 1983-08-19 | Method for processing semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15098683A JPS6042839A (en) | 1983-08-19 | 1983-08-19 | Method for processing semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6042839A true JPS6042839A (en) | 1985-03-07 |
Family
ID=15508783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15098683A Pending JPS6042839A (en) | 1983-08-19 | 1983-08-19 | Method for processing semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042839A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234932A (en) * | 1988-07-25 | 1990-02-05 | Sony Corp | Gettering method for semiconductor wafer |
| FR2704949A1 (en) * | 1993-05-06 | 1994-11-10 | Bosch Gmbh Robert | Process for the manufacture of sensors and sensor manufactured according to this method. |
| US5502010A (en) * | 1992-07-17 | 1996-03-26 | Kabushiki Kaisha Toshiba | Method for heat treating a semiconductor substrate to reduce defects |
| JP2002368001A (en) * | 2001-06-07 | 2002-12-20 | Denso Corp | Semiconductor device and its manufacturing method |
-
1983
- 1983-08-19 JP JP15098683A patent/JPS6042839A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234932A (en) * | 1988-07-25 | 1990-02-05 | Sony Corp | Gettering method for semiconductor wafer |
| US5502010A (en) * | 1992-07-17 | 1996-03-26 | Kabushiki Kaisha Toshiba | Method for heat treating a semiconductor substrate to reduce defects |
| US5885905A (en) * | 1992-07-17 | 1999-03-23 | Kabushiki Kaisha Toshiba | Semiconductor substrate and method of processing the same |
| FR2704949A1 (en) * | 1993-05-06 | 1994-11-10 | Bosch Gmbh Robert | Process for the manufacture of sensors and sensor manufactured according to this method. |
| JP2002368001A (en) * | 2001-06-07 | 2002-12-20 | Denso Corp | Semiconductor device and its manufacturing method |
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