JPS6040208B2 - Voltage controlled variable resistor - Google Patents
Voltage controlled variable resistorInfo
- Publication number
- JPS6040208B2 JPS6040208B2 JP2664476A JP2664476A JPS6040208B2 JP S6040208 B2 JPS6040208 B2 JP S6040208B2 JP 2664476 A JP2664476 A JP 2664476A JP 2664476 A JP2664476 A JP 2664476A JP S6040208 B2 JPS6040208 B2 JP S6040208B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- resistance element
- variable resistance
- controlled variable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H5/00—One-port networks comprising only passive electrical elements as network components
- H03H5/12—One-port networks comprising only passive electrical elements as network components with at least one voltage- or current-dependent element
Landscapes
- Networks Using Active Elements (AREA)
- Control Of Amplification And Gain Control (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明は制御様子に印加される電圧により出力抵抗値が
可変制御される電圧制御形可変抵抗器に関し、特にパイ
ロット信号自動利得調整方式に有効に使用されるべくメ
モリ機能を付加した電圧制御形可変抵抗器に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage-controlled variable resistor whose output resistance value is variably controlled by the voltage applied to the control mode, and in particular has a memory function to be effectively used in a pilot signal automatic gain adjustment method. The present invention relates to a voltage controlled variable resistor with additional features.
伝送通信系等の伝送路レベル調整には、パィロット信号
制御による自動利得調整方式が用いられることが少なく
ない。An automatic gain adjustment method using pilot signal control is often used to adjust the level of a transmission line in a transmission communication system or the like.
これはパイロット信号のレベルの増減を監視し、基準レ
ベルに対し伝送路の信号レベルを一定にするように調整
する方式である。この方式において、伝送路のレベル調
整用の装置として用いられるものに例えば電圧制御形可
変抵抗器がある。This is a method that monitors increases and decreases in the level of the pilot signal and adjusts the signal level of the transmission line to be constant with respect to the reference level. In this system, for example, a voltage controlled variable resistor is used as a device for adjusting the level of the transmission line.
この可変抵抗器は制御端子を有し、該制御端子に印加さ
れる電圧により出力抵抗値が可変制御されるものである
。この電圧制御形可変抵抗器には抵抗値の温度特性、交
流信号を印加した時の歪高調波成分発生等の観点から、
高安定度、高品質、高信頼性が要求される。従来、この
要求を満たす電圧制御形可変抵抗器として例えば第１図
に示たものがある。This variable resistor has a control terminal, and the output resistance value is variably controlled by the voltage applied to the control terminal. This voltage-controlled variable resistor is designed to
High stability, high quality, and high reliability are required. Conventionally, there is a voltage-controlled variable resistor that satisfies this requirement, for example, as shown in FIG.
これは制御端子に印加される制御電圧のレベルの変動を
逐次検出して出力で後続の抵抗値出力素子を駆動する駆
動素子として、演算増幅器（以下オベァンプという）３
を用い、抵抗値出力素子として電圧制御形可変抵抗素子
である電界効果トランジスタ（以下、ＦＥＴという）５
を用いて、電圧制御形可変抵抗器を構成したものである
。すなわち、オベアンプ３の十入力端子１を制御端子と
して入力電圧を印加し、オベアンプ３の出力電圧はＦＥ
Ｔ５のゲート１６に高抵抗６を介して印加される。一方
、ＦＥＴ５のソース端子１８は接地され、ドレィン端子
１７には電圧源９と高抵抗８からなる定電流源回路１０
から定電流を供給されていて、且つ、ドレィン端子１７
からはオベアンプ３の一入力端子１９に高抵抗１４，１
５を介して帰還されている。更にドレィソ１７とゲート
１６は高抵抗７で接続されている。一般に、ＦＥＴを交
流の可変抵抗器として使用する場合、交流信号に対して
歪高調波成分が発生し、伝送通信系の品質を低下させる
原因となる。This is an operational amplifier (hereinafter referred to as an operational amplifier) 3 as a driving element that sequentially detects fluctuations in the level of the control voltage applied to the control terminal and drives the subsequent resistance value output element with its output.
A field effect transistor (hereinafter referred to as FET) 5, which is a voltage controlled variable resistance element, is used as a resistance value output element.
A voltage controlled variable resistor is constructed using the following. That is, the input voltage is applied to the input terminal 1 of the OBE amplifier 3 as a control terminal, and the output voltage of the OBE amplifier 3 is FE.
It is applied to the gate 16 of T5 via the high resistance 6. On the other hand, the source terminal 18 of the FET 5 is grounded, and the drain terminal 17 is connected to a constant current source circuit 10 consisting of a voltage source 9 and a high resistance 8.
A constant current is supplied from the drain terminal 17.
A high resistance 14,1 is connected to one input terminal 19 of the oven amplifier 3.
It is returned via 5. Further, the drain sensor 17 and the gate 16 are connected through a high resistance 7. Generally, when an FET is used as an alternating current variable resistor, distortion harmonic components are generated in the alternating current signal, which causes deterioration in the quality of the transmission communication system.
そこでこの種の歪成分抑圧のために、良く知られている
ようにドレイン端子１７とソース端子１８との間の電圧
Ｕ。ｓのＵｏｓ／２なる電圧がゲート端子１６に印加さ
れるように抵抗６と７の値は選ばれている。以上のよう
に構成すると、帰還回路のため入力電圧に直線的に比例
し、且つ、歪成分の少ない交流抵抗値が直流阻止用のコ
ンデンサ１１を通して出力端子２及び接地間より得られ
る。なお、第１図では抵抗値出力素子として電圧制御形
可変抵抗素子であるＦＥＴ５を用いているが、電流制御
形可変抵抗素子である傍熱形サーミスタをＦＥＴ５のか
わりに用いることができる。この場合第１図の１７およ
び１８間にサーミスタを接続しかつ１６からの電流を該
サーミスタの傍の熱発生部に導び〈ように接続すればよ
い。ここで、再びパイロット信号自動利得調整方式に言
及するが、この方式においては伝送路のパイロット信号
が断の時にその断の直前のパイロット信号のレベル値を
長時間に亘つて記憶することができる高性能の電圧記憶
回路が必要とされている。この要求を満たす電圧記憶回
路としては第２図に示されるような良く知られた回路が
使用されている。すなわち、リレーコイルによりリレー
接点４が閉状態の時、出力ＣＵＴにはオベアンプ３の一
入力端子ＩＮに加えられる入力電圧に対して１対１なる
電圧を発生し、一方リレーコイルにより該リレー接点４
が開状態の時、コンデンサ１２の充電作用とＭＯＳ型Ｆ
ＥＴ５の高入力抵抗との作用により、出力電圧はリレ−
４や開状態になる直前の値に、回路定数によって決まる
時定数に従って長時間安定に保持される、いわゆる電圧
記憶回路を構成している。Therefore, in order to suppress this type of distortion component, as is well known, the voltage U between the drain terminal 17 and the source terminal 18 is increased. The values of resistors 6 and 7 are chosen such that a voltage of Uos/2 of s is applied to gate terminal 16. With the above configuration, because of the feedback circuit, an AC resistance value that is linearly proportional to the input voltage and has few distortion components can be obtained from between the output terminal 2 and the ground through the DC blocking capacitor 11. Although the FET 5, which is a voltage-controlled variable resistance element, is used as the resistance value output element in FIG. 1, an indirectly heated thermistor, which is a current-controlled variable resistance element, can be used instead of the FET 5. In this case, a thermistor may be connected between 17 and 18 in FIG. 1, and the current from 16 may be led to a heat generating portion near the thermistor. Here, we will refer again to the pilot signal automatic gain adjustment method. In this method, when the pilot signal on the transmission line is disconnected, the level value of the pilot signal immediately before the disconnection can be stored for a long time. A high performance voltage storage circuit is needed. As a voltage storage circuit that satisfies this requirement, a well-known circuit as shown in FIG. 2 is used. That is, when the relay contact 4 is in the closed state by the relay coil, a voltage that is 1:1 with respect to the input voltage applied to one input terminal IN of the oven amplifier 3 is generated at the output CUT, and on the other hand, the relay contact 4 is
When is open, the charging action of capacitor 12 and MOS type F
Due to the interaction with the high input resistance of ET5, the output voltage is
4 or the value immediately before the open state is maintained stably for a long time according to a time constant determined by a circuit constant, forming a so-called voltage memory circuit.
以上のごとく、パイロット信号自動利得調整方式を実現
するには、第１図に示したような可変抵抗器および第２
図に示したようなパイロット信号の断に応答してその直
前のパイロット信号のレベル値を長時間保持する電圧記
憶回路が必要であった。As described above, in order to realize the pilot signal automatic gain adjustment method, it is necessary to use a variable resistor and a second
A voltage storage circuit as shown in the figure is required to respond to the disconnection of the pilot signal and hold the level value of the immediately preceding pilot signal for a long period of time.
ここで、可変抵抗器を上記パイロット信号自動利得調整
方式に有効に使用可能とさせるためには、第２図の電圧
記憶回路の出力電圧を第１図の可変抵抗器の制御端子に
接続して可変抵抗器に電圧記憶機能（メモリ）を付加す
ればよいのであるが、このようにして構成するメモリ付
可変抵抗器はいかにも複雑な構成である。In order to effectively use the variable resistor in the pilot signal automatic gain adjustment method described above, the output voltage of the voltage storage circuit shown in FIG. 2 must be connected to the control terminal of the variable resistor shown in FIG. It would be possible to add a voltage storage function (memory) to the variable resistor, but the variable resistor with memory constructed in this way has a very complicated structure.
本発明の目的は上述したパイロット信号自動制御方式の
実現のための条件を満たすメモリ付可変抵抗器を極めて
簡単な回路構成で提供することにある。An object of the present invention is to provide a variable resistor with a memory that satisfies the conditions for realizing the above-mentioned automatic pilot signal control method with an extremely simple circuit configuration.
すなわち本発明は第１図に示した可変抵抗器と第２図に
示した電圧記憶回路との構成が極めて類似していること
に注目し、該可変抵抗器に電圧記憶機能を付加する際に
双方に共通なる構成要素を該可変抵抗器の構成要素（第
１図の抵抗値出力素子であるＦＥＴ５と、駆動素子であ
るオベアンプ３）で兼用できないかという思想に基づく
ものである。That is, the present invention focuses on the fact that the configurations of the variable resistor shown in FIG. 1 and the voltage storage circuit shown in FIG. 2 are extremely similar, and when adding a voltage storage function to the variable resistor, This is based on the idea that the components of the variable resistor (the FET 5, which is the resistance value output element in FIG. 1, and the oven amplifier 3, which is the drive element) that are common to both can be used for the same purpose.
さらに、本発明は上記電圧記憶回路の構成要素のうち上
記可変抵抗器の構成要素と実質共通でない非共通要素（
第２図のりレー接点４およびリレーコイルからなるスイ
ッチ回路と、該スイッチ回路の出力および接地間に接続
されたコンデンサ１２）を該可変抵抗器内に組み込めば
よいという思想にも基づくものである。本発明によれば
、第１の入力端子に接続される第２の入力端子とを有す
る演算増幅器と、該演算増幅器の出力信号を制御端に受
ける電圧又は電流制御形可変抵抗素子と、該可変抵抗素
子に定電流を流すための定電流源と、該可変抵抗素子の
出力量を上記演算増幅器の第１の入力端子に帰還させる
ための帰還回路とを有し、上記制御端子に印加される電
圧に応じた出力抵抗値が上記可変抵抗素子の出力として
得られるようにした電圧制御形可変抵抗器において、上
記制御端子に印加される信０号が断の時に開くスイッチ
回路と該スイッチ回路の出力および接地間に接続される
コンデンサとを上記演算増幅器の第２の入力端子の入力
側に、あるいは上記演算増幅器の出力端子と上記可変抵
抗素子の上記制御端との間に、挿入接続し、該コンデン
サの充電電荷と該コンデンサの後続段の有する高入力抵
抗との相互作用による電圧記憶機能を付加したことを特
徴とする電圧制御形可変抵抗器力ｉ２得られる。Furthermore, the present invention provides a non-common element (
It is also based on the idea that a switch circuit consisting of a relay contact 4 and a relay coil as shown in FIG. 2, and a capacitor 12 connected between the output of the switch circuit and ground can be incorporated into the variable resistor. According to the present invention, an operational amplifier having a second input terminal connected to a first input terminal, a voltage or current controlled variable resistance element receiving an output signal of the operational amplifier at a control terminal, and The variable resistance element has a constant current source for causing a constant current to flow through the resistance element, and a feedback circuit for feeding back an output amount of the variable resistance element to a first input terminal of the operational amplifier, and is applied to the control terminal. A voltage-controlled variable resistor in which an output resistance value corresponding to the voltage is obtained as the output of the variable resistance element includes a switch circuit that opens when the signal 0 applied to the control terminal is disconnected; A capacitor connected between the output and ground is inserted and connected to the input side of the second input terminal of the operational amplifier, or between the output terminal of the operational amplifier and the control terminal of the variable resistance element, A voltage-controlled variable resistor i2 is obtained which is characterized in that it has an added voltage storage function due to the interaction between the charged charge of the capacitor and the high input resistance of the stage subsequent to the capacitor.
以下、図面により本発明の実施例を説明する。Embodiments of the present invention will be described below with reference to the drawings.
第３図は本発明による第１の実施例である。駆動素子で
あるオベアンプ３の十入力端子１を制御端子としてこれ
にアナログ電圧を印加する。スイッチ回路２１はリレー
コイルとＩＪレー接点４からなり、上記制御端子に印加
される信号が断の時のりレー接点４が開くように動作す
る。オベァンプ３の出力電圧は、スイッチ回路２１のリ
レー接点４を介し、更に高抵抗６を介して抵抗値出力素
子であるＭＯＳ型ＦＥＴ５のゲート（即ち制御端）１６
に印加される。一方、ＭＯＳ型ＦＥＴのソース１８は接
地されており且つ、ＭＯＳ型ＦＥＴ５のドレィン１７に
は定電圧源９及び高抵抗８からなる定電流源回路１０よ
り定電流が供給されている。更に、ドレィン１７から該
オベアンプ３の−入力端子１９に帰還抵抗１４及び１５
を介して帰還されている。，一方、ドレイン１７とゲー
ト１６には高抵抗７とコンデンサー３との直列回路が接
続され且つ、該スイッチ回路２１の出力をコンデンサー
２を通して接地する。尚、抵抗６と７は同じ値であり、
交流信号に対して十分インピーダンスが大きいので、ス
イッチ回路２１の接点４が閉及び関いずれの状態におい
てもドレィン１７及びソース１８間の１／２の電圧が常
にゲート１６に印加されるように作用している。また、
コンデンサー２及び１３は絶縁抵抗が高く、且つ交流信
号に対して十分インピーダンスが低いことが要求される
。以上のようにして構成されたメモリ付可変抵抗器は構
成が簡単であり、又スイッチ回路２１の接点４が閉状態
のときは帰還抵抗７及び６により位定に且つ、アナログ
入力電圧に対し直線的に動作する。FIG. 3 shows a first embodiment according to the present invention. An analog voltage is applied to the input terminal 1 of the OBE amplifier 3, which is a driving element, as a control terminal. The switch circuit 21 consists of a relay coil and an IJ relay contact 4, and operates so that the relay contact 4 opens when the signal applied to the control terminal is disconnected. The output voltage of the amplifier 3 is applied via the relay contact 4 of the switch circuit 21 and further via the high resistance 6 to the gate (i.e., control end) 16 of the MOS type FET 5, which is a resistance value output element.
is applied to On the other hand, the source 18 of the MOS type FET is grounded, and a constant current is supplied to the drain 17 of the MOS type FET 5 from a constant current source circuit 10 consisting of a constant voltage source 9 and a high resistance 8. Further, feedback resistors 14 and 15 are connected from the drain 17 to the − input terminal 19 of the obeamp 3.
has been returned via. On the other hand, a series circuit of a high resistance 7 and a capacitor 3 is connected to the drain 17 and the gate 16, and the output of the switch circuit 21 is connected to the ground through the capacitor 2. Note that resistors 6 and 7 have the same value,
Since the impedance is sufficiently large for alternating current signals, 1/2 of the voltage between the drain 17 and the source 18 is always applied to the gate 16 even when the contact 4 of the switch circuit 21 is closed or closed. ing. Also,
The capacitors 2 and 13 are required to have high insulation resistance and sufficiently low impedance to AC signals. The variable resistor with memory configured as described above has a simple configuration, and when the contact 4 of the switch circuit 21 is in the closed state, it can be positioned by the feedback resistors 7 and 6, and is linear with respect to the analog input voltage. It works properly.
更にスイッチ回路２１の接点４が閉状態（スイッチ回路
オン）及び開状態（スイッチ回路オフ）のいずれの場合
にもコンデンサー２及び１３並びに高抵抗６及び７の働
きにより歪高調波成分の少ない抵抗器として動作する。
更に、スイッチ回路がオフの時、コンデンサ１２及び１
３の充電効果とＭＯＳ型ＦＥＴの高入力抵抗との相互作
用により（ここでオフ時のスイッチ回路と、コンデンサ
１２及び１３の絶縁抵抗は非常に高いことが要求される
）、長時間安定にＭＯＳ型ＦＥＴは抵抗値出力素子とし
て動作する。一方、第４図は本発明による第２の実施例
である。Furthermore, whether the contact 4 of the switch circuit 21 is in the closed state (switch circuit on) or in the open state (switch circuit off), the resistor has low distortion harmonic components due to the functions of the capacitors 2 and 13 and the high resistances 6 and 7. operates as
Furthermore, when the switch circuit is off, capacitors 12 and 1
Due to the interaction between the charging effect of 3 and the high input resistance of the MOS type FET (here, the switch circuit when off and the insulation resistance of capacitors 12 and 13 are required to be very high), the MOS can be stably operated for a long time. The type FET operates as a resistance value output element. On the other hand, FIG. 4 shows a second embodiment according to the present invention.
この実施例では、オベアンプ３として、高入力抵抗とし
て知られるＭＯＳＦＥＴを入力段にしているオベアンプ
を選ぶ。一方、入力可変電圧は制御端子２２よりスイッ
チ回路２１の接点４を介して、オベアンプ３の十入力端
子１に印加する。更にスイッチ回路２１の出力をコンデ
ンサー２によって接地する。このような構成にするとオ
ベァンプ３の高入力抵抗とコンデンサ１２の充電電荷と
の働きにより、ＭＯＳ型ＦＥＴ５とオベアンプ３はスイ
ッチ回路２１がオン及びオフのいずれの場合にも閉ルー
プを構成しているので外乱による出力抵抗値の変動の著
しく抑圧された高安定な抵抗器となり、且つ従来のメモ
リ付可変抵抗器よりも構成が簡単になっている。なお、
この実施例の場合、抵抗値出力素子としてＭＯＳ型ＦＥ
Ｔ５を一例として説明したが、接合型ＦＥＴ等その他の
電圧制御形可変抵抗素子を用いてもよく、さらに電流制
御形可変抵抗素子である僕熱形サーミスタをも用いるこ
とができる。この場合、第４図の１７および１８間にサ
ーミスタを接続し、かつ１６からの電流を該サーミスタ
の傍の熱発生部に導くように接続すればよい。以上説明
したように、本発明によれば、従来のメモリ付可変抵抗
器よりも構成が簡単になる特徴を有するメモリ付電圧制
御形可変抵抗器が得られる。In this embodiment, as the OBE amplifier 3, an OBE amplifier whose input stage is a MOSFET known for its high input resistance is selected. On the other hand, the input variable voltage is applied from the control terminal 22 to the input terminal 1 of the oven amplifier 3 via the contact 4 of the switch circuit 21. Further, the output of the switch circuit 21 is grounded by a capacitor 2. With this configuration, the MOS type FET 5 and the amplifier 3 form a closed loop both when the switch circuit 21 is on and off due to the action of the high input resistance of the amplifier 3 and the charged charge of the capacitor 12. This is a highly stable resistor in which fluctuations in output resistance value due to disturbances are significantly suppressed, and the configuration is simpler than conventional variable resistors with memory. In addition,
In the case of this embodiment, a MOS type FE is used as the resistance value output element.
Although T5 has been described as an example, other voltage-controlled variable resistance elements such as a junction FET may be used, and furthermore, a self-heating type thermistor that is a current-controlled variable resistance element may also be used. In this case, a thermistor may be connected between 17 and 18 in FIG. 4, and the current from 16 may be connected to the heat generating section near the thermistor. As described above, according to the present invention, a voltage-controlled variable resistor with a memory can be obtained which has a feature that the configuration is simpler than the conventional variable resistor with a memory.
第１図は従来の電圧制御形可変抵抗器の回路構成図、第
２図は従来の電圧記憶回路の構成図、第３図は本発明に
よる第１の実施例のメモリ付電圧制御形可変抵抗器の回
路構成図、第４図は本発明による第２の実施例のメモリ
付電圧制御形可変抵抗器の回路構成図である。
１，１９・・・・・・オベアンプの入力端子、２，２０
・・・・・・可変抵抗値出力端子、３・・・・・・オベ
アンプ、４・・・・・・リレー接点、５・・…・ＦＥＴ
、６，７，８・・・・・・高抵抗、９…・・・定電圧源
、１０・・…・定電流源、１４，１５・…・・帰還抵抗
、１６・・・・・・ゲート端子、１７……ドレイン端子
、１８……ソース端子、１１，１２，１３……コンデン
サ、２１……スイツチ回路、２２・・・・・・制御端子
。
第１図
第２図
第３図
第４図FIG. 1 is a circuit configuration diagram of a conventional voltage-controlled variable resistor, FIG. 2 is a configuration diagram of a conventional voltage storage circuit, and FIG. 3 is a voltage-controlled variable resistor with memory according to the first embodiment of the present invention. FIG. 4 is a circuit diagram of a voltage-controlled variable resistor with memory according to a second embodiment of the present invention. 1, 19...Obe amplifier input terminal, 2, 20
...Variable resistance value output terminal, 3...Obe amplifier, 4...Relay contact, 5...FET
, 6, 7, 8... High resistance, 9... Constant voltage source, 10... Constant current source, 14, 15... Feedback resistor, 16... Gate terminal, 17...Drain terminal, 18...Source terminal, 11, 12, 13...Capacitor, 21...Switch circuit, 22...Control terminal. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
端子とを有する演算増幅器と、該演算増幅器の出力信号
を制御端に受ける電圧又は電流制御形可変抵抗素子と、
該可変抵抗素子に定電流を流すための定電流源と、該可
変抵抗素子の出力量を上記演算増幅器の第１の入力端子
に帰還させるための帰還回路とを有し、上記制御端子に
印加される電圧に応じた出力抵抗値が上記可変抵抗素子
の出力として得られるようにした電圧制御形可変抵抗素
子において、上記制御端子に印加される信号が断の時に
開くスイツチ回路と該スイツチ回路の出力および接地間
に接続されるコンデンサとを上記演算増幅器の第２の入
力端子の入力側に、あるいは上記演算増幅器の出力端子
と上記可変抵抗素子の上記制御端との間に、挿入接続し
、該コンデンサの充電電荷と該コンデンサの後続段の有
する高入力抵抗との相互作用による電圧記憶機能を付加
したことを特徴とする電圧制御形可変抵抗器。1: an operational amplifier having a first input terminal and a second input terminal connected to a control terminal; a voltage- or current-controlled variable resistance element whose control terminal receives an output signal of the operational amplifier;
a constant current source for causing a constant current to flow through the variable resistance element; and a feedback circuit for feeding back an output amount of the variable resistance element to a first input terminal of the operational amplifier; The voltage-controlled variable resistance element is configured such that an output resistance value corresponding to the voltage applied to the variable resistance element is obtained as the output of the variable resistance element, and the voltage-controlled variable resistance element includes a switch circuit that opens when the signal applied to the control terminal is disconnected, and a switch circuit that opens when the signal applied to the control terminal is disconnected. A capacitor connected between the output and ground is inserted and connected to the input side of the second input terminal of the operational amplifier, or between the output terminal of the operational amplifier and the control terminal of the variable resistance element, A voltage-controlled variable resistor characterized in that a voltage storage function is added by the interaction between the charge of the capacitor and a high input resistance of a stage subsequent to the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2664476A JPS6040208B2 (en) | 1976-03-13 | 1976-03-13 | Voltage controlled variable resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2664476A JPS6040208B2 (en) | 1976-03-13 | 1976-03-13 | Voltage controlled variable resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52110553A JPS52110553A (en) | 1977-09-16 |
| JPS6040208B2 true JPS6040208B2 (en) | 1985-09-10 |
Family
ID=12199145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2664476A Expired JPS6040208B2 (en) | 1976-03-13 | 1976-03-13 | Voltage controlled variable resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040208B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS64173Y2 (en) * | 1983-10-21 | 1989-01-05 |
-
1976
- 1976-03-13 JP JP2664476A patent/JPS6040208B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS64173Y2 (en) * | 1983-10-21 | 1989-01-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52110553A (en) | 1977-09-16 |
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