JPS603754A - Malfunction detector - Google Patents
Malfunction detectorInfo
- Publication number
- JPS603754A JPS603754A JP58112004A JP11200483A JPS603754A JP S603754 A JPS603754 A JP S603754A JP 58112004 A JP58112004 A JP 58112004A JP 11200483 A JP11200483 A JP 11200483A JP S603754 A JPS603754 A JP S603754A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- expected
- input
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は制御用電子計算機の誤動作検出装置に関する。[Detailed description of the invention] The present invention relates to a malfunction detection device for a control computer.
被制御装置からの入力信号から得られる情報を演算し被
制御装置の制御信号を出力する制御用電子計算機がある
。この様な制御用電子計算機において、周辺の装置から
発生するノイズ等、による論理誤演算、論理設計ミスか
ら生じる制御７スデムのデッドロック、暴走することが
ある。There is a control electronic computer that calculates information obtained from an input signal from a controlled device and outputs a control signal for the controlled device. In such a control electronic computer, deadlock or runaway of the control system may occur due to logic errors or logic design errors due to noise generated from peripheral devices.
従来の制御用電子計算機では、設計時に誤動作防止策を
組み込み、設計時に考慮した範囲の誤動作に対処可能で
あるが、制御用電子計算機が外部のノイズ等の誤動作や
、誤動作防止策から漏れた論理設計ミスから生じる制御
システムのデッドロックや暴走に対処する手段は備えて
おらず、誤動作が生じたら制御用電子計算機自体では対
処できないと言う欠点があった。Conventional control electronic computers incorporate malfunction prevention measures at the time of design and are able to deal with malfunctions within the scope of the design. There was no means to deal with deadlocks or runaways in the control system caused by design errors, and the control electronic computer itself was unable to deal with malfunctions.
本発明は上記の欠点を除去し、誤動作を検出する手段を
提供し、誤動作からの復旧対策を他のシステムに通知し
得るものである。The present invention eliminates the above drawbacks, provides means for detecting malfunctions, and can notify other systems of measures to recover from malfunctions.
本発明の制御用電子計算機の誤動作検出装置は、制御装
置の現時点での入力信号及び出力信号を記憶しこの条件
での期待制御出力値と制御装置のｆｌ制御出力を比較す
ることにより誤動作を検出する手段を備えて構成される
。The malfunction detection device for a control computer of the present invention stores the current input signal and output signal of the control device, and detects malfunction by comparing the expected control output value under these conditions with the fl control output of the control device. It is configured with means to do so.
次に本発明の実施例について図面を用いて説明する。第
１図は本発明の一実施例のブロック図、第２図は本発明
を説明するためのタイミングチャートである。被制御装
置（図示せず）からの入力信号１０を制御装置２からの
入力記憶指令２１により入力記憶装置１記憶し、その出
力である入力記憶信号１１け制御装置２及び期待出力装
置５の一方の入力となる。制御装置２０制御出力２０は
制御装置２の出力指令２２により出力装＠３に読み込ま
れ出力信号３０として被制御装置（図示せず）の制御出
力及び出力記憶装置４に入力記憶指令２１によって読み
込まれる。出力記憶装置４の出力である出力記憶信号４
０は期待出力装置５のもう一方の入力となる。期特出力
装ｊＶｉ−５は入力記憶信号１１及び出力記憶信号４０
の両方の入力から期待出力信号５０を出力する。期待出
力装置４０は入力記憶信号１１により制御装置２が演算
出力する制御出力信号２０の期待値を出力するものであ
る。出力判定装置６は出力信号３０と期待出力信号５０
を出立指令２２のタイミングで比較し、不一致により制
御装置２の誤動作を検出する。制御装置２から入力記憶
指令２１が１イ１のタイミングで発生したとき入力記憶
装置１には入力信号ＩＯが、出力記憶装置４０には出力
信号３０が記憶される。徊ｉｌｌ装蝕２は人力記憶信号
１１に対応する制御出力１１１号２０を出力する。制御
装置２の演算終了を示す出力指令２２が１０１のタイミ
ングで出力装置Ｎ ３１’ｃ出力されると、′イ１のタ
イミングで記憶した入力記憶信号１１と出力記憶信号４
０を入力とする期待出力装置５の期待出力５０と出力信
号３０ケ出力判定装置６により比較し誤動作検出信号６
（）を得る。μ（動作検出信号６０は１０１のタイミン
グでは期待出力５０と出力信号３０が等しく正常動作で
あることケ示し、“二１のタイミングでけ不−到であり
誤動作全検出した例を示す。期待出力装置べ５Ｖｉ制御
装置２の誤動作の検出するレベルに応じた期待値を出力
する。その期待値は制御装置２の動作から考えられる現
在の入力信号及び出力信号に対応した旬１特出力１＋ｊ
Ｌ ｋ示す様−な単純な配列表の様なものでも良い。記
入 ）出力信号紳数がＩＯ本程間であれば簡単に人手で
きる読出専用記憶装置やプログラマブルロジックアレー
等を用いることができる。Next, embodiments of the present invention will be described using the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the present invention. An input signal 10 from a controlled device (not shown) is stored in the input storage device 1 according to an input storage command 21 from the control device 2, and the input storage signal 11 is output from one of the control device 2 and the expected output device 5. becomes the input. The control output 20 of the control device 20 is read into the output device @3 by the output command 22 of the control device 2, and read into the control output and output storage device 4 of the controlled device (not shown) as an output signal 30 by the input storage command 21. . Output storage signal 4 which is the output of output storage device 4
0 becomes the other input of the expected output device 5. The special output device jVi-5 has an input storage signal 11 and an output storage signal 40.
The expected output signal 50 is output from both inputs. The expected output device 40 outputs the expected value of the control output signal 20 calculated and outputted by the control device 2 based on the input storage signal 11. The output determination device 6 outputs an output signal 30 and an expected output signal 50.
are compared at the timing of the departure command 22, and a malfunction of the control device 2 is detected due to a mismatch. When the input storage command 21 is generated from the control device 2 at a timing of 1-1, the input signal IO is stored in the input storage device 1, and the output signal 30 is stored in the output storage device 40. The wandering illumination device 2 outputs control outputs 111 and 20 corresponding to the human power storage signal 11. When the output command 22 indicating the end of the calculation of the control device 2 is outputted from the output device N 31'c at the timing 101, the input storage signal 11 and the output storage signal 4 stored at the timing 11 are output.
The expected output 50 of the expected output device 5 whose input is 0 is compared with the 30 output signals by the output determination device 6, and a malfunction detection signal 6 is obtained.
get (). μ (The operation detection signal 60 indicates that the expected output 50 and the output signal 30 are equal and normal operation at the timing 101, and shows an example in which the operation failed at the timing 21 and all malfunctions were detected.Expected output The device 5Vi outputs an expected value according to the level at which malfunction of the control device 2 is detected.The expected value is the seasonal 1 special output 1+j corresponding to the current input signal and output signal considered from the operation of the control device 2.
It may be something like a simple sequence list as shown in Lk. (Entry) If the number of output signals is about IO, a read-only storage device, a programmable logic array, etc., which can be easily handled manually, can be used.
この発明による誤動作検出装置を用いた制御用電子計算
機によれば外部のノイズ、論理エラー等による誤動作な
検出することが可能であり、誤まった情報処理による誤
動作を防止することが可能である。A control electronic computer using the malfunction detection device according to the present invention can detect malfunctions caused by external noise, logic errors, etc., and can prevent malfunctions caused by erroneous information processing.
以上詳細に説明して明らかな様に本発明によれば制御用
電子計算機に誤動作があれば検出しつる誤動作検出装置
が得られるのでオンライン制御用の監視システム等に大
変有効である。As is clear from the above detailed description, the present invention provides a malfunction detection device that can detect any malfunction in the control computer, and is therefore very effective for online control monitoring systems and the like.
第１図は本発明の一実施例のブロック図、第２図は本発
明を説明するためのタイミングチャートである。
なお図において、１−・・・・・入力記憶装置、２・・
・・・・制御装置、３・・・・・・出力装置％４・・・
・・・出力記憶装置、５・・・・・・期待出力装置、６
・・・・・・出力判定装置、１０・・・・・・入力信号
、２０・・・・・・制御出力信号、２１・・・・・・入
力記憶指令、２２・・・・・・出力指令、３０・・・・
・・出力信号、４０・・・・・・出力記憶信号、５０・
・・・・・期待出力信号、６０・・・・・・誤動作検出
信号、である。
代理人 弁理士 内 原 晋（１゛FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the present invention. In the figure, 1-...input storage device, 2...
...Control device, 3...Output device%4...
...Output storage device, 5...Expected output device, 6
...Output determination device, 10...Input signal, 20...Control output signal, 21...Input storage command, 22...Output Directive, 30...
...Output signal, 40...Output storage signal, 50.
. . . expected output signal, 60 . . . malfunction detection signal. Agent Patent Attorney Susumu Uchihara (1゛
Claims (1)
、第−及び第二の記憶手段の出力を人力とし現在の状態
から制御装置の次の時点の出力の期待信号と制御装置の
該時点の出力信号を比較することにより誤動作を検出す
る手段ヲ備えている事を特徴とする制御用電子計算機の
誤動作検出装置０The first storage means for storing the current input signal of the control device, and the outputs of the second and second storage means are manually inputted to calculate the expected signal of the next output of the control device from the current state and the corresponding output of the control device. Malfunction detection device 0 for a control electronic computer, characterized by comprising means for detecting malfunction by comparing output signals at a point in time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112004A JPS603754A (en) | 1983-06-22 | 1983-06-22 | Malfunction detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58112004A JPS603754A (en) | 1983-06-22 | 1983-06-22 | Malfunction detector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS603754A true JPS603754A (en) | 1985-01-10 |
Family
ID=14575546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58112004A Pending JPS603754A (en) | 1983-06-22 | 1983-06-22 | Malfunction detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2598532A1 (en) * | 1986-05-06 | 1987-11-13 | Thomson Csf | PROCESSOR FOR CALCULATING DISCRETE FOURIER TRANSFORMATION COMPRISING AN ONLINE TEST DEVICE |
-
1983
- 1983-06-22 JP JP58112004A patent/JPS603754A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2598532A1 (en) * | 1986-05-06 | 1987-11-13 | Thomson Csf | PROCESSOR FOR CALCULATING DISCRETE FOURIER TRANSFORMATION COMPRISING AN ONLINE TEST DEVICE |
| US5018091A (en) * | 1986-05-06 | 1991-05-21 | Thomson-Csf | Discrete fourier transform calculating processor comprising a real-time testing device |
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