JPS60254745A - Manufacture of complementary type dielectric isolating substrate - Google Patents
Manufacture of complementary type dielectric isolating substrateInfo
- Publication number
- JPS60254745A JPS60254745A JP59111311A JP11131184A JPS60254745A JP S60254745 A JPS60254745 A JP S60254745A JP 59111311 A JP59111311 A JP 59111311A JP 11131184 A JP11131184 A JP 11131184A JP S60254745 A JPS60254745 A JP S60254745A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- type single
- type
- island
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は、Ｐ型またはＮ型の一伝導型の単結晶島と、前
記−伝導型と反対の伝導型の単結晶島とが互いに分離さ
れて多結晶シリコンにより支持された、相補型誘電体分
離基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention provides a method in which a single crystal island of one conductivity type of P type or N type and a single crystal island of a conductivity type opposite to the above-mentioned - conductivity type are separated from each other. The present invention relates to a method for manufacturing a complementary dielectrically isolated substrate supported by polycrystalline silicon.
口、従来の技術
このような相補型誘電体分離基板の従来の製造方法を、
第２図（ａ）〜（ｇ）の断面図によシ説明する。The conventional manufacturing method of such complementary dielectric isolation substrate is
This will be explained with reference to the sectional views shown in FIGS. 2(a) to 2(g).
まず第２図（ａ）のように１両方位（１００）のＮ型単
結晶基板１を選択的にシリコン酸化膜でマスクし、アル
カリ溶液による異方性エツチングを行ないＮ型単結晶島
２を形成する。つぎに、同図（ｂ）のように％Ｎ型単結
晶島２以外の領域をシリコン酸化膜３とシリコン窒化膜
４でマスクし、Ｎ型不純物をイオン注入して不純物濃度
の高いＮ型単結晶島埋込轡５を形成する。つぎに、同図
（Ｃ）のように、選択酸化を行ないＮ型単結晶島２を１
．５μｍ程度のシリコン酸化膜６でマスクし、シリコン
酸化膜３とシリコン窒化膜４を除去し、Ｐ型不純物をド
ープしたエピタキシ・・ル成長により、Ｎ型単結晶島２
の高さより厚く、Ｐ型単結晶シリコン層７及び遷移領域
８と呼ばれる結晶欠陥の多い単結晶シリコン層を成長さ
せ、多結晶シリコン層９を堆積させる。つぎに同図（ｄ
）のように％Ｐ型単結晶シリコン層７をＮ型単結晶島２
と同程度の高さまで研削加工し、Ｐ型巣結晶島１１をシ
リコン酸化膜１ｏでマスクしてアルカリ溶液による異方
性エツチングを行ない、Ｐ型巣結晶島１１を形成する。First, as shown in FIG. 2(a), an N-type single-crystal substrate 1 with 100 layers is selectively masked with a silicon oxide film, and anisotropic etching is performed using an alkaline solution to form N-type single-crystal islands 2. Form. Next, as shown in Figure (b), the area other than the N-type single crystal island 2 is masked with a silicon oxide film 3 and a silicon nitride film 4, and N-type impurity ions are implanted to form an N-type single crystal island with a high impurity concentration. A crystal island embedded 5 is formed. Next, as shown in the same figure (C), selective oxidation is performed to reduce the N type single crystal islands 2 to 1
．． Masked with a silicon oxide film 6 of approximately 5 μm, the silicon oxide film 3 and silicon nitride film 4 are removed, and N-type single crystal islands 2 are grown by epitaxial growth doped with P-type impurities.
A single crystal silicon layer thicker than the height of , and having many crystal defects called a P-type single crystal silicon layer 7 and a transition region 8 is grown, and a polycrystalline silicon layer 9 is deposited. Next, the same figure (d
), the P-type single-crystal silicon layer 7 is replaced by the N-type single-crystal island 2.
The P-type nested crystal islands 11 are masked with a silicon oxide film 1o and anisotropically etched with an alkaline solution to form the P-type nested crystal islands 11.
つぎに同図ｔ６）のように、Ｐ型不純物をイオン注入し
て不純物濃度の高いＰ型単結晶島埋込層１２を形成する
。つぎに同図（ｆ）のように、Ｎ型及びＰ型の単結晶島
を２．５μｍ程度のシリコン酸化膜１３でマスクし、エ
ピタキシャル成長によシ、多結晶シリコン層１４を堆積
させる。つぎに同図（ｇ）のように、同図（ｆ）のＡＡ
’まで多結晶シリコン層１４を研削加工し、これを基準
として、Ｎ型単結晶島２とＰ型巣結晶島１１を分離する
ようにＢＢ／まで単結晶層を研削加工することによル、
相補型誘電体分離基板１５を得ることができる。Next, as shown at t6) in the figure, P-type impurity ions are implanted to form a P-type single crystal island buried layer 12 with a high impurity concentration. Next, as shown in FIG. 5F, the N-type and P-type single crystal islands are masked with a silicon oxide film 13 of about 2.5 μm, and a polycrystalline silicon layer 14 is deposited by epitaxial growth. Next, as shown in the same figure (g), the AA of the same figure (f)
By grinding the polycrystalline silicon layer 14 to ', and using this as a reference, grinding the single crystal layer to BB/ so as to separate the N-type single crystal island 2 and the P-type nested crystal island 11.
A complementary dielectric isolation substrate 15 can be obtained.
ハ１発明が解決しようとする問題点
上記の工程で単結晶島を作る時、エツチングの際、島の
四隅に発生する形状崩れを防ぐため、マスクパターンの
四隅に補償パターン（図示なし）を付けている。Ｎ型単
結晶島２では、補償パターンは単結晶層の上に位置する
が、Ｐ型巣結晶島１１の場合、多結晶シリコン層９が遷
移領域８の方にくい込むため、補償パターンが多結晶シ
リコン層９と遷移領域８及び単結晶シリコン層７の上に
位置する。このような状態でエツチングを行なうと、多
結晶シリコンに対するエッチ速度と単結晶シリコンに対
するそれが異なるため、顕著な形状崩れがＰ型巣結晶島
の隅のうち、Ｎ型単結晶島に隣接した所に起きるという
欠点が生じる。C1 Problems to be Solved by the Invention When forming single-crystal islands in the above process, compensation patterns (not shown) are attached to the four corners of the mask pattern in order to prevent deformation that occurs at the four corners of the islands during etching. ing. In the N-type single crystal island 2, the compensation pattern is located on the single crystal layer, but in the case of the P-type nested crystal island 11, the polycrystalline silicon layer 9 sinks into the transition region 8, so the compensation pattern is located on the polycrystalline layer. It is located on the silicon layer 9 , the transition region 8 and the single crystal silicon layer 7 . When etching is performed in such a state, the etch rate for polycrystalline silicon is different from that for single crystal silicon, so that the shape is noticeably distorted in the corners of the P-type nested crystal islands adjacent to the N-type single crystal islands. The disadvantage is that it occurs in
二０問題点を解決するためめ技術手段
本発明は、Ｐ型巣結晶島を形成する際、Ｎ型単結晶島の
上に作るマスクを、Ｎ型単結晶島の内側に狭め、エピタ
キシャル成長により作られる単結晶シリコン領域を実効
的に広げることによシ、上記欠点を解消し、Ｎ型単結晶
島とＰ型巣結晶島の形状を同程度に整えることができる
。20 Technical Means for Solving Problems The present invention, when forming P-type nested crystal islands, narrows the mask formed on the N-type single-crystal islands inside the N-type single-crystal islands, and forms them by epitaxial growth. By effectively expanding the single-crystal silicon region, the above-mentioned drawbacks can be overcome and the shapes of the N-type single-crystal islands and the P-type nested crystal islands can be adjusted to the same degree.
ホ、実施例 つぎに本発明を実施例により説明する。E, Example Next, the present invention will be explained by examples.
第１図（ａ）〜（ｄ）は本発明の一実施例の製造工程順
の基板断面図である。まず、第１図（ａ）のように、面
方位（１０６）のＮ型単結晶基板１を選択的にシリコン
酸化膜でマスクし、アルカリ溶液による異方性エツチン
グを行ない、Ｎ型単結晶島２を形成し、その周辺を５μ
ｍ程度残してＮ型単結晶島２をシリコン酸化膜１８でマ
スクする。つぎに同図（ｂ）のように％Ｐ型不純物をド
ープしたエピタキシャル成長により、Ｎ型単結晶島２の
高さよシ厚く、Ｐ型巣結晶シリコン鳩７及び遷移領域８
と呼ばれる結晶欠陥の多い単結晶層を成長させ、それ以
外□のＮ型単結晶島上に多結晶シリコン層９を堆積させ
る。従来技術による第２図（Ｃ）と比較して、第１図（
ａ）のマスクをＮ型単結晶島２の内側へ寄せた分だけ、
多結晶シリコン層９がＮ型単結晶島２の内側に狭まシ、
Ｐ型単結晶シリコン層７が外側へ広がり、遷移領域８も
Ｎ型単結晶島２の方へ移動する。従って、遷移領域を含
めたＰ型巣結晶シリコン領域は実効的に広がる。つぎに
第１図（Ｃ）ように、Ｐ型単結晶シリコン層７をＮ型単
結晶島２と同程度の高さまで研削加工し１選択的にシリ
コン酸化膜１０でマスクし、アルカリ溶液による異方性
エツチングを行ない、Ｐ型巣結晶島１１を形成する。FIGS. 1(a) to 1(d) are sectional views of a substrate in the order of manufacturing steps according to an embodiment of the present invention. First, as shown in FIG. 1(a), an N-type single-crystal substrate 1 with a plane orientation (106) is selectively masked with a silicon oxide film, and anisotropic etching is performed using an alkaline solution to form N-type single-crystal islands. 2 and the surrounding area with 5μ
The N-type single crystal island 2 is masked with a silicon oxide film 18, leaving about m. Next, as shown in the same figure (b), by epitaxial growth doped with % P-type impurity, the height of the N-type single crystal island 2 is increased, and the P-type nest crystal silicon dove 7 and the transition region 8 are grown.
A single crystal layer with many crystal defects called . . . is grown, and a polycrystalline silicon layer 9 is deposited on the other □ N-type single crystal islands. In comparison with FIG. 2(C) according to the prior art, FIG.
By the amount that the mask in a) is brought closer to the inside of the N-type single crystal island 2,
The polycrystalline silicon layer 9 is narrowed inside the N-type single crystal island 2,
The P-type single-crystal silicon layer 7 spreads outward, and the transition region 8 also moves toward the N-type single-crystal island 2 . Therefore, the P-type nested crystalline silicon region including the transition region is effectively expanded. Next, as shown in FIG. 1C, the P-type single-crystal silicon layer 7 is ground to the same height as the N-type single-crystal island 2, selectively masked with a silicon oxide film 10, and treated with an alkaline solution. Directional etching is performed to form P-type nested crystal islands 11.
前記第１図（ｂ）において、Ｐ型単結晶シリコン領域７
が実効的に広がったため、補償パターンはＰ型巣結晶シ
リコン領域の上に位置する。従って、エッチ速度に起因
する形状崩れがＰ型巣結晶島の隅のうち、特にＮ型単結
晶島２に隣接した所に発生することを防上できる。つぎ
に同図（ｄ）のように、同図ＩＣ）のシリコン酸化膜１
８，１０を除去した後、Ｐ型巣結晶島１１をシリコン酸
化膜１６．シリコン窒化膜１７でマスクし、Ｎ型不純物
をイオン注入して不純物濃度の高いＮ型単結晶島埋込層
５を形成する。その後、選択酸化によ）Ｎ型単結晶島２
を１．５μｍ程度のシリコン酸化膜でマスクし、それ以
外のシリコン酸化膜１６．シリコン窒化膜１７を除去し
て、Ｐ型不純物をイオン注入して不純物濃度の高いＰ型
巣結晶島埋込層を形成すると、第２図（ｅ）に示すと同
じ基板が得られる。さらに、従来技術と同様の方法によ
り、第２図（ｇ）に示す相補型誘電体分離基板１５を得
る。In FIG. 1(b), the P-type single crystal silicon region 7
has effectively expanded, so that the compensation pattern is located above the P-type nest crystalline silicon region. Therefore, it is possible to prevent deformation caused by the etch rate from occurring in the corners of the P-type nested crystal islands, particularly in the areas adjacent to the N-type single crystal islands 2. Next, as shown in the same figure (d), the silicon oxide film 1 of the same figure IC)
8 and 10, the P-type nest crystal island 11 is covered with a silicon oxide film 16. Masked with a silicon nitride film 17, N-type impurity ions are implanted to form an N-type single crystal island buried layer 5 with a high impurity concentration. Then, by selective oxidation) N-type single crystal island 2
is masked with a silicon oxide film of approximately 1.5 μm, and the remaining silicon oxide film 16. When the silicon nitride film 17 is removed and a P-type impurity is ion-implanted to form a P-type nested crystal island buried layer with a high impurity concentration, the same substrate as shown in FIG. 2(e) is obtained. Furthermore, a complementary dielectric isolation substrate 15 shown in FIG. 2(g) is obtained by a method similar to that of the prior art.
尚、上記実施例では、面方位（１００）を用いたが、他
の面方位、たとえば（１１１）でも構わないし、Ｎ型単
結晶基板の代わりにＰ型巣結晶基板を用いてもよい。In the above embodiments, the plane orientation (100) is used, but other plane orientations, such as (111), may be used, and a P-type nested crystal substrate may be used instead of the N-type single crystal substrate.
マスクを内側へ寄せてエピタキクヤル成長を行ない、単
結晶シリコン領域を実効的に広げることにより、Ｐ型巣
結晶島の隅のうち、Ｎ型単結晶島に隣接した領域におけ
る形状崩れの発生を防ぐ効果がある。By moving the mask inward to perform epitaxial growth and effectively expanding the single crystal silicon region, it is effective in preventing shape collapse in the region adjacent to the N type single crystal island among the corners of the P type nested crystal island. There is.
第１図＋８）〜（ｄ）は本発明の一実施例の製造工程順
の基板断面図、第２図（ａ）〜（ｇ）は従来の相補型誘
電体分離基板の製造工程順の基板断面図である。
１・・・・・・Ｎ型単結晶基板、２・・・・・・Ｎ型単
結晶島、３．６，１０，１３，１６．１８・・・・・・
シリコン酸化膜、４．１７・・・・・・シリコン窒化膜
、５・・・・・・Ｎ型単結晶島埋込層、７・・・・・・
Ｎ型単結晶シリコン層、８・・・・・・遷杉領域、９．
１４・・・・・・多結晶シリコン層、１１・・・・・・
Ｐ型巣結晶シリコン島、１２・・・・・・Ｐ型巣結晶島
埋込層、１５・・・・・・相補型誘電体分離基板。
茅 ｌ 図Figures 1+8) to (d) are cross-sectional views of a substrate in the order of manufacturing steps according to an embodiment of the present invention, and Figures 2(a) to (g) are substrates in the order of manufacturing steps of a conventional complementary dielectric isolation substrate. FIG. 1... N-type single crystal substrate, 2... N-type single crystal island, 3.6, 10, 13, 16.18...
Silicon oxide film, 4.17...Silicon nitride film, 5...N-type single crystal island buried layer, 7...
N-type single crystal silicon layer, 8... Sensugi region, 9.
14... Polycrystalline silicon layer, 11...
P-type nested crystal silicon island, 12... P-type nested crystalline island buried layer, 15... Complementary type dielectric isolation substrate. Kaya l figure
Claims (1)
ン酸化膜で選択的にマスクし、アルカリ溶液を用いた異
方性エツチングにより一伝導型の単結晶島を形成し、こ
の単結晶島の表面のうちの周辺を除いた残りの部分をシ
リコン酸化膜でマスクし、前記−伝導型と反対の伝導型
の不純物をドープしたエピタキシャル成長により、前記
−伝導型単結晶島の高さよりも厚く該−伝導型単結晶島
の方に広がった反対伝導型の単結晶領域を前記基板の斜
出表面上に成長させると共に、前記マスクしたー伝導型
単結晶島の上に多結晶シリコンを堆積させ、つぎに、前
記反対伝導型の単結晶領域を前記−伝導型単結晶島と同
程度の高さまで研削加工し、つぎに、シリコン酸化膜で
マスクし、アルカリ溶液を用いた異方性エツチングによ
り反対伝導型の単結晶島を作シ、それから、前記−伝導
型および反対板溝型の単結晶島の上のシリコン酸化膜を
除去し、つぎに選択イオン注入により、前記−伝導型お
よび反対伝導型単結晶島にそれぞれ島自身と同じ伝導型
の高濃度の埋込層を形成し、さらにエピタキシャル成長
により、前記−伝導型および反対伝導型の単結晶島の上
に厚いシリコン酸化膜を介して多結晶シリコンを堆積さ
せた後、この多結晶シリコン層を研削加工して前記−伝
導型および反対伝導型単結晶島を互いに分離することを
特徴とする相補型誘電体分離基板の製造方法。A P-type or N-type monoconductive single crystal semiconductor substrate is selectively masked with a silicon oxide film, and monoconductive single crystal islands are formed by anisotropic etching using an alkaline solution. The remaining part of the surface except for the periphery is masked with a silicon oxide film, and by epitaxial growth doped with an impurity of a conductivity type opposite to the -conductivity type, the silicon oxide film is formed to be thicker than the height of the -conductivity type single crystal island. - growing single-crystalline regions of opposite conductivity extending towards the conductivity-type single-crystal islands on the diagonal surface of the substrate, and depositing polycrystalline silicon on the masked conductivity-type single-crystal islands; Next, the opposite conductivity type single crystal region is ground to the same height as the − conductivity type single crystal island, and then masked with a silicon oxide film and anisotropically etched using an alkaline solution to reverse the etching process. A conduction type single crystal island is created, and then the silicon oxide film on the -conduction type and opposite plate groove type single crystal islands is removed, and then selective ion implantation is performed to form the -conduction type and opposite conduction type single crystal islands. A highly concentrated buried layer of the same conductivity type as the island itself is formed on each single crystal island, and then a polycrystalline layer is formed on the single crystal islands of the -conductivity type and the opposite conductivity type via a thick silicon oxide film by epitaxial growth. A method for manufacturing a complementary dielectric isolation substrate, characterized in that after silicon is deposited, the polycrystalline silicon layer is ground to separate the - conduction type and opposite conduction type single crystal islands from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59111311A JPS60254745A (en) | 1984-05-31 | 1984-05-31 | Manufacture of complementary type dielectric isolating substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59111311A JPS60254745A (en) | 1984-05-31 | 1984-05-31 | Manufacture of complementary type dielectric isolating substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60254745A true JPS60254745A (en) | 1985-12-16 |
Family
ID=14558007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59111311A Pending JPS60254745A (en) | 1984-05-31 | 1984-05-31 | Manufacture of complementary type dielectric isolating substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254745A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422299A (en) * | 1989-09-11 | 1995-06-06 | Purdue Research Foundation | Method of forming single crystalline electrical isolated wells |
-
1984
- 1984-05-31 JP JP59111311A patent/JPS60254745A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422299A (en) * | 1989-09-11 | 1995-06-06 | Purdue Research Foundation | Method of forming single crystalline electrical isolated wells |
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