JPS60252971A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS60252971A
JPS60252971A JP59109913A JP10991384A JPS60252971A JP S60252971 A JPS60252971 A JP S60252971A JP 59109913 A JP59109913 A JP 59109913A JP 10991384 A JP10991384 A JP 10991384A JP S60252971 A JPS60252971 A JP S60252971A
Authority
JP
Japan
Prior art keywords
address
line
memory
data
storage address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59109913A
Other languages
Japanese (ja)
Inventor
Toru Otsu
徹 大津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59109913A priority Critical patent/JPS60252971A/en
Publication of JPS60252971A publication Critical patent/JPS60252971A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to use a memory address in place of a bad memory position by holding a memory address when accessing a memory and an error of data is detected, and when access is made to the held memory address, converting to request to generated memory access and executing. CONSTITUTION:When access is made to a memory 1, a CPU2 designates an address by an address line 3, and gives and receives memory data by a data line 4. In the case of reading, data of address designated by an address line 5 are read out and transferred to a CPU1 by the data line 4 through a data line 10 and a bus control circuit 7, and at the same time, checking is made by a parity checking circuit 11. When an error is detected, a register 13 is controlled by a signal from a signal line 12 to hold the memory address containing error data. The content of the register 13 is sent to a magnitude judging circuit 20, and when it is equal to or larger than address from the CPU2, output is generated in a line 22. When there is output from a line 17, address from the CPU is made +1 in a circuit 24, and convesion address is supplied to the memory 1, and other address are supplied as they are.

Description

【発明の詳細な説明】 ｌａ＞産業上の利用分野 本発明は計算機記憶装置のアクセス制御に係り、特に障
害のある記憶位置を含む記憶装置を救済して、使用を続
けるための記憶装置アクセス制＜ｉｌ力弐に関する。Detailed Description of the Invention la > Industrial Application Field The present invention relates to access control of computer storage devices, and in particular to storage device access control for rescuing a storage device containing a faulty storage location and continuing its use. <Regarding il Riki 2.

多くの計算機では、主記憶装置等の障害による記憶デー
タの誤りを検出するために、パリティ方式に代表される
ような誤り検出機能を有する。Many computers have an error detection function, typified by a parity method, in order to detect errors in stored data due to failures in main storage devices or the like.

ところで、妥当な品質の計算機においては、多数の構成
部品が同時に障害になることは極めて稀であるから、記
憶装置で誤りが検出された場合にも、障害は例えば大量
の記憶素子中の１ビツトが不良になっており、障害部分
以外は続けて使用できる場合が多い。By the way, in a computer of reasonable quality, it is extremely rare for a large number of components to fail at the same time, so even if an error is detected in a storage device, the failure may be due to, for example, one bit in a large number of storage elements. In many cases, parts other than the defective part can be used continuously.

＋ｂｌ従来の技術 そのために、従来比較的大型の計算機システムでは、例
えば障害の検出された記憶アドレスを、含む適当なデー
タブロック単位で除外して使用するような制御が使用さ
れる場合があった。+bl PRIOR TECHNOLOGY For this reason, in conventional relatively large computer systems, control has been used in which, for example, a storage address in which a fault has been detected is excluded and used in units of appropriate data blocks.

又、記憶装置を複数の装置で構成し、障害が発生した場
合には、該当の部分装置を除いて記憶装置を再構成する
方式もしばしば用いられる。Furthermore, a method is often used in which a storage device is configured with a plurality of devices, and when a failure occurs, the storage device is reconfigured by excluding the relevant partial device.

しかし、経済的要求の厳しい比較的小型の計算機では、
大型機のような障害対策は採り難（、記せ装置に障害が
発生すると、不良部分を更新しない限り、計算機の正常
な使用ができなかった。However, for relatively small computers with strict economic requirements,
It is difficult to take measures against failures like those for large machines (if a failure occurred in the recording device, the computer could not be used normally unless the defective part was replaced).

（Ｃ１発明が解決しようとする問題点 本発明は、比較的小型の計算機でも不良記憶装置を救済
して計算機の利用を可能とする手段を提供することを目
的とする。(C1 Problems to be Solved by the Invention It is an object of the present invention to provide a means for repairing a defective storage device even in a relatively small-sized computer, thereby making the computer usable.

＋ｄ１問題点を解決するための手段 この目的は、記憶データの誤り検出機能を有する計算機
の記憶装置アクセスにおいて、該誤り検出されたデータ
の記憶アドレスを保持する手段、及び該保持する記憶ア
ドレスと異なる記憶アドレスを発生する手段を有し、上
記保持する記憶アドレスへのアクセス要求を上記発生し
た記憶アドレスへのアクセス要求に変換して実行するよ
うに構成されてなる本発明の記憶装置アクセス制御方式
によって達成される。+d1 Means for Solving the Problem This purpose is to provide a means for holding a storage address of data in which an error has been detected, and a storage address that is different from the storage address to be held, in accessing a storage device of a computer having a function of detecting errors in stored data. According to the storage device access control method of the present invention, the storage device access control method has means for generating a storage address, and is configured to convert an access request to the stored storage address into an access request to the generated storage address. achieved.

（ｅ）作用 即ち、記憶装置にアクセスしてデータの誤りが検出され
たとき、その記憶アドレスを保持しておき、その後その
計算機を再初期設定等して使用を再開する。(e) Effect: When the storage device is accessed and a data error is detected, the storage address is held, and then the computer is reinitialized and used again.

そこで、保持している記憶アドレスへのアクセス要求が
発生すると、保持しているアドレスと異なる記憶アドレ
スを発生して、該記憶アドレスで指示される記憶位置を
、不良記憶位置の代わりに使用するようにするので記憶
装置の使用をＦａ続することができ、従って殆ど正常状
態と変わりなく計算機の利用ができる。Therefore, when a request to access a stored storage address occurs, a storage address different from the stored address is generated, and the storage location specified by the storage address is used in place of the defective storage location. Therefore, the use of the storage device can be continued, and therefore the computer can be used almost as if it were in a normal state.

代替記憶アドレスの発生方式としては、例えば実施例と
して詳細に説明するように、不良記憶アドレス及びそれ
より大きな値の記憶アドレスを一定値だけ大きい値にシ
フトすることによって発生することができる。As a method of generating an alternative storage address, for example, as will be described in detail as an embodiment, the alternative storage address can be generated by shifting a defective storage address and a storage address with a larger value by a fixed value to a larger value.

（ｆ）実施例 図は本発明の一実施例を示す計算機のブロック図である
。図において、１は記憶装置、２は記憶装置１にデータ
の書込み／続出しアクセスの要求を発生する中央処理装
置（以下ＣＰＵという）である。(f) Embodiment diagram is a block diagram of a computer showing an embodiment of the present invention. In the figure, 1 is a storage device, and 2 is a central processing unit (hereinafter referred to as CPU) that generates a data write/continue access request to the storage device 1.

ＣＰＵ２は記憶装置ｌにアクセスするとき、アドレス線
３で記憶アドレスを指定し、データｖＡ４で記憶データ
を授受する。When the CPU 2 accesses the storage device 1, it specifies the storage address using the address line 3, and sends and receives storage data using the data vA4.

通常の状態では、アドレス線３の信号はそのままアドレ
ス線５へ伝達されて、記憶装置１を制御する。アクセス
制御線６で書込みアクセスが指定されている場合には、
ｃ　ｐ　ｕ、ｉからデータ線４、ハス制御回路７を経て
パリティ発生回路８に書込みデータが転送される。パリ
ティ発生回路８でパリティビットを付加してデータ線９
を経て記憶装置１へ転送され、指定のアドレスへ書込み
が行われる。In a normal state, the signal on the address line 3 is directly transmitted to the address line 5 to control the memory device 1. If write access is specified by access control line 6,
Write data is transferred from c p u,i to the parity generation circuit 8 via the data line 4 and the hash control circuit 7 . The parity generation circuit 8 adds a parity bit to the data line 9.
The data is then transferred to the storage device 1 through the process, and written to the specified address.

読出しの場合には、アドレス線５で指定される記憶アド
レスのデータが読み出されて、データ線１０、ハス制御
回路７を経て、データ線４でＣＰＵ１へ転送される。こ
のとき同時に、データ線ｌＯの続出しデータがパリティ
検査回路１１に入力される。In the case of reading, the data at the storage address specified by the address line 5 is read out and transferred to the CPU 1 via the data line 4 via the data line 10 and the hash control circuit 7. At the same time, successive data on the data line IO is input to the parity check circuit 11.

パリティ検査回路１１はデータのパリティを検査し、パ
リティ条件を満足しない場合には信号線１２に誤り信号
を出す。通常のシステムでは、この信号はＣＰＵ　２へ
送られ、この時の読出しデータを無効にする等の処理が
実行される。The parity check circuit 11 checks the parity of the data, and outputs an error signal to the signal line 12 if the parity condition is not satisfied. In a normal system, this signal is sent to the CPU 2, and processing such as invalidating the read data at this time is executed.

本発明においては、信号線１２の誤り信号がアドレス保
持手段であるレジスタ１３も制御し、そのときアドレス
線３にＣＰＵ　２から送られている記憶アドレス（誤り
データのある記憶アドレス）をレジスタ１３に保持させ
る。In the present invention, the error signal on the signal line 12 also controls the register 13 which is an address holding means, and at that time, the storage address (the storage address containing the error data) sent from the CPU 2 to the address line 3 is transferred to the register 13. hold it.

レジスタＩ３は例えば保持用の電池１４等の手段により
、この計算機の電源を切断しても保持するうにされ、必
要な場合にＣＰＵ　２からの制御線１５の信号によって
リセットされると、以後新しい値の設定が可能になるも
のとする。For example, the register I3 is maintained by a storage battery 14 or the like even when the power of this computer is turned off, and if necessary, it is reset by a signal on the control line 15 from the CPU 2, and then the new value is stored. It shall be possible to set the following.

レジスタ１３の内容は論理和ゲートＪ６を経て、該内容
が“Ｏ゛でないとき、信号線１７を°１゛にする。The contents of the register 13 pass through an OR gate J6, and when the contents are not "O", the signal line 17 is set to "1".

信号線１７はマルチプレクサ１８を制御する信号の１と
なり、これが°０゛の場合は、他の信号にかかわらず信
号線１９の信号をアドレス綿５へ通過させる。The signal line 17 becomes the signal 1 that controls the multiplexer 18, and when this is 0, the signal on the signal line 19 is passed to the address line 5 regardless of other signals.

即ち、ＣＰＵ　２から出される記憶アドレスがそのま＼
記憶装置１へ送られる。In other words, the memory address issued by CPU 2 remains unchanged.
The data is sent to storage device 1.

信号線１７に１゛があるときは、以下に述べる記憶アド
レスの切換えが有効になる。When the signal line 17 has 1, the storage address switching described below becomes effective.

レジスタ１３の内容は信号線２１で大小判定回路２０へ
も送られ、こ＼でアドレス線３でＣＰＵ　２から送られ
る記憶アドレスと比較される。大小判定回路２０はアド
レス線３から入力される値が信号１２１から入力される
値に等しいか、又は信号１２１の値より大きい場合に信
号線２２を１″　とし、その他の場合は°０゛　とする
機能を持つ。The contents of the register 13 are also sent to the magnitude determination circuit 20 via a signal line 21, where they are compared with the storage address sent from the CPU 2 via an address line 3. The magnitude determination circuit 20 sets the signal line 22 to 1'' when the value input from the address line 3 is equal to the value input from the signal 121 or larger than the value of the signal 121, and otherwise sets it to 0. It has the function of

信号線１７が°１゛の場合に、信号線２２が°０゛であ
れば、信号線１９の信号がアドレス線５へ通過し、信号
線２２が１”であれば信号線２３の信号がアドレス線５
へ通過する。If the signal line 17 is at 1'' and the signal line 22 is at 0, the signal on the signal line 19 passes to the address line 5, and if the signal line 22 is 1'', the signal on the signal line 23 is address line 5
pass to.

以上の制御により、信号線１７及び２２が共に１゛の場
合のみ、ＣＰＵ　２からアドレス＆’ｊｌ　３に送られ
た記憶アドレスが、アドレス発生回路２４で変換されζ
、アドレス１５へ伝達される。With the above control, only when the signal lines 17 and 22 are both 1, the storage address sent from the CPU 2 to the address &'jl 3 is converted by the address generation circuit 24.
, and is transmitted to address 15.

アドレス発生回路２４は、例えば入力に＋１し７た値を
信号線２３に出力する機能を有する。従って、ＣＰＵ　
２から送られる記憶アドレスがレジスタ１３に保持され
るアドレス以上の場合には、ずべζ１だけ大きい方ヘシ
フトされることになる。このソフト量は、要すれば１よ
り大きな４ｆｉとしてもよいことは、明らかであろう。The address generation circuit 24 has a function of outputting a value obtained by adding +1 to the input by 7 to the signal line 23, for example. Therefore, the CPU
If the storage address sent from No. 2 is greater than or equal to the address held in the register 13, it will be shifted to the larger address by ζ1. It will be obvious that this soft amount may be 4fi greater than 1, if desired.

又、誤り発生アドレス以上をすべてソフトするのではな
く、誤り発生アドレスのみを他のアトルス値（例えば、
その記憶装置の最終アドレス）へ変換するようにしても
よい。Also, rather than software all the addresses above the error occurrence address, only the error occurrence address is converted to other atlus values (for example,
(the final address of the storage device).

以上の説明ではレジスタ１３を保持する手段として電池
１４を用いることにしたが、電気的に書き換え可能な読
出し専用記憶値！　（ＥＦＲＯＭ）にレジスタ１３の内
容を書込む機構を設けζもよく、あるいはレジスタ１３
の内容を計算機の利用者に表示しておいて、電源再投入
後の初期にレジスタ１３に設定させる機構を設けてもよ
い。In the above explanation, the battery 14 was used as a means to hold the register 13, but the read-only memory value can be electrically rewritten! It is also possible to provide a mechanism to write the contents of register 13 to (EFROM), or
A mechanism may be provided to display the contents of the computer to the user of the computer and to set the contents in the register 13 at an early stage after the power is turned on again.

＋ｇ１発明の効果 以上の説明から明らかなように本発明によれば、計算機
の記憶装置の一部に障害があっても、その計算機を殆ど
正常状態と同様に稼動することができ、計算機の利用度
を向上すると言う著しい工業的効果がある。+g1 Effects of the Invention As is clear from the above explanation, according to the present invention, even if there is a failure in a part of the storage device of a computer, the computer can be operated almost in the same way as in a normal state, and the use of the computer can be improved. It has a remarkable industrial effect of improving the temperature.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例を示すブロック図である。 図において、 １は記憶装置、　２は中央処理装置、 ３はアドレス線、　４はデータ線、 ８はパリティ発生回路、１１はパリティ検査回路、１３
はアドレス保持用のレジスタ、 １８はマルチプレクサ、　２ｏは大小判定回路、２４は
アドレス発生回路を示す。 代理人　弁理士　検問　宏四部膨The figure is a block diagram showing one embodiment of the present invention. In the figure, 1 is a storage device, 2 is a central processing unit, 3 is an address line, 4 is a data line, 8 is a parity generation circuit, 11 is a parity check circuit, 13
18 is a multiplexer, 2o is a magnitude determination circuit, and 24 is an address generation circuit. Agent Patent Attorney Examiner Hiroshibu Hiroshi

Claims (1)

【特許請求の範囲】 ｆｌｌ記憶データの誤り検出機能を有する計算機の記憶
装置アクセスにおいて、該誤り検出されたデータの記憶
アドレスを保持する手段、及び該保持する記憶アドレス
と異なる記憶アドレスを発生する手段を有し、上記保持
する記憶アドレスへのアクセス要求を上記発生した記憶
アドレスへのアクセス要求に変換して実行するように構
成されてなることを特徴とする記憶装置アクセス制ｊＢ
方式。 （２）上記記憶アドレス発生手段は、上記保持する記憶
アドレス及びそれより大きな値の記憶アドレスに等しい
アクセス要求記憶アドレスに、一定値を加えて記憶アド
レスを発生することを特徴とする特許請求の範囲第ｆｉ
１項記載の記憶装置アクセス制御方式。[Scope of Claims] When accessing a storage device of a computer having a function of detecting errors in full storage data, means for holding the storage address of the error-detected data, and means for generating a storage address different from the storage address to be held. and is configured to convert the access request to the stored storage address into the generated access request to the storage address and execute the generated storage address access request.
method. (2) The storage address generating means generates a storage address by adding a fixed value to the access request storage address that is equal to the storage address to be held and a storage address with a larger value. No. fi
The storage device access control method according to item 1.
JP59109913A 1984-05-30 1984-05-30 Memory access control system Pending JPS60252971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59109913A JPS60252971A (en) 1984-05-30 1984-05-30 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59109913A JPS60252971A (en) 1984-05-30 1984-05-30 Memory access control system

Publications (1)

Publication Number Publication Date
JPS60252971A true JPS60252971A (en) 1985-12-13

Family

ID=14522316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59109913A Pending JPS60252971A (en) 1984-05-30 1984-05-30 Memory access control system

Country Status (1)

Country Link
JP (1) JPS60252971A (en)

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