JPS6025259A - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPS6025259A
JPS6025259A JP58133315A JP13331583A JPS6025259A JP S6025259 A JPS6025259 A JP S6025259A JP 58133315 A JP58133315 A JP 58133315A JP 13331583 A JP13331583 A JP 13331583A JP S6025259 A JPS6025259 A JP S6025259A
Authority
JP
Japan
Prior art keywords
semiconductor element
film substrate
thick
damp
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58133315A
Other languages
English (en)
Inventor
Hiroshi Miyazaki
博司 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58133315A priority Critical patent/JPS6025259A/ja
Publication of JPS6025259A publication Critical patent/JPS6025259A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、厚膜基板上に半導体素子をマウントワイヤポ
ンディングし、さらにコンデンサ等の素子と外部接続端
子を半田付して電気回路を形成し、防湿絶縁塗料で外装
した混成集積回路装置に関するものである。
最近の混成集積回路装置（以下ＨＩＣ）は高密度・軽量
・小型・高信頼性が要求されて（・る。第１図に従来の
ＨＩＣの断面図を示す。図にお（・て、厚膜基板１の上
に金属及びペースト剤で半導体素子２をマウントし、Ａ
Ｕ線ボンディング３を行ない接続をとる。その上にシリ
コン樹脂（フレキシブル）４を塗布し、後工程の半田付
のため半導体素子を保籐している。その後厚膜基板上に
、はんだ付固定の半導体素子５および受動体素子６を、
また、端子ランド７に外部端子８を半田ディツプ及びリ
フロ一方式で半田付をし、ＨＩＣ回路を形成する。さら
に、厚膜基板上のガラス部と外装エポキシ樹脂との密着
による厚膜基板上の抵抗部クラックを保護するため、バ
デファシリコン樹脂９を塗布し硬化させる。その上に外
装エポキシ樹脂（粉体）１０を高温で塗布し高温硬化を
行なってＨＩＣを完成させる。
このような従来のＨＩＣでは、半導体素子保護用のシリ
コン樹脂４がフレキシブルカため、ＨＩＣ組立組立数扱
〜・によってボンディングＡ　ｕ　線３の変形および断
線を発生させやす（・。また、シリコン樹脂のバッファ
剤９は粘度１０〜２０ＣＩ）Ｓのため流れやず＜、リー
ド線へのは（・上りのため耐湿性が悪くなる。さらに、
外装エポキシ１０と厚膜基板１との熱膨張差（エポキシ
樹脂４．ｌＸ１０　’　／ｃｍＣｓ厚膜基板６　Ｘ　１
０−’　／ｆｆ１Ｃ）によっ又熱ショック等の試験で樹
脂クラック及び基板クラックを発生しやす＜　４００＋
ａｍ％　１５ｍ以上の大きさでは、　例えば−３０Ｃ〜
８５Ｃ３０〜を保証できない。
本発明の目的は、半導体素子保護用のフレキシブルなシ
リコン樹脂の代わりに固さが５５蚊鼠シヨワーＤ）のエ
ポキシ樹脂を用い夕［部からの応力によってＡｕ線俊形
を発生せず、又熱ショック等の熱ストレスで樹脂クラッ
クを発生さぜな（・防湿絶縁塗料で外装した軽量・小型
及び簡易な構造のＨ工Ｃを提供するにある。
つぎに本発明を実施例により説明する一０第２図は本発
明の一実施例の断面図である。第２図において、厚膜基
板１に半導体素子２をマウントし、ＡｕＩｗ３をボンデ
ィングする。ボンディング線３を含めて半導体素子２を
、固さが５５以上（シ目ワーＤ）のエポキシ樹脂１１で
包み熱硬化させる。その後厚膜基板上にミニモールドト
ランジスタ５及びコンデンサ６などを、また端子ランド
７に外部端子８を、半田ディツプ及び１ノフロ一方式で
半田付をし、ＨＩＣ回路を構成する。それから、搭載部
品全部を含む厚膜基板１０表面に防湿絶縁塗料１２をデ
ィップ及びはけ塗りで塗布し熱硬化させる。その膜厚は
１００〜３００μｍ程度である。
上側においてエポキシ樹脂１１を、例えば、住Ｘ３Ｍ社
製、スコッチキャス）　＃２８１ヒ防湿絶縁塗料（日立
化成社製、ＴＦ−３３４０アクリル系）９を用いた場合
、熱ショック−３０ｔ？〜８Ｉ？、３０缶、及びＨＨＢ
Ｔ（８５ｔ：’　８５％１０（１０Ｈ）はクリアできる
。
本発明の混′ｅ、集積回路装置では半導体素子保護用の
シリコン樹脂の代わりに応力等に耐えうるエポキシ樹脂
を用い機械的強度と耐湿性をもたせ、外装を熱応力が小
さく、シリコンのバッファ剤の必要のない防湿絶縁塗料
を用いて熱シヨツク性を向上させ、よって軽量・小型及
び従来より簡易構造として、高い信頼性を有する効果が
得られる。
【図面の簡単な説明】
第１図は従来の混成集積回路装置の断面図、第２図は本
発明の一実施例の断面図である。 １・・・・・・厚膜基板（抵抗等焼成済）１．２・・・
・・・半導体素子、３・・・・・・ボンディングＡｕ線
、４・・・・・・プリコートシリコン樹脂、５・・・・
・・ミニモールドトランジスタ、６・・・・・・コンデ
ンサ、７・・・・・・端子ランド、８・・・・・・外部
端子、９・・・・・・バッファシリコン剤、１０・・・
・・・外装エポキシ樹脂、１１・・・・・・固（・保護
樹脂、１２・・・・・・防湿絶縁塗料。

Claims (1)

    【特許請求の範囲】
  1. 厚膜基板上に半導体素子をマウントし、さらにワイヤポ
    ンディングしたのち、前記ボンディングワイヤと共に前
    記半導体素子を前記ボンディング線の変形を生じないよ
    うな固い樹脂でグリコートし、つぎにこのプリコートし
    た半導体素子および前記厚膜回路基板に直接とり付けた
    回路部品に対し、ディップまたははけ塗りで外装の防湿
    塗料を塗布し、硬化させてなることを特徴とする混成集
    積回路装置。
JP58133315A 1983-07-21 1983-07-21 混成集積回路装置 Pending JPS6025259A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58133315A JPS6025259A (ja) 1983-07-21 1983-07-21 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58133315A JPS6025259A (ja) 1983-07-21 1983-07-21 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPS6025259A true JPS6025259A (ja) 1985-02-08

Family

ID=15101803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58133315A Pending JPS6025259A (ja) 1983-07-21 1983-07-21 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPS6025259A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63103000A (ja) * 1986-10-21 1988-05-07 ロンシール工業株式会社 装飾材およびその製造方法
JPH0269949A (ja) * 1988-09-05 1990-03-08 Nec Corp 混成集積回路装置の防湿処理方法
JPH04335556A (ja) * 1991-05-10 1992-11-24 Murata Mfg Co Ltd 混成集積回路
FR2685159A1 (fr) * 1991-12-17 1993-06-18 Matra Sep Imagerie Inf Procede de fabrication de circuits electroniques a micro-composants nus et circuit encapsule realisable par ce procede.

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5113625A (ja) * 1974-07-19 1976-02-03 Kubota Ltd Konbain
JPS5116259A (ja) * 1974-07-31 1976-02-09 Shin Meiwa Ind Co Ltd Jidoyosetsusochi
JPS51101862A (ja) * 1975-03-05 1976-09-08 Hitachi Ltd
JPS546699A (en) * 1977-06-14 1979-01-18 Stanley Electric Co Ltd Looking device
JPS5415167A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Thick film hybrid integrated circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5113625A (ja) * 1974-07-19 1976-02-03 Kubota Ltd Konbain
JPS5116259A (ja) * 1974-07-31 1976-02-09 Shin Meiwa Ind Co Ltd Jidoyosetsusochi
JPS51101862A (ja) * 1975-03-05 1976-09-08 Hitachi Ltd
JPS546699A (en) * 1977-06-14 1979-01-18 Stanley Electric Co Ltd Looking device
JPS5415167A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Thick film hybrid integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63103000A (ja) * 1986-10-21 1988-05-07 ロンシール工業株式会社 装飾材およびその製造方法
JPH0366160B2 (ja) * 1986-10-21 1991-10-16 Lonseal Kogyo Kk
JPH0269949A (ja) * 1988-09-05 1990-03-08 Nec Corp 混成集積回路装置の防湿処理方法
JPH04335556A (ja) * 1991-05-10 1992-11-24 Murata Mfg Co Ltd 混成集積回路
FR2685159A1 (fr) * 1991-12-17 1993-06-18 Matra Sep Imagerie Inf Procede de fabrication de circuits electroniques a micro-composants nus et circuit encapsule realisable par ce procede.

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