JPS6025158U - Simulation frame for synthetic resin molding - Google Patents

Simulation frame for synthetic resin molding

Info

Publication number
JPS6025158U
JPS6025158U JP11599183U JP11599183U JPS6025158U JP S6025158 U JPS6025158 U JP S6025158U JP 11599183 U JP11599183 U JP 11599183U JP 11599183 U JP11599183 U JP 11599183U JP S6025158 U JPS6025158 U JP S6025158U
Authority
JP
Japan
Prior art keywords
synthetic resin
resin molding
frame
simulation frame
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11599183U
Other languages
Japanese (ja)
Other versions
JPH0126110Y2 (en
Inventor
湯浅 敬昭
Original Assignee
ロ−ム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ロ−ム株式会社 filed Critical ロ−ム株式会社
Priority to JP11599183U priority Critical patent/JPS6025158U/en
Publication of JPS6025158U publication Critical patent/JPS6025158U/en
Application granted granted Critical
Publication of JPH0126110Y2 publication Critical patent/JPH0126110Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はトランジスタ用リードフレームの平面図、第2
図は前記リードフレームとモールド金型との位置関係を
示す平面図、第3図は第2図の■−I線拡大断面図、第
4図は第3図のTV−IV線拡大断面図、第5図はトラ
ンジスタ用模擬フレームの平面図、第6図は模擬フレー
ムとモールド金型の位置関係を示す平面図、第7図は第
6図の■−■線拡大断面図、第8図はIC用リードフレ
ームの平面図、第9図はリードフレームと製品部との位
置関係を示す平面図、第10図は第9図のX−X線視で
示す拡大断面図、第11図はIC用模擬フレームの平面
図、第12図は第11図のX■−X■線断面図、第13
図は模擬フレームと製品との位置関係を示す平面図、第
14図は第13図のXIV−XIV線拡大断面図である
。 1.20・・・・・・製品用リードフレーム、7,8・
・・・・・モールド金型、27.28・・・・・・モー
ルド金型、11.11’・・・・・・段付き合せ面、2
9.29’・・・・・・段付き合せ面、12.32・・
・・・・模擬フレーム、14.35・・・・・・栓板部
Figure 1 is a plan view of a transistor lead frame, Figure 2 is a plan view of a lead frame for a transistor.
The figure is a plan view showing the positional relationship between the lead frame and the mold die, FIG. 3 is an enlarged sectional view taken along the line ■-I in FIG. 2, and FIG. 4 is an enlarged sectional view taken along the line TV-IV in FIG. Figure 5 is a plan view of a simulated transistor frame, Figure 6 is a plan view showing the positional relationship between the simulated frame and the mold, Figure 7 is an enlarged sectional view taken along the line ■-■ in Figure 6, and Figure 8 is a plan view showing the positional relationship between the simulated frame and the mold. A plan view of a lead frame for IC, FIG. 9 is a plan view showing the positional relationship between the lead frame and the product part, FIG. 10 is an enlarged sectional view taken along line X-X in FIG. 9, and FIG. 11 is an IC lead frame. Fig. 12 is a sectional view taken along the line X--X in Fig. 11, Fig.
The figure is a plan view showing the positional relationship between the simulated frame and the product, and FIG. 14 is an enlarged sectional view taken along the line XIV-XIV in FIG. 13. 1.20... Lead frame for products, 7,8.
...Mold die, 27.28...Mold die, 11.11'...Stepped mating surface, 2
9.29'・・・Stepped surface, 12.32...
...Mock frame, 14.35...Plug plate part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子部品の製品部を樹脂モールドする一対の合せモール
ド金型に対し着脱自在に装着する模擬フレームに、前記
両金型のキャビティより外側に形成した段付き合せ面に
て挟着される栓板部を形成し、該栓坂部を前記キャビテ
ィ内に突出させない−ように構成して成る合成樹脂モー
ルド成型用模擬フレーム。
A plug plate portion is sandwiched between a stepped mating surface formed on the outside of the cavity of both molds, and is attached to a mock frame that is detachably attached to a pair of mating mold molds for resin-molding a product part of an electronic component. A simulated frame for synthetic resin molding, which is configured such that the stopper slope portion does not protrude into the cavity.
JP11599183U 1983-07-25 1983-07-25 Simulation frame for synthetic resin molding Granted JPS6025158U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11599183U JPS6025158U (en) 1983-07-25 1983-07-25 Simulation frame for synthetic resin molding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11599183U JPS6025158U (en) 1983-07-25 1983-07-25 Simulation frame for synthetic resin molding

Publications (2)

Publication Number Publication Date
JPS6025158U true JPS6025158U (en) 1985-02-20
JPH0126110Y2 JPH0126110Y2 (en) 1989-08-04

Family

ID=30267563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11599183U Granted JPS6025158U (en) 1983-07-25 1983-07-25 Simulation frame for synthetic resin molding

Country Status (1)

Country Link
JP (1) JPS6025158U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117222A (en) * 1982-12-24 1984-07-06 Hitachi Ltd Dummy lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117222A (en) * 1982-12-24 1984-07-06 Hitachi Ltd Dummy lead frame

Also Published As

Publication number Publication date
JPH0126110Y2 (en) 1989-08-04

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