JPS60247954A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60247954A JPS60247954A JP59102562A JP10256284A JPS60247954A JP S60247954 A JPS60247954 A JP S60247954A JP 59102562 A JP59102562 A JP 59102562A JP 10256284 A JP10256284 A JP 10256284A JP S60247954 A JPS60247954 A JP S60247954A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- polyimide
- terminal
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は感光性ポリアミドを使用した半導体装置、特に
その配線端子部位置認識技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device using photosensitive polyamide, and particularly to a technology for recognizing the position of a wiring terminal portion thereof.
近年、トランジスタ、ＩＣあるいはＬＳＩにおいて、そ
の保護膜としであるいは、多層配線間の絶縁膜としてポ
リイミド系樹脂が注目されている。In recent years, polyimide resins have been attracting attention as protective films for transistors, ICs, and LSIs, or as insulating films between multilayer interconnections.
ポリイミド系樹脂は耐熱性がすぐれていることの他にシ
リコンの酸化物や窒化物などの無機系絶縁膜材に比べて
平坦化が容易であり、さらに製品の歩留りや信頼性が高
いなどの多くの利点を有する。In addition to its excellent heat resistance, polyimide resin is easier to flatten than inorganic insulating film materials such as silicon oxides and nitrides, and it also has many advantages such as high product yield and reliability. It has the following advantages.
このポリイミド膜を最終保護膜に使用してＩＣやＬＳＩ
を製造する場合、配線の端子部は外部への電極取出しの
ため忙、その上のポリイミド膜をホトレジスト技術によ
り取除き、この部分に対して金線などを接続する「ワイ
ヤボンディング」を行うのが普通である。This polyimide film is used as the final protective film for IC and LSI.
When manufacturing, the terminal part of the wiring is used to take out the electrode to the outside, so the polyimide film on it is removed using photoresist technology, and "wire bonding" is performed to connect gold wire etc. to this part. It's normal.
ポリイミド膜は通常、透明又は半透明な被膜として形成
され、ワイヤボンディングにあたっては、この透明又は
半透明の膜を通して見える配線形状からポンディング部
のパターンを認識してボンディング位置決めを行ってい
る。しかし、ポリイミド膜が半透明、又は透明に近いこ
とによりパターン認識に不確実さを伴うことがわかった
。A polyimide film is usually formed as a transparent or semi-transparent film, and in wire bonding, the bonding position is determined by recognizing the pattern of the bonding part from the wiring shape seen through the transparent or semi-transparent film. However, it has been found that pattern recognition is accompanied by uncertainty because the polyimide film is semitransparent or nearly transparent.
このようなポリイミド系樹脂は、また、従来の多層配線
層間絶縁膜形成プロセスの合理化を目的に、ホトレジス
トと絶縁膜の機能を併せもつ感光性耐熱材料としての開
発もすすみ、相次いでその結果が発表されている（日経
エレクトロニクス、１９８１年７月２０日号ｐ−８８
）。These polyimide resins are also being developed as photosensitive heat-resistant materials that have both the functions of photoresists and insulating films, with the aim of streamlining the conventional multilayer wiring interlayer insulating film formation process, and the results have been announced one after another. (Nikkei Electronics, July 20, 1981 issue, p-88)
).
本発明の目的は感光性のポリイミド系樹脂の特性を利用
して半導体装置におけるボンディング部の認識精度を高
めること忙ある。An object of the present invention is to improve the accuracy of recognizing bonding portions in semiconductor devices by utilizing the characteristics of photosensitive polyimide resin.
他の目的はボンディングにおいてセンサによる自動位置
決めを可能にした半導体製造技術の提供にある。Another object of the present invention is to provide a semiconductor manufacturing technology that enables automatic positioning using sensors during bonding.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述及び添付図面よりあきらかになるであろ
う。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the attached drawings.
本願において開示される発明のうち代表的なものの概要
を簡単忙説明すれば下記の通りである。A brief summary of typical inventions disclosed in this application is as follows.
すなわち、半導体基体の一生面に半導体素子を形成し、
上記基体表面上に上記半導体素子に接続する配線を形成
し、上記半導体素子及び配線を覆うように着色又は不透
明化した感光性ポリイミド膜を形成し、この感光性ポリ
イミド膜の一部を露光し現像処理した後、熱処理を施す
ことにより上記配線の外端子部を露出する絶縁被膜を形
成し、然る後、上記配線外端子部表面と上記着色又は不
透明化した絶縁膜との反射度の差から上記配線外端子位
置を光学的に認識しながら上記配線端子と外部の端子と
の間のワイヤ接続を行うもので、これによりボンディン
グ作業が容易になり、さらにセンサによる自動位置決め
を実現できる。That is, a semiconductor element is formed on the entire surface of a semiconductor substrate,
Wiring connected to the semiconductor element is formed on the surface of the substrate, a colored or opaque photosensitive polyimide film is formed to cover the semiconductor element and the wiring, and a part of the photosensitive polyimide film is exposed and developed. After the treatment, heat treatment is performed to form an insulating film that exposes the external terminal portion of the wiring, and then, from the difference in reflectance between the surface of the external terminal portion of the wiring and the colored or opaque insulating film, The wire connection between the wiring terminal and an external terminal is performed while optically recognizing the position of the terminal outside the wiring, which facilitates the bonding work and further enables automatic positioning using a sensor.
第１図［ａｌ〜ｆｇｌは本発明による一実施例を示すも
のであって半導体装置においてポリイミド膜形成工程の
７０チヤート（計画図）である。FIG. 1 [al to fgl] shows one embodiment of the present invention, and is a 70 chart (planned diagram) of a polyimide film forming process in a semiconductor device.
第２図乃至第６図は第１図１ａｌ〜（ｇ］に対応する工
程断面図である。FIGS. 2 to 6 are process cross-sectional views corresponding to FIGS. 1A to 1G.
以下各工程にしたがって詳述する。Each step will be explained in detail below.
ｔａｌ シリコン半導体基板１の表面に不純物を選択導
入し、半導体素子を形成する。次に、該素子の電極とな
る部分のシリコン酸化物（ＳｊＯ＊）膜２を通常のホト
リングラフィ技術を用いて開窓する。tal Impurities are selectively introduced into the surface of the silicon semiconductor substrate 1 to form a semiconductor element. Next, a window is opened in the silicon oxide (SjO*) film 2 in the portion that will become the electrode of the device using a normal photolithography technique.
アルミニウム膜を基板ｌ上に蒸着法（又はスパッタ法）
により形成し、ホトレジスト処理を行なって、バターニ
ングしてアルミニウム配線３を形成する（第２図参照）
。Evaporation method (or sputtering method) of aluminum film on substrate l
The aluminum wiring 3 is formed by photoresist treatment and patterning (see Fig. 2).
.
ｌｂｌ 感光性ポリイミドのフェスを基板表面に塗布す
る。この感光性ポリイミドは本出願人により開発された
全芳香族系ポリアミドの前駆体にビスアジドなどの感光
基を結合させたものであり、たとえばポリアミド酸、ビ
スアジド光架橋剤、炭素−炭素二重結合を有するアミン
化合物、分子内に１個以上の水酸基を含４かつその沸点
が常圧で１５０℃以上の化合物から成る感光性重合体組
成物であって、ポリアミド酸の構造が一般式（下記の〔
１〕）の繰り返し単位で表わされるポリアミド酸を用い
るものである。lbl Apply a photosensitive polyimide face to the substrate surface. This photosensitive polyimide is made by bonding a photosensitive group such as bisazide to a fully aromatic polyamide precursor developed by the applicant. A photosensitive polymer composition comprising an amine compound having one or more hydroxyl groups in the molecule and a boiling point of 150°C or higher at normal pressure, wherein the structure of the polyamic acid is the general formula (the following [
A polyamic acid represented by the repeating unit 1) is used.
（但し、Ｒ′は２価の芳香族環含有有機基又はケイ素含
有有機基を表わす。）
注目すべき感光性ポリイミド樹脂の特徴は、ビスアジド
光架橋剤の量を変化させるだけで感光性ポリイミド樹脂
の色を自由忙変化させることができるということである
。(However, R' represents a divalent aromatic ring-containing organic group or a silicon-containing organic group.) The noteworthy feature of photosensitive polyimide resin is that it can be made into photosensitive polyimide resin by simply changing the amount of bisazide photocrosslinking agent. This means that you can change the color at will.
すなわち、光の透過性を自由に変化させることができる
ため、感光性ポリイミド樹脂の有無を容易に認識するこ
とができるということである。That is, since the light transmittance can be freely changed, the presence or absence of the photosensitive polyimide resin can be easily recognized.
フェス中の樹脂濃度１４重量％、粘度３ｏポアズ、塗布
は回転数３００ Ｏｒ ｐｍ で３０秒間スピンナによ
り行う。塗布後８５±５℃で２０分プリベークして上記
フェスを乾燥させる。この時の感光性ポリイミド４の膜
厚は、約４．５μｍである（第３図参照）。The resin concentration in the face was 14% by weight, the viscosity was 3o poise, and the coating was carried out using a spinner at a rotational speed of 300 Or pm for 30 seconds. After coating, prebaking is performed at 85±5° C. for 20 minutes to dry the above-mentioned face. The film thickness of the photosensitive polyimide 4 at this time is about 4.5 μm (see FIG. 3).
ｔｅｌ この後、第４図に示すようにマスク５を通して
紫外線をフェスに照射し露光を行う。露光エネルギーと
して２’ ＯＯｍｊ／ ｃｍ”が適当である。tel Thereafter, as shown in FIG. 4, the mask is exposed to ultraviolet light through a mask 5. A suitable exposure energy is 2'OOmj/cm''.
＋ｄｌ 現像を行って感光性ポリイミド４の未露光部分
を除去し、たとえば第５図に示すように配線３の一部が
露出するようにスルーホール８をあける。+dl development is performed to remove the unexposed portions of the photosensitive polyimide 4, and for example, as shown in FIG. 5, a through hole 8 is opened so that a part of the wiring 3 is exposed.
このときの現像液はノルマル・メチル拳ピロリドン（Ｎ
ＭＰと称す）：水＝４二１（容積比）組成のものを用い
２５℃で１ｏ分間浸漬する。このときの感光性ポリイミ
ド６の膜厚は約４μｍである。The developer at this time was normal methylpyrrolidone (N
(referred to as MP): water having a composition of 421 (volume ratio) and immersed at 25° C. for 10 minutes. The film thickness of the photosensitive polyimide 6 at this time is about 4 μm.
この後、現像処理した半導体基板をＮＭＰ ：水＝１
： Ｉの混合液に浸して洗浄を１分相度行い、感光性ポ
リイミドの溶は残った部分を除去する。After this, the developed semiconductor substrate was subjected to NMP:water=1
: Immerse in the mixture of I and wash for 1 minute to remove the remaining photosensitive polyimide solution.
つづいて、水のみによる洗浄を２０〜３０分行い感光性
ポリイミド膜表面の異物を完全になくす。Subsequently, cleaning with only water is performed for 20 to 30 minutes to completely eliminate foreign substances on the surface of the photosensitive polyimide film.
最後に熱処理を行うことにより感光性ポリイミド中の感
光基を揮散させるとともに重合硬化させて第５図に示す
ようにパターン化したポリイミド膜７を得る。この熱処
理にあたっては、まず１８０±２０℃で３０分間ベーキ
ングし、次いで窒素雰囲気中で４００±５℃で６０分キ
ュアな行う。第６図は第５図に対応する平面図であって
、着色又は不透明のポリイミド膜７にあけられたスルー
ホール８を通し配線３の端子部３ａがポンディングパッ
ドとして露出する形態を示し又いる。Finally, heat treatment is performed to volatilize the photosensitive groups in the photosensitive polyimide and polymerize and harden it, thereby obtaining a patterned polyimide film 7 as shown in FIG. In this heat treatment, first, baking is performed at 180±20° C. for 30 minutes, and then curing is performed at 400±5° C. for 60 minutes in a nitrogen atmosphere. FIG. 6 is a plan view corresponding to FIG. 5, and also shows a form in which the terminal portion 3a of the wiring 3 is exposed as a bonding pad through a through hole 8 made in a colored or opaque polyimide film 7. .
ｔｅｌ この後、図示されないが、ウェハ状の半導体基
板をスフ２イビングによりベレット化し、個々のベレッ
トをバクケージへの組立工程に送す。すなわち、第７図
に示すように、タブ９と複数のり一部１０を一体に形成
したリードフレームを用意し、タブ９の上に前記ベレッ
ト１１を銀ベースト等により接続（ベレットボンディン
グ）する。tel After that, although not shown in the drawings, the wafer-shaped semiconductor substrate is formed into pellets by swiping, and each pellet is sent to an assembly process into a bag cage. That is, as shown in FIG. 7, a lead frame in which a tab 9 and a plurality of adhesive portions 10 are integrally formed is prepared, and the bullet 11 is connected to the tab 9 using a silver base or the like (bullet bonding).
げノ つづいて第８図に示すようにベレット１１におけ
るポンディングパッドとり一部１０との間をワイヤ１２
を介して接続（ワイヤボンディング）を行う。このワイ
ヤボンディングにあたっては、第６図に示したようにポ
ンディングパッドとなる配ｌｓ端子部分３ａはその周囲
の着色され又は不透明化されたポリイミド膜と明確に識
別できることから、ボンディングの位置決めが容易とな
る。Next, as shown in FIG.
Connection (wire bonding) is made via. In this wire bonding, as shown in FIG. 6, the wiring terminal portion 3a that becomes the bonding pad can be clearly distinguished from the colored or opaque polyimide film surrounding it, making it easy to position the bonding. Become.
第９図は自動位置決めボンディング装置の要部を示す斜
視図である。ボンディング位置決めはセンサーを用い自
動的忙決定されワイヤーボンディングが行なわれる場合
の例を示す。同図に示すように光源１３より出た光はポ
ンディングパッド（３ａ）にあたって反射し受光部（セ
ンサ）１４で受けられる。次にセンサ１４からの情報は
受光回路１５に入り、次にパターンの白黒をオン・オフ
伯号忙変える二値化回路１６で白のところに位置合せす
るような信号を発生させ、ポンチインク動作制御回路１
７を経てボンダ１８をワイヤボンディング動作させる。FIG. 9 is a perspective view showing the main parts of the automatic positioning bonding device. An example is shown in which bonding positioning is automatically determined using a sensor and wire bonding is performed. As shown in the figure, the light emitted from the light source 13 hits the bonding pad (3a), is reflected, and is received by the light receiving section (sensor) 14. Next, the information from the sensor 14 enters the light receiving circuit 15, which then generates a signal to align with the white part in the binarization circuit 16, which changes the black and white of the pattern on and off, and performs the punch ink operation. Control circuit 1
7, the bonder 18 is operated for wire bonding.
ｔｇｌ 最後に樹脂モールドを行い、ベレット全体を封
止することにより半導体装置が完成する。tgl Finally, the semiconductor device is completed by performing resin molding and sealing the entire pellet.
〔効 果コ
感光性ポリイミド樹脂は感光基（ビスアジド）の量を変
えることにより透明度のコントロールが可能で、感光基
の量を増すことにより黒色化し、ポリイミドの光透過性
がなくなる。したがって感光性ポリイミドを最終保ｌ！
膜として用いることにより、ポンディングパッド位置の
認識精度が、従来の透明被膜を用いる場合に比して飛躍
的に向上し、センサによる自動位置決めボンディングを
可能ならしめ、その結果、組立コストの節減に有利とな
った。[Effects] Transparency of photosensitive polyimide resin can be controlled by changing the amount of photosensitive groups (bisazide); increasing the amount of photosensitive groups turns black, and the light transmittance of polyimide disappears. Therefore, the final protection for photosensitive polyimide!
By using it as a film, the recognition accuracy of the bonding pad position is dramatically improved compared to the case of using a conventional transparent film, making it possible to perform automatic positioning bonding using a sensor, and as a result, reducing assembly costs. It was advantageous.
本発明はＩＣ及び単体トランジスタを含めた半導体装置
全般に適用することができる。The present invention can be applied to all semiconductor devices including ICs and single transistors.
第１図は本発明による半導体装置製造プロセスの例を示
すフロチャートである。
第２図は本発明の一実施例を示すものであって半導体装
置の一部工程断面図、
第３図は同じく感光性ポリイミドを塗布した状態を示す
断面図、
第４図は同じく露光状態を示す断面図、第５図は同じく
現象状態を示す断面図、第６図はｊＩ５図に対応する一
部平面図である。
第７図は同じくペレット付けを示す断面図、第８図は同
じくワイヤボンディングした状態を示す断面図、
第９図は本発明による自動位置決めボンディングの一実
施形態を示す斜面図（一部回路図）である。
１・・・半導体基体、２・・・酸化膜、３・・・アルミ
ニウム配線、４・・・感光性ポリイミド被膜、５・・・
マスク、７・・・パターン化したポリイミド膜、８・・
・スルーホール、９・・・タブ、１０・・・リード、１
１・・・ペレット、１２・・・ワイヤ、１３・・・光源
、１４・・・センサ、１５・・・受光回路、１６・・・
二値化回路、１７・・・制御回路、第 １ 図
第 ２ 図
第 ４ 図
第 ６ 図
第 ７ 図
第 ８ 図FIG. 1 is a flow chart showing an example of a semiconductor device manufacturing process according to the present invention. FIG. 2 shows an embodiment of the present invention, and is a cross-sectional view of a part of the process of a semiconductor device, FIG. 3 is a cross-sectional view showing a state in which photosensitive polyimide is applied, and FIG. 4 shows a state in which it is exposed to light. FIG. 5 is a sectional view similarly showing the phenomenon state, and FIG. 6 is a partial plan view corresponding to FIG. jI5. FIG. 7 is a sectional view showing pellet attachment, FIG. 8 is a sectional view showing wire bonding, and FIG. 9 is a perspective view (partial circuit diagram) showing an embodiment of automatic positioning bonding according to the present invention. It is. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Oxide film, 3... Aluminum wiring, 4... Photosensitive polyimide coating, 5...
Mask, 7... Patterned polyimide film, 8...
・Through hole, 9...Tab, 10...Lead, 1
DESCRIPTION OF SYMBOLS 1... Pellet, 12... Wire, 13... Light source, 14... Sensor, 15... Light receiving circuit, 16...
Binarization circuit, 17...Control circuit, Fig. 1 Fig. 2 Fig. 4 Fig. 6 Fig. 7 Fig. 8
Claims (1)
体素子と、上記主面上に上記素子に接続された配線及び
上記素子及び配線を覆い、上記配線外端子部を露出する
ように形成された耐熱性絶縁被膜とを有する半導体装置
であって、上記耐熱性絶縁被−光性ポリイミドから成り
上記配線外端子部の位置を光学的に認識できる程度に着
色され又は不透明化されていることを％徴とする半導体
装置。 ２ 半導体基体の一生面に半導体素子を形成する工程、
上記基体表面上に上記半導体素子に接続する配線を形成
する工程、上記半導体素子及び配線を覆う着色、スは不
透明化した感光性ポリイミド系樹脂膜を形成する工程、
この感光性ポリイミド系樹脂膜の一部を露光し現像した
後、熱処理を施すことにより上記−主面上に上記配線の
外端子部を露出する絶縁被膜を形成する工程、然る後に
上記配線端子部表面と着色又は不透明化された絶縁被膜
との反射度の差から上記配線端子位置を光学的に認識し
ながら上記配線端子と外部端子との間のワイヤ接続を行
う工程とを有することを特徴とする半導体装置の製造方
法。[Scope of Claims] 1. A semiconductor substrate, a plurality of semiconductor elements formed on the main surface thereof, wiring connected to the elements on the main surface, and a terminal covering the elements and the wiring, and a terminal outside the wiring. A semiconductor device having a heat-resistant insulating coating formed to expose a portion thereof, the semiconductor device being made of the heat-resistant insulating coated polyimide and colored to such an extent that the position of the external wiring terminal portion can be optically recognized. Or a semiconductor device whose characteristic is that it is made opaque. 2. A step of forming a semiconductor element on the whole surface of a semiconductor substrate,
forming a wiring connected to the semiconductor element on the surface of the substrate; forming a colored, opaque photosensitive polyimide resin film covering the semiconductor element and the wiring;
After exposing and developing a part of this photosensitive polyimide resin film, heat treatment is performed to form an insulating coating on the main surface exposing the outer terminal portion of the wiring, followed by the wiring terminal. The wire connection between the wiring terminal and the external terminal is performed while optically recognizing the position of the wiring terminal based on the difference in reflectivity between the surface of the part and the colored or opaque insulating coating. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59102562A JPS60247954A (en) | 1984-05-23 | 1984-05-23 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59102562A JPS60247954A (en) | 1984-05-23 | 1984-05-23 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60247954A true JPS60247954A (en) | 1985-12-07 |
Family
ID=14330666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59102562A Pending JPS60247954A (en) | 1984-05-23 | 1984-05-23 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60247954A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1850390A2 (en) * | 2006-04-28 | 2007-10-31 | LG Electronics Inc. | Display device module |
-
1984
- 1984-05-23 JP JP59102562A patent/JPS60247954A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1850390A2 (en) * | 2006-04-28 | 2007-10-31 | LG Electronics Inc. | Display device module |
| EP1850390A3 (en) * | 2006-04-28 | 2011-11-30 | LG Display Co., Ltd. | Display device module |
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