JPS6024583B2 - Manufacturing method for semiconductor lead frames - Google Patents
Manufacturing method for semiconductor lead framesInfo
- Publication number
- JPS6024583B2 JPS6024583B2 JP4016679A JP4016679A JPS6024583B2 JP S6024583 B2 JPS6024583 B2 JP S6024583B2 JP 4016679 A JP4016679 A JP 4016679A JP 4016679 A JP4016679 A JP 4016679A JP S6024583 B2 JPS6024583 B2 JP S6024583B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor lead
- plated
- lead frame
- semiconductor
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000007747 plating Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 10
- 238000005406 washing Methods 0.000 claims description 8
- 239000000243 solution Substances 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 238000005238 degreasing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- IZLAVFWQHMDDGK-UHFFFAOYSA-N gold(1+);cyanide Chemical compound [Au+].N#[C-] IZLAVFWQHMDDGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000001509 sodium citrate Substances 0.000 description 1
- NLJMYIDDQXHKNR-UHFFFAOYSA-K sodium citrate Chemical compound O.O.[Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O NLJMYIDDQXHKNR-UHFFFAOYSA-K 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
- 239000001488 sodium phosphate Substances 0.000 description 1
- 229910000162 sodium phosphate Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- RYFMWSXOAZQYPI-UHFFFAOYSA-K trisodium phosphate Chemical compound [Na+].[Na+].[Na+].[O-]P([O-])([O-])=O RYFMWSXOAZQYPI-UHFFFAOYSA-K 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 本発明は半導体用リードフレームの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor lead frame.
従来、半導体パッケージの組立に供される半導体用リー
ドフレームは、一般に銅、ニッケル、クロム、コバルト
、鉄の単体またはこれらの数種からの合金などの半導体
リード用金属板を食刻するか又は打抜いてＩＣチップを
取付けるマゥンテング部とパッケージの外部リード線の
部分とを有するリードフレーム素体を成形したのち、該
成形されたりードフレーム素体のメッキすべき領域以外
の表面を電気絶縁性且つ耐メッキ液性の絶縁被覆用拾具
で保護してから、無電解〆ッキ又は電解メッキを行なっ
て、半導体用リードフレーム秦体のボンディング用金属
をメッキすべき領域に金、銀などのボンディング用金属
をメッキし、その後、前記絶縁被覆用治臭を〆ツキずみ
の製品から除去することにより製造されている。而しな
がら、この方法には【ｉ）メッキ前の脱脂作業を含めた
前処理が必要である、（ｉｉ）メッキ対象物のメッキを
つけない部分を絶縁被覆する治具が必要である、（ｉｉ
ｉ）水洗を含む後処理が必要であるなどの欠点があり、
改善が要望されてきた。Conventionally, semiconductor lead frames used for assembling semiconductor packages are generally made by etching or stamping metal plates for semiconductor leads such as copper, nickel, chromium, cobalt, iron, or alloys of several of these. After molding a lead frame body having a mounting part to which an IC chip is removed and a part for external lead wires of the package, the surface of the molded lead frame body other than the area to be plated is made electrically insulating and plating resistant. After protecting with a liquid-based insulation coating pick-up, perform electroless plating or electrolytic plating to apply bonding metal such as gold or silver to the area to be plated with bonding metal of the semiconductor lead frame body. It is manufactured by plating the insulation coating, and then removing the odor control agent for insulation coating from the plated product. However, this method (i) requires pretreatment including degreasing before plating, (ii) requires a jig to insulate the parts of the object to be plated that are not to be plated. ii
i) There are disadvantages such as the need for post-treatment including washing with water;
Improvements have been requested.
本発明は叙上の欠点を解消した半導体用ＩＪードフレー
ムの製造方法につき研究の結果、半導体リード用金属板
の表面側に半導体用リードフレームからボンディング用
金属をメッキすべき領域を除去したもののポジ画像を有
する第１のレジストを設けると共に半導体リード用金属
板の裏面側に半導体用リードフレームのポジ画像を有す
る第２のレジストを設け、次いで金属露出部をエッチン
グしてボンディング用金属をメッキすべき領域がハーフ
エッチングされた半導体用リードフレーム素体を作製し
、水洗して腐蝕液を充分に除去したのち、前記第１及び
第２のレジストを剥離しない状態でメッキを行なって半
導体リード用金属板のハーフエッチングした部分にボン
ディング用金属をメッキし「しかるのち、前記第１及び
第２のレジストを剣膜する方法により、（ｉ）メッキ対
象物のメッキしない部分はすでにエッチング用レジスト
で絶縁被覆されているので、あらためてメッキ対象物に
絶縁被覆用捨臭をとりつける必要性がなくなる、（ｉｉ
）エッチングされた金属面は清浄化されているので、脱
脂処理が不要である、（ｉｉｉ）水洗を含む後処理はエ
ッチング製品の後処理をかねて行なうことができること
を見し、出し、かかる知見にもとづいて完成したもので
、その要旨は「半導体用リードフレーム素体のボンディ
ング用金属をメッキすべき領域にボンディング用金属を
メッキした半導体用リードフレームの製造方法において
、半導体リード用金属板の表面側に半導体用リードフレ
ームからボンディング用金属をメッキすべき領域を除去
したもののポジ画像を有する第１のレジストを設けると
共に半導体リード用金属板の裏面側に半導体用リードフ
レームのポジ画像を有する第２のレジストを設け、次い
で金属露出部を表裏からエッチングして、ボンディング
用金属をメッキすべき領域がハーフエッチングされた半
導体用リードフレーム素体を作製し、水洗して腐蝕液を
除去したのち、前記第１及び第２のレジストを剥膜しな
い状態で半導体リード用金属板のハーフエッチングした
部分にボンディング用金属をメッキし、しかるのち、前
記第１及び第２のレジストを剥膜することを特徴とする
半導体用リードフレームの製造方法。The present invention has been developed as a result of research into a method for manufacturing an IJ card frame for semiconductors that eliminates the above-mentioned drawbacks, and as a result of research, the positive image of a semiconductor lead frame in which the area to be plated with bonding metal is removed from the front side of the metal plate for semiconductor leads. At the same time, a second resist having a positive image of the semiconductor lead frame is provided on the back side of the semiconductor lead metal plate, and then the exposed metal portion is etched to form an area where bonding metal is to be plated. A semiconductor lead frame body with half-etched is prepared, washed with water to sufficiently remove the corrosive solution, and then plated without removing the first and second resists to form a semiconductor lead metal plate. The half-etched part is plated with a bonding metal, and then the first and second resists are coated, whereby (i) the part of the object to be plated that is not to be plated is already insulated with the etching resist; Therefore, there is no need to add odor for insulation coating to the object to be plated (ii
) The etched metal surface is clean, so no degreasing is necessary; and (iii) post-treatment, including water washing, can also serve as post-treatment of the etched product. It was originally completed, and its gist is ``In a method for manufacturing a semiconductor lead frame in which bonding metal is plated on the area of the semiconductor lead frame body where bonding metal is to be plated, the surface side of the semiconductor lead metal plate is A first resist having a positive image of a region to be plated with bonding metal from a semiconductor lead frame is provided on the semiconductor lead frame, and a second resist having a positive image of the semiconductor lead frame on the back side of the semiconductor lead metal plate. A resist is provided, and then the exposed metal portions are etched from the front and back to produce a semiconductor lead frame body in which the region to be plated with the bonding metal is half-etched. After washing with water to remove the corrosive solution, A bonding metal is plated on the half-etched portion of the semiconductor lead metal plate without removing the first and second resists, and then the first and second resists are removed. A method for manufacturing lead frames for semiconductors.
」である。以下、本発明につき、図面を参照しながら詳
細に説明する。”. Hereinafter, the present invention will be explained in detail with reference to the drawings.
先ず、写真製版法或いは印刷法によって第３図示の如く
、銅、ニッケル、クロム、コバルト、鉄の単体またはそ
れらの数種からの合金などの半導体リード用金属板１の
表面側に半導体用リードフレームからボンディング用金
属をメッキすべき領域を除去したもののポジ画像を有す
る第５図示のような第１のレジスト２を設けると共に半
導体リード用金属板１の裏面側に半導体用リードフレー
ムのポジ画像を有する第６図示のような第２のレジスト
３を設ける。First, as shown in Figure 3, a semiconductor lead frame is formed on the surface side of a semiconductor lead metal plate 1 made of copper, nickel, chromium, cobalt, or iron, or an alloy of several of these, by photolithography or printing. A first resist 2 as shown in FIG. 5 having a positive image after removing the area to be plated with bonding metal is provided, and a positive image of a semiconductor lead frame is provided on the back side of the semiconductor lead metal plate 1. A second resist 3 as shown in FIG. 6 is provided.
次いで金属露出部をエッチングして第２図示の如くボン
ディング用金属をメッキすべき領域がハーフエッチング
された半導体用リードフレーム素体４を作製する。Next, the exposed metal portion is etched to produce a semiconductor lead frame body 4 in which the region to be plated with bonding metal is half-etched, as shown in the second figure.
エッチング終了後水洗して腐蝕液を充分に除去したのち
、第３図示の如く第１及び第２のレジスト２，３を剥膜
しない状態で半導体リード用金属板のハーフエッチング
した部分に金、銀などのボンディング用金属５をメッキ
する。After etching is completed, the corrosive solution is thoroughly removed by washing with water, and then gold and silver are applied to the half-etched portion of the semiconductor lead metal plate without removing the first and second resists 2 and 3, as shown in Figure 3. A bonding metal 5 such as the like is plated.
しかるのち、第４図示の如く第１及び第２のレジスト２
，３を剥膜して、第７図示のような半導体用リードフレ
ーム素体のボンディング用金属をメッキすべき領域にボ
ンディング用金属をメッキした半導体用リードフレーム
６を得る。Thereafter, as shown in the fourth figure, the first and second resists 2 are
.
尚、本発明の方法において、エッチングされた金属面は
清浄化されているので、メッキ前の脱脂処理は行なう必
要はない。In addition, in the method of the present invention, since the etched metal surface is cleaned, there is no need to perform degreasing treatment before plating.
以上のように本発明の方法によれば、半導体用リードフ
レーム素体に部分メッキの際、メッキ対・象物に絶縁被
覆用治具をとりつける必要がなく、又、脱脂処理は不要
であり、且つ水洗を含む後処理はエッチング製品の後処
理をかねるのでその結果として工程を短縮することがで
き、且つ絶縁被覆用捨具取付け時に発生するピン曲り等
の不良事故を減少させることができる。As described above, according to the method of the present invention, when partially plating a semiconductor lead frame element, there is no need to attach an insulating coating jig to the plating target/object, and there is no need for degreasing treatment. In addition, the post-processing including washing with water also serves as the post-processing of the etched product, so that the process can be shortened as a result, and defects such as bent pins that occur when attaching the insulation coating waste tool can be reduced.
又、耐鰍性レジストを絶縁被覆用レジストとかねている
ので半導体用リードフレーム秦体に対する部分メッキエ
リアの整合性を従来より高めることができる。次に本発
明の実施例をあげて本発明につき具体的に説明する。Furthermore, since the scorch-resistant resist is also used as the insulating coating resist, the consistency of the partial plating area with respect to the semiconductor lead frame body can be improved compared to the conventional method. Next, the present invention will be specifically explained with reference to Examples.
実施例 １
０．２５肋の厚さの４２合金（Ｎｉ４２重量％、Ｆｅ５
８重量％）の板の両面に感光液（ＦＲ−１亀富士薬品工
業■製）を均一に８〜１０ミクロンの厚さに塗布し、乾
燥した。Example 1 Alloy 42 (42 wt% Ni, Fe5) with a thickness of 0.25 ribs
A photosensitive solution (FR-1 manufactured by Kamefuji Pharmaceutical Co., Ltd.) was uniformly applied to a thickness of 8 to 10 microns on both sides of a plate (8% by weight) and dried.
次いで片側の鮫光液塗布面に第８図示のような半導体リ
ードフレームからボンディング用金属をメッキすべき領
域を除去したもののネガ画像を有する第１の原版８をあ
てがい、ついで真空焼枠などを用いて両者を密着させて
から蟻付面照度８〜１０万ルクスのキセノンランプを用
いて７頂趣・間紫外線に富んだ光を照射し焼付を行なっ
た。又、もう一方の感光液塗布面には第９図示のような
半導体用リードフレームのネガ画像を有する第２の原版
９をあてがい、同様にして暁付を行なつた。以上のよう
にして焼付を行なったのち、水のシャワーをかけて現像
を行ない、その後、１５０〜１８０℃で５分間加熱乾燥
を行なった。Next, a first master plate 8 having a negative image of a semiconductor lead frame from which the area to be plated with bonding metal has been removed, as shown in Figure 8, is applied to one side of the surface coated with the shark-light liquid, and then a vacuum printing frame or the like is used. After the two were brought into close contact with each other, a xenon lamp with an illuminance of 80,000 to 100,000 lux was used to irradiate the dovetail surface with light rich in ultraviolet rays at 7 peaks to perform baking. Further, a second original plate 9 having a negative image of a semiconductor lead frame as shown in FIG. 9 was applied to the other surface coated with the photosensitive liquid, and gradation was carried out in the same manner. After baking as described above, the film was developed by showering with water, and then dried by heating at 150 to 180°C for 5 minutes.
以上のようにして半導体リード用金属板の両側にレジス
トを設けてから塩化第２鉄溶液（４５〜４７℃、３８〜
４０ｏ茂′）を半導体リード用金属板の両側からふきつ
けて金属露出部をエッチングしてボンディング用金属を
メッキすべき領域がハーフエッチングされた半導体用リ
ードフレーム素体を作製した。After providing a resist on both sides of the metal plate for semiconductor leads as described above, a ferric chloride solution (45-47°C, 38-40°C) was applied.
A semiconductor lead frame body in which a region to be plated with a bonding metal was half-etched was prepared by spraying a 40 mm thick film from both sides of a metal plate for semiconductor leads and etching the exposed metal parts.
次いで水洗して腐蝕液を除去したのち、レジストを剥膜
しない状態で半導体リード用金属板のハーフエッチング
した部分にテンベレックス７０２（日本ェレクトロプレ
イテイングエンジニアーズ欄製）を用い、液温７０〜７
５ｑｏ、電流密度６〜８Ａ／ｄ〆、時間５分のメッキ条
件のもとで金メッキを行なった。その後、９０〜９５ｏ
Ｃ、１０％苛性ソーダ水溶液中にメッキ後のレジスト付
半導体リード用金属板を浸潰してレジストを溶解剥離し
、次いで水洗及び乾燥を行なうことにより金が部分メッ
キされた半導体用リードフレームを得ることができた。After washing with water to remove the corrosive solution, Tenberex 702 (manufactured by Japan Electroplating Engineers Co., Ltd.) was used on the half-etched portion of the metal plate for semiconductor leads without removing the resist, and the solution temperature was 70-7.
Gold plating was performed under plating conditions of 5 qo, current density of 6 to 8 A/d, and time of 5 minutes. After that, 90-95o
C. A semiconductor lead frame partially plated with gold can be obtained by immersing the plated resist-attached metal plate for semiconductor leads in a 10% caustic soda aqueous solution, dissolving and peeling off the resist, and then washing with water and drying. did it.
実施例 ２
実施例１と同様にして但し、メッキを無電解〆ッキ法に
よって行ない、半導体用リードフレームの製造を行なっ
た。Example 2 A semiconductor lead frame was manufactured in the same manner as in Example 1, except that plating was performed by an electroless plating method.
金メッキ液としては、シアン化金力リウム２夕／そ、塩
化アンモニウム７５夕／夕、クエン酸ナトリウム５０多
／そ、及び次歴リン酸ナトリウム１０夕／夕からなり、
ｐＨをＮＨ４０日（アンモニア水）で調節して７〜７．
５にしたものを用いた。The gold plating solution consists of 2 days/day of gold cyanide, 75 days/day of ammonium chloride, 50 days/day of sodium citrate, and 10 days/day of sodium phosphate,
Adjust the pH with NH40 (ammonia water) to 7-7.
5 was used.
液温は９２〜９５ｏ０に保った。この無電解〆ッキによ
り、感光膜上に若干金属が折出するが、次工程のアルカ
リ浸簿にて感光膜が溶解剥離するときに一諸に脱落した
。The liquid temperature was maintained at 92-95o0. Due to this electroless plating, some metal was precipitated on the photoresist film, but it fell off all at once when the photoresist film was dissolved and peeled off in the next step of alkaline immersion.
第１図ないし第４図は本発明の製造方法の途中過程を示
す断面図、第５図は第１のレジストの平面図、第６図は
第２のレジストの平面図、第７図は半導体用リードフレ
ームの平面図、第８図は第１のレジスト製版用原版の平
面図、第９図は第２のレジスト製版用原版の平面図であ
る。
１・・・・・・半導体リード用金属板、２・・・・・・
第１のレジスト、３・・・・・・第２のレジスト、４・
・・・・・半導体用リードフレーム秦体、５…・・・ボ
ンディング用金属、６．・・・・・半導体用リードフレ
ーム。
第１図第２図
第３図
第４図
第５図
第６図
第７図
第８図
第９図1 to 4 are cross-sectional views showing intermediate steps in the manufacturing method of the present invention, FIG. 5 is a plan view of the first resist, FIG. 6 is a plan view of the second resist, and FIG. 7 is a semiconductor FIG. 8 is a plan view of the first resist plate-making original plate, and FIG. 9 is a plan view of the second resist plate-making original plate. 1...Metal plate for semiconductor leads, 2...
First resist, 3...Second resist, 4.
... Lead frame for semiconductor, 5... Metal for bonding, 6. ...Lead frame for semiconductors. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9
Claims (1)
をメツキすべき領域にボンデイング用金属をメツキした
半導体用リードフレームの製造方法において、半導体リ
ード用金属板の表面側に半導体用リードフレームからボ
ンデイング用金属をメツキすべき領域を除去したものの
ポジ画像を有する第１のレジストを設けると共に半導体
リード用金属板の裏面側に半導体用リードフレームのポ
ジ画像を有する第２のレジストを設け、次いで金属露出
部をエツチングして、ボンデイング用金属をメツキすべ
き領域がハーフエツチングされた半導体用リードフレー
ム素体を作製し、水洗して腐蝕液を除去したのち、前記
第１及び第２のレジストを剥膜しない状態で半導体リー
ド用金属板のハーフエツチングした部分にボンデイング
用金属をメツキし、しかるのち、前記第１及び第２のレ
ジストを剥膜することを特徴とする半導体用リードフレ
ームの製造方法。1. In a method for manufacturing a semiconductor lead frame in which bonding metal is plated in the region of a semiconductor lead frame body where bonding metal is to be plated, the bonding metal is plated from the semiconductor lead frame on the front side of the semiconductor lead metal plate. A first resist having a positive image after removing the area to be plated is provided, and a second resist having a positive image of the semiconductor lead frame is provided on the back side of the semiconductor lead metal plate, and then the exposed metal portion is etched. A semiconductor lead frame body in which the region to be plated with bonding metal is half-etched is prepared, and after washing with water to remove the corrosive solution, the first and second resists are removed without being removed. A method for manufacturing a lead frame for a semiconductor, comprising plating a bonding metal on a half-etched portion of a metal plate for a semiconductor lead, and then peeling off the first and second resists.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016679A JPS6024583B2 (en) | 1979-04-03 | 1979-04-03 | Manufacturing method for semiconductor lead frames |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016679A JPS6024583B2 (en) | 1979-04-03 | 1979-04-03 | Manufacturing method for semiconductor lead frames |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55133561A JPS55133561A (en) | 1980-10-17 |
| JPS6024583B2 true JPS6024583B2 (en) | 1985-06-13 |
Family
ID=12573171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4016679A Expired JPS6024583B2 (en) | 1979-04-03 | 1979-04-03 | Manufacturing method for semiconductor lead frames |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024583B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0671058B2 (en) * | 1985-06-05 | 1994-09-07 | 日立電線株式会社 | Manufacturing method of lead frame having minute spot-like plated portion |
| JPH0795577B2 (en) * | 1988-04-12 | 1995-10-11 | 富士プラント工業株式会社 | Partial plating method on lead frame |
| KR100530754B1 (en) * | 1998-09-09 | 2006-02-28 | 삼성테크윈 주식회사 | Method of continuously manufacturing a lead frame |
| JP2010010634A (en) * | 2008-06-30 | 2010-01-14 | Shinko Electric Ind Co Ltd | Lead frame, and method of manufacturing semiconductor device |
-
1979
- 1979-04-03 JP JP4016679A patent/JPS6024583B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55133561A (en) | 1980-10-17 |
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