JPS6024058A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6024058A JPS6024058A JP58132302A JP13230283A JPS6024058A JP S6024058 A JPS6024058 A JP S6024058A JP 58132302 A JP58132302 A JP 58132302A JP 13230283 A JP13230283 A JP 13230283A JP S6024058 A JPS6024058 A JP S6024058A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- wiring
- output
- output wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000005669 field effect Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 24
- 229910052751 metal Inorganic materials 0.000 abstract description 24
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 240000000220 Panda oleosa Species 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
- H10B99/10—Memory cells having a cross-point geometry
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、半導体集積回路装置に関し、特にデコーダ回
路を有する半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a decoder circuit.
絶縁ゲート型電界効果トランジスタを構成素子とｆるＲ
、ＯＭ、ＲＡＭ、ＦＲＯＭ 等（７）半導体記憶ｉ置で
のアドレス信号によってメモリセルを選択するためのア
ドレス信号の入るｎ人力（ｎは２以上の整数）のＮＯＲ
回路と、前記ＮＯＲ回路の出力に接続されたバッファ回
路からなるデコーダ回路は、大容量の半導体記憶装置で
は第１図のごと〈メモリセル領域ｌの間にデコーダ回路
領域２がおるという構成のものが多い。R with an insulated gate field effect transistor as a constituent element
, OM, RAM, FROM, etc. (7) NOR of n manual input (n is an integer of 2 or more) into which an address signal is input to select a memory cell by an address signal in a semiconductor memory location.
In a large-capacity semiconductor memory device, a decoder circuit consisting of a circuit and a buffer circuit connected to the output of the NOR circuit is configured as shown in FIG. There are many.
この時のデコーダ回路の構成は第２図に示す第１の従来
例のようにＮＯＲ回路３の両側に／くラフア回路４を接
続し、そこから、メモリセルのゲート入力とする為にト
ランジスタのゲート電極と同じ第１の金属層で形成され
た出力配線５を引き出した構成となっている。The configuration of the decoder circuit at this time is as in the first conventional example shown in FIG. The output wiring 5 formed of the same first metal layer as the gate electrode is drawn out.
また、図示していないが、第２の金属層で形成された信
号及び電源配線が縦方向に走っている。Further, although not shown, signal and power supply wiring formed of the second metal layer runs in the vertical direction.
第１の従来例ではバッファ回路を２個用いる為、消費電
力が大きくなるという欠点があシ、また、ＲＯＭ、ＦＲ
ＯＭ等ではトランジスタの狭チャンネル効果、短チャン
ネル効果等によってデコーダ回路中の素子寸法の縮小化
が回路に要求される能力によって制限される為、プロセ
スで決定されるメモリセルの素子寸法の縮小化に比べ七
の速度が遅いのでデコーダ回路の出力配線の向きを横方
向とすると、デコーダの縦方向の寸法がメモリセルの縦
方向の寸法よシ大きくなる。この為デコーダ回路及びそ
の領域によってチップサイズが決定されるようになシ、
チップサイズの縮小を計ることが難かしくなる。第１の
従来例の場合３．５μ程度の設計ルールが限界となる。The first conventional example uses two buffer circuits, which has the disadvantage of increasing power consumption.
In OM etc., the reduction of the element size in the decoder circuit is limited by the capability required of the circuit due to the narrow channel effect, short channel effect, etc. of transistors, so it is difficult to reduce the element size of the memory cell determined by the process. In comparison, the speed of the 7th circuit is slower, so if the output wiring of the decoder circuit is oriented horizontally, the vertical dimension of the decoder will be larger than the vertical dimension of the memory cell. For this reason, the chip size is determined by the decoder circuit and its area.
It becomes difficult to measure the reduction in chip size. In the case of the first conventional example, the design rule of about 3.5μ is the limit.
そこで最近では第３図に示す第２の従来例のような構成
のデコーダ回路が使われつつある。Therefore, recently, a decoder circuit having a configuration like the second conventional example shown in FIG. 3 is being used.
第２の従来例では１段のＮＯＲ回路３′で第１の従来例
のＮＯＲ回路２段の代わりとし、第２の金属層で形成さ
れたアドレス入力信号線６によって制御されるバッファ
回路４′によシ２段分の出力を取シ出している。これに
よってメモリセル１段分に用いるバッファ回路は１個と
なシ第１の従来例より消費電力が少なくなシ、またＮＯ
Ｒ回路を共用する分デコーダ回路の寸法が小さくできる
。In the second conventional example, a single stage NOR circuit 3' is used instead of the two stages of NOR circuits in the first conventional example, and a buffer circuit 4' is controlled by an address input signal line 6 formed of a second metal layer. The output is equivalent to two stages. As a result, the number of buffer circuits used for one stage of memory cells is one, and power consumption is lower than that of the first conventional example.
Since the R circuit is shared, the size of the decoder circuit can be reduced.
しかしながら、以前に述べたように出力配線５はゲート
電極と同じ第１の金属層で形成されている・ 為、デコ
ーダ回路中を通ることができない。However, as mentioned previously, the output wiring 5 is formed of the same first metal layer as the gate electrode, and therefore cannot pass through the decoder circuit.
従って、デコーダ回路のない領域を通って配線する必要
が生じ、この為、メモリセルの高さで制限をうけている
デコーダ回路にさらに寸法的な制限が加えられるのでデ
コーダ回路は横方向にのびることになシ、設置十ルール
が小さくなってもかなシチッグサイズに影響がでてくる
。実際に第２の従来例のデコーダ回路を２５６−？ロビ
４）のＦＲＯＭをレイアウトするとして２．５μｍの設
計ルールを用いて設計した場合、横方向の長さは９５０
μｍ にもなる。また、この時デコーダ回路部分を通る
出力配線５の長さも同じ長さかそれ以上にもなる。Therefore, it becomes necessary to route the wiring through an area where there is no decoder circuit, and this imposes further dimensional restrictions on the decoder circuit, which is limited by the height of the memory cell, so that the decoder circuit cannot extend horizontally. Even if the installation ten rules become smaller, it will affect the size of the Kana Shichig. Actually, the second conventional decoder circuit is 256-? When designing the FROM of Robi 4) using the 2.5 μm design rule, the horizontal length is 950 μm.
It can be as large as μm. Further, at this time, the length of the output wiring 5 passing through the decoder circuit portion becomes the same length or longer.
出力配線層５を形成する第１の金属層は通常、多結晶シ
リコンが用いられる。多結晶シリコンの比抵抗はかなり
大きく、第２の従来例でのデコーダ回路を通る部分の出
力配線５の抵抗は先の２５６ＮＯビートのＦＲＯＭの例
では７．６にΩにもなる。この抵抗と第１の金属層と半
導体基板との間の容量によって、この部分で出力信号に
遅れが生じ、デコーダ回路の両側のメモリセル領域での
スイッチング・スピードがアンバランスになるという欠
点もある。The first metal layer forming the output wiring layer 5 is usually made of polycrystalline silicon. The specific resistance of polycrystalline silicon is quite large, and the resistance of the output wiring 5 passing through the decoder circuit in the second conventional example is as high as 7.6 Ω in the 256 NO beat FROM example. This resistance and the capacitance between the first metal layer and the semiconductor substrate cause a delay in the output signal in this part, which also has the disadvantage of unbalanced switching speeds in the memory cell areas on both sides of the decoder circuit. .
本発明の目的はバッファ回路を１個だけ用い、スイッチ
ング・スピードのアンバランスをなくし、さらに寸法を
縮小したデコーダ回路を有する半導体集積回路装置を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that uses only one buffer circuit, eliminates imbalance in switching speed, and has a decoder circuit whose size is reduced.
本発明の半導体集積回路装置は、半導体基板上に絶縁ゲ
ート型電界効果トランジスタを主構成素子とするｎ入力
（ｎは２以上の整数）のＮＯＲ回路と前記ＮＯＲ回路の
出力に接続されるバッファ回路よシなるデコーダ回路を
形成した領域と、該領域の両側に前記デコーダ回路の出
力配線と接続されるメモリ形成領域が構成され、絶縁ゲ
ート型電界効果トランジスタのゲート電極及び相互配線
釜に出力配線よりなる第１の配線層と電源電位。The semiconductor integrated circuit device of the present invention includes a NOR circuit with n inputs (n is an integer of 2 or more) having an insulated gate field effect transistor as a main component on a semiconductor substrate, and a buffer circuit connected to the output of the NOR circuit. A region where a different decoder circuit is formed, and a memory formation region connected to the output wiring of the decoder circuit are formed on both sides of the region, and the output wiring is connected to the gate electrode of the insulated gate field effect transistor and the interconnection pot. the first wiring layer and power supply potential.
接地電位等の供給配線及び相互配線よシなる第２の配線
層よシなる多層配線構造を有する半導体集積回路装置に
おいて、前記第１層に形成されたメモリ領域への出力配
線はバッファ回路からの第１の出力配線と該出力配線の
デコーダ回路領域の反対側に設けられた第２の出力配線
よりなル、更に第３層に前記第１及び第２の出力配線の
対応する位置にデコーダ回路形成領域上を横切シ、両側
のメモリセル領域上にのびる第３の出力配線を有し、前
記第１．第２の出力配線と第３の出力配線はデコーダ回
路の外側の部分に設けられたコンタクトによシそれぞれ
接続されることにより構成される。In a semiconductor integrated circuit device having a multilayer wiring structure consisting of a second wiring layer consisting of supply wiring for ground potential, etc. and mutual wiring, the output wiring to the memory area formed in the first layer is connected to the buffer circuit. A first output wiring and a second output wiring provided on the opposite side of the decoder circuit area of the output wiring, and further a decoder circuit provided in a third layer at a position corresponding to the first and second output wiring. A third output wiring extends across the formation region and over the memory cell regions on both sides, and the first. The second output wiring and the third output wiring are configured by being connected to contacts provided on the outside of the decoder circuit, respectively.
次に、本発明の実施例について、図面を８照して詳細に
説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第４図は本発明の一実施例の構成を示す平面図でおる。FIG. 4 is a plan view showing the configuration of an embodiment of the present invention.
図において３”はＮＯＲ回路、４“はバッファ回路、５
は第１層目に形成された第１の金属層による出力配線で
ある。７は本発明による第３の金属層を用いた配線、８
及び８′は第１の金属層と第３の金属層を接続するコン
タクトである。In the figure, 3" is a NOR circuit, 4" is a buffer circuit, and 5 is a buffer circuit.
is an output wiring formed by the first metal layer formed in the first layer. 7 is a wiring using the third metal layer according to the present invention; 8
and 8' are contacts connecting the first metal layer and the third metal layer.
本実施例ではＮＯＲ回路３′はバッファ回路４″に接続
され、このデコーダ回路の出力配線５は第１層に第１の
金属層として取シ出されている。また７は第３層に形成
された出力配線であるが８及び８′のコンタクトによシ
両者は接続される。又一方布側にある８′によシ第１層
と接続された出力配線７はバッファ回路４″及びＮＯＲ
回路３′を横切り反対側に至り左側の出力配線５より立
上ったコンタクト８′と接し更にのびて同様に他のコン
タクト８と接続される。In this embodiment, the NOR circuit 3' is connected to a buffer circuit 4'', and the output wiring 5 of this decoder circuit is taken out as a first metal layer on the first layer. The output wiring 7 connected to the first layer through 8' on the fabric side is connected to the buffer circuit 4'' and NOR by the contacts 8 and 8'.
It crosses the circuit 3' to reach the opposite side, contacts the contact 8' rising from the output wiring 5 on the left side, extends further, and is similarly connected to other contacts 8.
本実施例では右側の第１の層に形成された出力配線５は
コンタクト８′により立上シ第３層の右側の出力配線７
に接続し更にデコーダ回路部分を横切っているが、各層
の間には十分な厚さの絶縁膜が被着されているので下部
に形成されているトランジスタ部分に影響を与えること
はない。従って、第２図の従来例で問題となった配線を
反対側に引き出すために要した部分は不要となシデコー
ダ回路の高さ方向の寸法を大きくするという問題はなく
なった。そして第３層の出力配線は左側のコンタクト８
′で第１層の出力配線と接続されると共に第３層の金属
配線として延長し、次のコンタクト８に接している。In this embodiment, the output wiring 5 formed on the first layer on the right side is raised by the contact 8', and the output wiring 7 on the right side of the third layer is raised up by the contact 8'.
, and further crosses the decoder circuit section, but since a sufficiently thick insulating film is deposited between each layer, it does not affect the transistor section formed below. Therefore, the problem of increasing the height dimension of the side decoder circuit because the portion required for drawing out the wiring to the opposite side is unnecessary, which was a problem in the conventional example shown in FIG. 2, is eliminated. And the output wiring of the third layer is the contact 8 on the left side.
It is connected to the output wiring of the first layer at ', and is extended as a metal wiring of the third layer, and is in contact with the next contact 8.
以上説明した構成によるためデコーダ回路の大きさは、
素子寸法、入力信号及び電源配線の数、回路内部の配線
によ）決定され、第１．第シ゛の従来例のごとく出力配
線による制限がないので可能なかぎシ小さくできる。Due to the configuration explained above, the size of the decoder circuit is
(Determined by element dimensions, number of input signal and power supply wiring, wiring inside the circuit), and the first. Since there is no restriction due to the output wiring as in the prior art example shown in FIG.
なお、前記したように第２の従来例のデコーダ回路を２
５６キロビツトのＰＲＯＭを２．５μｍの設計ルールで
設計したとき横方向の長さが９５０μｍであったが、本
発明の実施例に従い設計すると上記長さは６３５μｍ
となシ第２の従来例の６７チの大きさになった。Note that, as mentioned above, the decoder circuit of the second conventional example is
When a 56 kilobit PROM was designed using the 2.5 μm design rule, the lateral length was 950 μm, but when designed according to the embodiment of the present invention, the length was 635 μm.
The size is now 67 inches compared to the second conventional example.
このように本発明によればデコーダ回路形成領域を小さ
くすることができ、すなわちチップサイズの縮小をはか
ることができる。As described above, according to the present invention, the area for forming the decoder circuit can be reduced, that is, the chip size can be reduced.
また、第３の金属配線層には比抵抗の小さい材料を用い
ることができるので、デコーダ回路上を通る出力配線で
信号を不必要に遅らせることにならず、デコーダの両側
でのスイッチングスピードがアンバランスになることは
ない。In addition, since a material with low resistivity can be used for the third metal wiring layer, the output wiring passing over the decoder circuit does not unnecessarily delay the signal, and the switching speed on both sides of the decoder is reduced. There will never be a balance.
更に詳細に説明すると、第４図に示すように、デコーダ
回路の出力でメモリ領域内のゲート配線となる部分５の
直上に抵抗の小さい第３の金属層による配線７を設け、
一定間隔をおいてゲート配線である第１の金属層と８．
８′でコンタクトを取るようにすればメモリ領域でデコ
ーダ回路から最も遠い部分のメモリ素子に信号を送る場
合、信号はメモリ素子に最も近いコンタクトまでは低抵
抗の第３の金属層を通るので抵抗は大きくならず、信号
を遅延なしに送ることができることになる。More specifically, as shown in FIG. 4, a wiring 7 made of a third metal layer with low resistance is provided directly above the portion 5 which is the output of the decoder circuit and becomes the gate wiring in the memory area.
8. a first metal layer serving as a gate wiring at regular intervals;
By making contact at 8', when sending a signal to the memory element farthest from the decoder circuit in the memory area, the signal passes through the third metal layer with low resistance to the contact closest to the memory element, so there is no resistance. does not become large, and signals can be sent without delay.
なお第１層の金属層には多結晶シリコンが多く用いられ
るが第３層の金属層はなるべく低抵抗の金属層が望まし
く、また第２層、第３層の金属は同一でも違ったもので
も差支えない。Note that polycrystalline silicon is often used for the first metal layer, but it is desirable that the third metal layer be a metal layer with as low resistance as possible, and the metals for the second and third layers may be the same or different. No problem.
以上説明したように、本発明によれば回路を簡略化でき
ると共にスイッチングスピードのアンバランスをなくシ
、かつ寸法を縮小したデコーダ回路を有する半導体集積
回路装置を得ることができる。As described above, according to the present invention, it is possible to obtain a semiconductor integrated circuit device having a decoder circuit that can simplify the circuit, eliminate imbalance in switching speed, and have a reduced size.
第１図は従来の半導体記憶装置中のデコーダ回路の領域
を示す図、第２図、第３図はそれぞれ従来のデコーダ回
路の構成図、第４図は本発明の一実施例の構成図である
。
ｌ・・・・・・メモリセル領域、２・・・・・・デコー
ダ回路領域、３．３’、３′′・・・・・・ＮＯＲ回路
、４．４’。
４″・・・・・・バッファ回路、５・・・・・・第１の
金属層による出力配線、６・−・・・・第２の金属層に
よる入力配線、７・・・・・・第３の金属層による配線
、８．８’・・・・・・出力配線５と７を接続するコン
タクト。FIG. 1 is a diagram showing the area of a decoder circuit in a conventional semiconductor memory device, FIGS. 2 and 3 are configuration diagrams of conventional decoder circuits, and FIG. 4 is a configuration diagram of an embodiment of the present invention. be. 1...Memory cell area, 2...Decoder circuit area, 3.3', 3''...NOR circuit, 4.4'. 4''... Buffer circuit, 5... Output wiring by first metal layer, 6... Input wiring by second metal layer, 7... Wiring by third metal layer, 8.8'...Contact connecting output wirings 5 and 7.
Claims (1)
構成素子とするｎ入力（ｎは２以上の整数）のＮＯＲ回
路と前記ＮＯＲ回路の出力に接続されるバッファ回路よ
シなるデコーダ回路を形成した領域と、該領域の両側に
前記デコーダ回路の出力配線と接続されるメモリ形成領
域が構成され、絶縁ゲート型電界効果トランジスタのゲ
ート電極及び相互配線釜に出力配線よシなる第１の配線
層と、電源電位、接地電位等の供給配線及び相互配線よ
シなる第２の配線層よりなる多層配線構造を有する半導
体集積回路装置において、前記第１層に形成されたメモ
リ領域への出力配線はバッファ回路からの第１の出力配
線と該出力配線のデコーダ回路領域の反対側に設けられ
た第２の出力配線よシなシ、更に第３層に前記第１及び
第２の出力配線の対応する位置にデコーダ回路形成領域
上を横切シ、両側のメモリセル領域上にのびる第３の出
力配線を有し、前記第１．第２の出方配線と第３の出力
配線はデコーダ回路の外側の部分に設けられたコンタク
トにょシそれぞれ接続されていることを特徴とする半導
体集積回路装置。A region in which a decoder circuit such as an n-input (n is an integer of 2 or more) NOR circuit whose main constituent elements are insulated gate field effect transistors and a buffer circuit connected to the output of the NOR circuit is formed on a semiconductor substrate. and a first wiring layer in which a memory formation region connected to the output wiring of the decoder circuit is formed on both sides of the region, and the gate electrode of the insulated gate field effect transistor and the output wiring are connected to the interconnection pot. In a semiconductor integrated circuit device having a multilayer wiring structure consisting of a second wiring layer consisting of supply wiring for power supply potential, ground potential, etc. and mutual wiring, the output wiring to the memory area formed in the first layer is connected to a buffer circuit. and a second output wiring provided on the opposite side of the decoder circuit area of the output wiring, and further a third layer at corresponding positions of the first and second output wiring. A third output wiring crosses over the decoder circuit formation area and extends over the memory cell area on both sides, and the first. A semiconductor integrated circuit device characterized in that the second output wiring and the third output wiring are respectively connected to contacts provided on an outer portion of the decoder circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58132302A JPS6024058A (en) | 1983-07-20 | 1983-07-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58132302A JPS6024058A (en) | 1983-07-20 | 1983-07-20 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6024058A true JPS6024058A (en) | 1985-02-06 |
Family
ID=15078117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58132302A Pending JPS6024058A (en) | 1983-07-20 | 1983-07-20 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024058A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61267994A (en) * | 1984-11-15 | 1986-11-27 | Fujitsu Ltd | Semiconductor memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5334927B2 (en) * | 1973-01-31 | 1978-09-25 |
-
1983
- 1983-07-20 JP JP58132302A patent/JPS6024058A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5334927B2 (en) * | 1973-01-31 | 1978-09-25 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61267994A (en) * | 1984-11-15 | 1986-11-27 | Fujitsu Ltd | Semiconductor memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5994849A (en) | Semiconductor integrated circuit device | |
| US6651236B2 (en) | Semiconductor integrated circuit device, and method of placement and routing for such device | |
| US4750026A (en) | C MOS IC and method of making the same | |
| JPS61180466A (en) | Laminated type semiconductor device | |
| JPS6024058A (en) | Semiconductor integrated circuit device | |
| JPS583379B2 (en) | semiconductor equipment | |
| JPH03120743A (en) | Semiconductor device | |
| US4716450A (en) | Semiconductor integrated circuit having complementary field effect transistors | |
| JP2997479B2 (en) | Gate array | |
| JPS59121853A (en) | Semiconductor device | |
| JPH0590427A (en) | Semiconductor ic device | |
| JPH033951B2 (en) | ||
| JP2575760B2 (en) | Integrated circuit wiring structure | |
| JPS6364337A (en) | Semiconductor integrated circuit device | |
| JPS60128655A (en) | Semiconductor device | |
| JPS644667B2 (en) | ||
| EP0278065A2 (en) | Semiconductor integrated circuit latch-up preventing apparatus | |
| JPH0541452A (en) | Standard cell system integrated circuit | |
| JPS59135744A (en) | Semiconductor integrated circuit device | |
| JPH02148845A (en) | Semiconductor device | |
| JPH09148442A (en) | Method for designing integrated circuit | |
| JPH05109891A (en) | Delay method of signal in semiconductor integrated circuit and its semiconductor integrated circuit | |
| JPS62115842A (en) | Gate array having delay cell | |
| JPH0330464A (en) | Semiconductor integrated circuit device | |
| JPH021952A (en) | Semiconductor integrated circuit in standard cell system |