JPS60235443A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60235443A
JPS60235443A JP59093477A JP9347784A JPS60235443A JP S60235443 A JPS60235443 A JP S60235443A JP 59093477 A JP59093477 A JP 59093477A JP 9347784 A JP9347784 A JP 9347784A JP S60235443 A JPS60235443 A JP S60235443A
Authority
JP
Japan
Prior art keywords
capacitor
semiconductor device
resin
power supply
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59093477A
Other languages
Japanese (ja)
Inventor
Tadayuki Akatsuki
赤月　忠之
Toshio Ichiyama
市山　寿雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59093477A priority Critical patent/JPS60235443A/en
Publication of JPS60235443A publication Critical patent/JPS60235443A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To improve the packaging density of a semiconductor device while preventing noises, by providing a capacitor having external electrodes within the sealing resin located over the semiconductor element sealed with resin. CONSTITUTION:Flat-plate conductors 6a and 6b are electrically connected to a power supply or the ground, and sealed with sealing resin 5 such that they are projected from the resin and extended outward to be connected to the power supply or the grounding line. A capacitor is composed of external electrodes 7a and 7b, a dielectric 8 held between the flat-plate conductors 6a and 6b and the like. This capacitor serves as a by-pass capacitor between the power supply and the ground. Since the by-pass capacitor is thus formed integrally with a semiconductor device, no space is required over the packaged substrate. Further, since a minimum length of conductive material is required for connecting the by-pass capacitor, undesirable inductance can be reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体装置、特に樹脂封止型の半導体装置
の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor devices, particularly resin-sealed semiconductor devices.

〔従来技術〕[Prior art]

従来のこの楯の半導体装置を第１図、第２図によって説
明する。第１図はプラスチックモールドタイプの半導体
装置の内部を含めて一部省略して示した平面図であり、
第２図は第１図の■−■線による断面図である。これら
の図で、１は集積回路などの半導体素子、２は前記半導
体素子１と内部リード線３により電気的に接続された外
部導電材で、半導体素子１は放熱機能を有する支持＆４
上に支持されている。なお、外部導電材２は互いに間隔
をおいて多数配置されるが、ここでは一部を示している
。A conventional semiconductor device with this shield will be explained with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a plastic mold type semiconductor device with some parts omitted, including the inside.
FIG. 2 is a sectional view taken along the line ■--■ in FIG. 1. In these figures, 1 is a semiconductor element such as an integrated circuit, 2 is an external conductive material that is electrically connected to the semiconductor element 1 by an internal lead wire 3, and the semiconductor element 1 is a support and 4 that has a heat dissipation function.
supported above. Note that a large number of external conductive materials 2 are arranged at intervals, and only a portion of them are shown here.

５は絶縁性のあるプラスチックモールド材等の封止樹脂
で、各外部導電材２を突出せしめて樹脂封止される。こ
の樹脂封止はあらかじめ半導体素子１、外部導電材２お
よび支持板４を支持した閉空間に押し出し成形により形
成される。Reference numeral 5 is a sealing resin such as an insulating plastic molding material, and each external conductive material 2 is made to protrude and sealed with the resin. This resin sealing is formed in advance by extrusion molding in a closed space that supports the semiconductor element 1, external conductive material 2, and support plate 4.

このような半導体装置を使用する場合、各種半導体素子
を内蔵した各半導体装置相互間の信号線を接続する必要
がある。この段階で一般に多用されている手段として、
プリント基板（図示せず）が使用される。半導体装置、
特に集積回路の信号変化が急峻なとき、集積回路の要求
する電源電流値が急激に変化する。この電源電流値の変
化が原因となって電源供給線上にノイズが発生し、他の
半導体素子の動作を不安定なものにしてしまう。When using such semiconductor devices, it is necessary to connect signal lines between the semiconductor devices each containing various semiconductor elements. A commonly used method at this stage is
A printed circuit board (not shown) is used. semiconductor equipment,
In particular, when the signal change of an integrated circuit is steep, the power supply current value required by the integrated circuit changes rapidly. This change in the power supply current value causes noise to occur on the power supply line, making the operation of other semiconductor elements unstable.

これを軽減する目的で、半導体素子への電源供給線と接
地線との間にバイパスコンデンサと呼ばれるコンデンサ
が接続され使用されている。In order to alleviate this problem, a capacitor called a bypass capacitor is connected between the power supply line to the semiconductor element and the ground line.

従来の半導体装置は上記のよう圧して使用されるので、
プリント基板上にコンデンサを付加する必要があり、こ
のためコンデンサのリード線の持つインダクタンスのた
めかえってノイズが増大する場合がある。また、プリン
ト基板上の実装密度が低下する等の欠点があった。Since conventional semiconductor devices are used under pressure as described above,
It is necessary to add a capacitor to the printed circuit board, which may actually increase noise due to the inductance of the capacitor lead wire. Further, there were drawbacks such as a reduction in the mounting density on the printed circuit board.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来の欠点を除去するために
なされたもめで、樹脂封止型の半導体装置の封止樹脂中
に外部＊極を備えたコンデンサな形成し、半導体素子に
電源を供給すると同時にバイパスコンデンサを実装密度
を下げることなく付加できる半導体装置を提供するもの
である。以下この発明の一実施例を図面について説明す
る。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and is a method of forming a capacitor with an external pole in the resin of a resin-sealed semiconductor device to supply power to the semiconductor element. The object of the present invention is to provide a semiconductor device in which a bypass capacitor can be added at the same time as the supply without reducing the packaging density. An embodiment of the present invention will be described below with reference to the drawings.

〔発明の実施例〕[Embodiments of the invention]

第３図、第４図はこの発明の一実施例を示す半導体装置
の平面図およびＩＶ−ＩＶ線による断面図である。第３
図、第４図において、第１図、第２図と同一符号は同じ
ものを示し、６ａおよび６ｂは電気的に電源もしくは接
地に接続された平板導体であり、封止樹脂５より突出し
【樹脂封止され、電源もしくは接地線に接続可能なよ５
にその外部へ延びており、外部電極７ａ、７ｂが設けら
れている。また、８は前記平板導体６ａ、６ｂｌＣよっ
て挾持された誘電体であり、これらでこの発明のコンデ
ンサが形成される。3 and 4 are a plan view and a sectional view taken along the line IV--IV of a semiconductor device showing an embodiment of the present invention. Third
4, the same reference numerals as in FIG. 1 and FIG. 5. Sealed and connectable to power or ground wire.
External electrodes 7a and 7b are provided on the external electrodes 7a and 7b. Further, 8 is a dielectric material sandwiched between the flat conductors 6a and 6blC, which form the capacitor of the present invention.

このコンデンサは岨源−接地間のバイパスコンデンサと
して機能する。このようにして形成されたバイパスコン
デンサは、半導体装置と一体化しているため、実装基板
上の空間を必要としない。また、バイパスコンデンサ接
続に必要な導電材が必要最小の長さにすぎないため、有
害なインダクタンス分が少なくできる。This capacitor functions as a bypass capacitor between the source and ground. Since the bypass capacitor formed in this manner is integrated with the semiconductor device, it does not require space on the mounting board. Furthermore, since the length of the conductive material required to connect the bypass capacitor is only the minimum length, harmful inductance can be reduced.

なお、上記実施例ではプラスチックモールド材等の封止
樹脂で樹脂封止して固定したが、第４図に示す■−■面
で着脱自在とし、平板導体６ａ。In the above embodiment, the flat conductor 6a is fixed by being sealed with a sealing resin such as a plastic molding material, but the flat conductor 6a is detachable from the plane 1--2 shown in FIG.

６ｂの形状を変形し、誘電体８０代わりとしてリチウム
電池等の小型電池を装着用能とした場合には、低消費電
力のＣ−ＭＯＳスタティック几ＡＭ等の停電時対策とし
て応用することも可能である。If the shape of 6b is modified and a small battery such as a lithium battery can be installed instead of the dielectric 80, it can also be applied as a countermeasure against power outages such as C-MOS static AM with low power consumption. be.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、樹脂封止された半導
体素子の上方の封止樹脂中に外部磁極を備えたコンデン
サを形成したので、実装密度が向上するとともに、ノイ
ズの少ない半導体装置が得られる効果がある。As explained above, the present invention forms a capacitor with an external magnetic pole in the sealing resin above the resin-sealed semiconductor element, which improves the packaging density and provides a semiconductor device with less noise. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のプラスチックモールドタイプの半導体装
置の構成を示す平面図、第２図は第１図の■−■線によ
る断面図、第３図、第４図はこの発明の一実施例を示す
半導体装置の平面図およびＩＶ−ＰＩ線による断面図で
ある。 図中、１は半導体素子、２は外部導電材、３は内部リー
ド線、４は支持板、５は封止樹脂、＄ａ。 ６ｂは平板導体、７ａ、７ｂは外部電極、８は誘電体で
ある。 なお、図中の同一符号は同一または相当部分を示す。 代理人　大岩増雄　（外２名）FIG. 1 is a plan view showing the configuration of a conventional plastic mold type semiconductor device, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIGS. 3 and 4 show an embodiment of the present invention. FIG. 2 is a plan view and a cross-sectional view taken along the line IV-PI of the semiconductor device shown in FIG. In the figure, 1 is a semiconductor element, 2 is an external conductive material, 3 is an internal lead wire, 4 is a support plate, 5 is a sealing resin, and $a. 6b is a flat conductor, 7a and 7b are external electrodes, and 8 is a dielectric. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others)

Claims (1)

【特許請求の範囲】 （１１支持板上に載置固定された半導体素子と複数の外
部導電材とを内部リード線により接続し、前記各外部導
電材を突出せしめ封止樹脂により樹脂封止した半導体装
置において、前記樹脂封止された半導体素子の上方の前
記封止樹脂中に外部電極を備えたコンデンサを形成した
ことを特徴とする半導体装置。 （２）　コンデンサは、平板導体を対向して形成したも
のである特許請求の範囲第（１１項記載の半導体装置。 （３）　コンデンサは、平板導体を複数枚互いに電気的
に分離された状態で配置して形成したものである特許請
求の範囲第（１）項記載の半導体装置。[Scope of Claims] (11 A semiconductor element mounted and fixed on a support plate and a plurality of external conductive materials are connected by internal lead wires, and each of the external conductive materials is made to protrude and sealed with a sealing resin. A semiconductor device, characterized in that a capacitor having an external electrode is formed in the sealing resin above the resin-sealed semiconductor element. (2) The capacitor has flat conductors facing each other. (3) The capacitor is formed by arranging a plurality of flat conductors electrically separated from each other. The semiconductor device according to item (1).
JP59093477A 1984-05-08 1984-05-08 Semiconductor device Pending JPS60235443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59093477A JPS60235443A (en) 1984-05-08 1984-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59093477A JPS60235443A (en) 1984-05-08 1984-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60235443A true JPS60235443A (en) 1985-11-22

Family

ID=14083417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59093477A Pending JPS60235443A (en) 1984-05-08 1984-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60235443A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390849U (en) * 1986-12-04 1988-06-13
JPH0388349U (en) * 1989-12-27 1991-09-10
EP0978854A2 (en) * 1998-08-04 2000-02-09 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390849U (en) * 1986-12-04 1988-06-13
JPH0388349U (en) * 1989-12-27 1991-09-10
EP0978854A2 (en) * 1998-08-04 2000-02-09 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure
EP0978854A3 (en) * 1998-08-04 2007-08-01 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure

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