JPS60224224A - Mask aligning method - Google Patents
Mask aligning methodInfo
- Publication number
- JPS60224224A JPS60224224A JP59079507A JP7950784A JPS60224224A JP S60224224 A JPS60224224 A JP S60224224A JP 59079507 A JP59079507 A JP 59079507A JP 7950784 A JP7950784 A JP 7950784A JP S60224224 A JPS60224224 A JP S60224224A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- systems
- alignment
- semiconductor substrate
- marks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置の製造工程に於いて使用するマス
クアライメント方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a mask alignment method used in the manufacturing process of semiconductor devices.
（従来技術とその問題点）
従来、縮小投影型光露光法によるパターン形成工程に於
いては、レチクル上に形成したパターンを、半導体基板
上の所定の位置に精度良く転写する為に該半導体基板の
位置を高精度に制御しながら、ステップ・アンド・リピ
ート露光を行なう方法が一般的である。上記の方法で半
導体基板上に所望のマスクパターンをステップ・アンド
・リピート露光する場合、一般に第１図に示すように半
導体基板１１の外周近傍には、パターン１２を形成しな
い空白領域１３が生ずる。これは一般に、半導体基板の
外周近傍は、半導体装置の製造工程に於いて種々の治具
等と接触する為に傷つき易い為であるが、従来の縮小投
影型光露光装置に於いては、一般に１ステツプ当シの露
光領域が、数誠角ないし十露角程度と比較的小さく、半
導体基板の外周近傍に生ずる余白領域を比較的小さく抑
えることが可能である為、従来は余り問題にならなかっ
た。ところが近年縮小投影型光露光の生産性を高める為
に、１ステツプ当シの露光面積を士数篇角ないし２０１
１１角程度まで拡大した露光装置が開発され、一般に使
用されるようＫなった。(Prior art and its problems) Conventionally, in a pattern forming process using a reduction projection light exposure method, in order to accurately transfer a pattern formed on a reticle to a predetermined position on a semiconductor substrate, A common method is to perform step-and-repeat exposure while controlling the position with high precision. When a desired mask pattern is step-and-repeat exposed on a semiconductor substrate by the above method, a blank area 13 where the pattern 12 is not formed generally occurs near the outer periphery of the semiconductor substrate 11, as shown in FIG. This is because the vicinity of the outer periphery of a semiconductor substrate is generally easily damaged due to contact with various jigs, etc. during the manufacturing process of semiconductor devices, but in conventional reduction projection type optical exposure equipment, Conventionally, this did not pose much of a problem because the exposure area per step was relatively small, on the order of a few centigrade angles to ten dew angles, and it was possible to keep the margin area near the outer periphery of the semiconductor substrate relatively small. Ta. However, in recent years, in order to increase the productivity of reduced projection light exposure, the exposure area per step has been increased from
Exposure equipment that enlarged the area to about 11 angles was developed and came into general use.
また超微細パターンの高精度転写技術として注目されて
いるＸ線露光に於いても１ステツプ当シの露光面積を約
ｔＯＷ角ないし３０１１１角としたステップ・アンド・
リピート露光装置が開発されている。上記のごとき露光
装置に於いては、第２図に示すように１ステツプの露光
領域２１の中にチップパターン２２とアライメントマー
ク２３を複数個形成するのが一般的である。この場合第
３図の露光例に示すように、半導体基板３１の周辺部の
余白領域３２に於いては、チップパターン３３を形成す
る余裕が十分布るにもかかわらず露光マスクの外周端近
傍に形成されているアライメントマーク３４が半導体基
板３１の外にはみ出してしまう為にマスクアライメント
が行なえず、多大な余白領域を生じてしまい、半導体基
板の利用効率及び生産性を低下させる一因となっていた
。In addition, in X-ray exposure, which is attracting attention as a high-precision transfer technology for ultra-fine patterns, the step-and-exposure method sets the exposure area per step to about tOW angle or 30111 angle.
A repeat exposure device has been developed. In the above-mentioned exposure apparatus, it is common to form a plurality of chip patterns 22 and alignment marks 23 in the exposure area 21 of one step, as shown in FIG. In this case, as shown in the exposure example in FIG. 3, although there is sufficient margin for forming the chip pattern 33 in the margin area 32 at the periphery of the semiconductor substrate 31, the area near the outer peripheral edge of the exposure mask is Since the formed alignment mark 34 protrudes outside the semiconductor substrate 31, mask alignment cannot be performed, resulting in a large blank area, which is one of the causes of lowering the utilization efficiency and productivity of the semiconductor substrate. Ta.
（発明の目的）
本発明の目的は上記のごとき従来のマスクアライメント
方法の欠点を改良し、半導体基板の１１ ？’ｌ’全域
を有効に利用できるマスクアライメント方法を提供する
ことである。(Objective of the Invention) The object of the present invention is to improve the above-mentioned drawbacks of the conventional mask alignment method, and to improve the 11 ? It is an object of the present invention to provide a mask alignment method that can effectively utilize the entire 'l' area.
（発明の構成）
本発明によれば可視光および光学レンズ系を用いたマス
クアライメント方法に於いて、４系統以上の光学レンズ
系と該レンズ系の各々に対応して設けたアライメントマ
ークを有するマスクを用い、前記光学レンズ系およびア
ライメントマークの中から任意の２系統の組合せを用い
て行なうことを特徴とするマスクアライメント方法が得
られる。(Structure of the Invention) According to the present invention, in a mask alignment method using visible light and an optical lens system, a mask having four or more optical lens systems and an alignment mark provided corresponding to each of the lens systems is provided. A mask alignment method is obtained, which is characterized in that it is carried out using a combination of any two systems from among the optical lens system and alignment mark.
（構成の詳細な説明） 以下、本発明の詳細を図面を用いて説明する。(Detailed explanation of configuration) Hereinafter, details of the present invention will be explained using the drawings.
本発明のマスクアライメント方法に於いては４系統のア
ライメント用光学系と、これに対応して設けた４つのア
ライメントマークを有するマスクを用いる。In the mask alignment method of the present invention, a mask having four alignment optical systems and four alignment marks provided correspondingly thereto is used.
第４図は、本発明のマスクアライメント方法に用いるマ
スクの主要部分を抜き出して模木的に示したもので、４
１はチップパターン、４２はアライメントマークをそれ
ぞれ示す。FIG. 4 is a mock-up of the main parts of the mask used in the mask alignment method of the present invention.
1 represents a chip pattern, and 42 represents an alignment mark.
第５図は、本発明のマスクアライメント方法によるステ
ップ・アンド・リピート露光の一実施例を模式的に示し
たものである。従来、第３図に示した半導体基板の空白
領域３２にはチップパターンの形成が出来なかったが、
本発明のマスクアライメント方法に於いては、パターン
を転写する基板の形状に応じて、第４図に示した４つの
アライメントマーク４２の中、任意の２個のアライメン
トマークを用いてマスクアライメントを行なう為、第５
図に示すように半導体基板５１の全面にむだ無くチップ
５２が形成できる。FIG. 5 schematically shows an example of step-and-repeat exposure using the mask alignment method of the present invention. Conventionally, a chip pattern could not be formed in the blank area 32 of the semiconductor substrate shown in FIG.
In the mask alignment method of the present invention, mask alignment is performed using any two alignment marks among the four alignment marks 42 shown in FIG. 4, depending on the shape of the substrate onto which the pattern is to be transferred. 5th
As shown in the figure, the chip 52 can be formed over the entire surface of the semiconductor substrate 51 without waste.
（発明の効果）
本発明のマスクアライメント方法によれば、同一寸法の
半導体基板上に同一寸法のチップパターンを露光する場
合、従来方法に比べてチップが１０チ以上多く形成でき
、半導体装置の生産性の向上および低価格化をもたらす
ことができる。(Effects of the Invention) According to the mask alignment method of the present invention, when exposing a chip pattern of the same size on a semiconductor substrate of the same size, more than 10 more chips can be formed compared to the conventional method, and the production of semiconductor devices is improved. This can lead to improved performance and lower costs.
第１図は、従来のステップ・アンド・リピート露光によ
る半導体基板上のチップパターン形成領域を示す概略平
面図、第２図は、大口径レチクル又はＸ線露光マスク上
の一般的パターン配列を示す模式的平面図、第３図は大
口径レチクルを用いたステップ・アンド・リピート光露
光又は一般的ステップ・アンド・リピート型Ｘ線露光に
よる半導体基板上のチップ・パターン形成領域を示す模
式的平面図、第４図は本発明のマスクアライメント方法
に於いて用いるマスクの主要部分を抜き出して示した模
式的平面図、第５図は本発明のマスクアライメント方法
を用いたステップ・アンド・リピートＸ線露光による半
導体基板上のチップパターン形成状態を示す模式的平面
図である。
図中各番号はそれぞれ次のものを示す。
１１．３１，５１・・・半導体基板、１２，２２゜３３
．４１，５２・・・チップパターン形成領域、１３．３
２・・・空白領域、２３，３４，４２・・・アライメン
トマーク。
兜１図
第２図
第３図Figure 1 is a schematic plan view showing a chip pattern formation area on a semiconductor substrate by conventional step-and-repeat exposure, and Figure 2 is a schematic diagram showing a general pattern arrangement on a large-diameter reticle or X-ray exposure mask. 3 is a schematic plan view showing a chip pattern forming area on a semiconductor substrate by step-and-repeat light exposure using a large-diameter reticle or general step-and-repeat type X-ray exposure, Figure 4 is a schematic plan view showing the main parts of the mask used in the mask alignment method of the present invention, and Figure 5 is a schematic plan view showing the main parts of the mask used in the mask alignment method of the present invention. FIG. 2 is a schematic plan view showing a state of chip pattern formation on a semiconductor substrate. Each number in the figure indicates the following. 11.31,51...Semiconductor substrate, 12,22°33
．． 41, 52... Chip pattern formation area, 13.3
2... Blank area, 23, 34, 42... Alignment mark. Kabuto Figure 1 Figure 2 Figure 3
Claims (1)
方法に於いて、４系統以上の光学レンズ系と該レンズ系
の各々に対応して設けたアライメントマークを有するマ
スクを用い、前記光学レンズ系およびアライメントマー
クの中から任意の２系統の組合せを用いて行なうことを
特徴とするマスクアライメント方法。In a mask alignment method using visible light and an optical lens system, a mask having four or more optical lens systems and an alignment mark provided corresponding to each of the lens systems is used, and the optical lens system and the alignment mark are aligned. A mask alignment method characterized in that it is carried out using a combination of any two systems from among the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079507A JPS60224224A (en) | 1984-04-20 | 1984-04-20 | Mask aligning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079507A JPS60224224A (en) | 1984-04-20 | 1984-04-20 | Mask aligning method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60224224A true JPS60224224A (en) | 1985-11-08 |
| JPH0556645B2 JPH0556645B2 (en) | 1993-08-20 |
Family
ID=13691855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59079507A Granted JPS60224224A (en) | 1984-04-20 | 1984-04-20 | Mask aligning method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60224224A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166026A (en) * | 1984-12-19 | 1986-07-26 | Fujitsu Ltd | Method of alignment |
| US5939132A (en) * | 1992-09-11 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Alignment chips positioned in the peripheral part of the semiconductor substrate and method of manufacturing thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53132271A (en) * | 1977-04-20 | 1978-11-17 | Thomson Csf | Thin semiconductor plate* method of positioning pattern projected to said plate in projector* and projector |
-
1984
- 1984-04-20 JP JP59079507A patent/JPS60224224A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53132271A (en) * | 1977-04-20 | 1978-11-17 | Thomson Csf | Thin semiconductor plate* method of positioning pattern projected to said plate in projector* and projector |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166026A (en) * | 1984-12-19 | 1986-07-26 | Fujitsu Ltd | Method of alignment |
| US5939132A (en) * | 1992-09-11 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Alignment chips positioned in the peripheral part of the semiconductor substrate and method of manufacturing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0556645B2 (en) | 1993-08-20 |
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