JPS60223348A - Fm multiplex demodulating circuit - Google Patents
Fm multiplex demodulating circuitInfo
- Publication number
- JPS60223348A JPS60223348A JP7856584A JP7856584A JPS60223348A JP S60223348 A JPS60223348 A JP S60223348A JP 7856584 A JP7856584 A JP 7856584A JP 7856584 A JP7856584 A JP 7856584A JP S60223348 A JPS60223348 A JP S60223348A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistors
- power supply
- level
- trs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/44—Arrangements characterised by circuits or components specially adapted for broadcast
- H04H20/46—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95
- H04H20/47—Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups H04H20/53-H04H20/95 specially adapted for stereophonic broadcast systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/22—Homodyne or synchrodyne circuits
- H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
- H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
- H04H40/54—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving generating subcarriers
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
この発明は、ＦＭ受信機に用いて好適なＦＭステレオ復
調回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an FM stereo demodulation circuit suitable for use in an FM receiver.
特開昭５３−１４３１０１号ｒＦＭステレオ復調回路の
異常音防止回路」（出願人、株式会社日立製作所）には
、異常音防止機能を有し１７２分局器としてのフリップ
フロップ回路が開示されている。Japanese Patent Application Laid-Open No. 53-143101 "Abnormal Noise Prevention Circuit for rFM Stereo Demodulation Circuit" (applicant, Hitachi, Ltd.) discloses a flip-flop circuit having an abnormal noise prevention function and serving as a 172 splitter.
本願発明に先立ち、本願発明者等が上記公開された技術
を検討したところ、十■ｃｃ電源が徐々に低下したとき
、第２図に示されたトランジスタＱ。Prior to the present invention, the present inventors studied the above-mentioned disclosed technology and found that when the 10cc power supply gradually decreased, the transistor Q shown in FIG.
とステレオスイッチ回路１２とを制御するが、上記トラ
ンジスタＱ、とステレオスイッチ回路１２とが同一タイ
ミングで制御されるとは限らず、例えばトランジスタＱ
、がオフからオンとなったとき、ステレオスイッチ回路
１２がオンのままであると、デー−ティ比の異った３８
ＫＨｚ副搬送波信号がステレオデコーダに供給されてし
まい、Ｌ信号とＲ信号との分離度が低下する可能性のあ
ることが判明した。However, the transistor Q and the stereo switch circuit 12 are not necessarily controlled at the same timing; for example, the transistor Q
, changes from off to on, if the stereo switch circuit 12 remains on, the 38
It has been found that the KHz subcarrier signal may be fed to the stereo decoder, reducing the degree of separation between the L and R signals.
本発明は上述の如き実状からなされたものであり、その
目的とするところは、電源電圧が低下してもデユーティ
比が変化せず、Ｌ信号及びＲ信号の分離度の低下を防止
することのできるステレオ復調回路を提供することにあ
る。The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent the duty ratio from changing even when the power supply voltage decreases and to prevent the degree of separation between the L signal and the R signal from decreasing. The purpose of the present invention is to provide a stereo demodulation circuit that can perform the following steps.
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明の概要を簡単に説明すれば
、下記のとおりであ、る。A brief summary of the invention disclosed in this application is as follows.
すなわち、ステレオ復調回路を構成する分局器として使
用されるフリツプフロツプ回路の位相反転動作を行う一
対のトランジスタにそれぞれスイッチング手段を設け、
電源電圧低下時にそのレベルを検出して上記スイッチン
グ手段を駆動することにより、上記一対のトランジスタ
を同時にオフ状態になし、Ｑ出力とＱ出力とのデー−テ
ィ比が変動することなく動作停止を行うものである。That is, a pair of transistors that perform a phase inversion operation of a flip-flop circuit used as a divider constituting a stereo demodulation circuit are provided with switching means, respectively.
By detecting the level when the power supply voltage drops and driving the switching means, the pair of transistors are turned off at the same time, and the operation is stopped without changing the duty ratio between the Q output and the Q output. It is something.
次に、本発明を適用したステレオ復調回路の一実施例を
、第１図〜第３図を参照して説明する。Next, an embodiment of a stereo demodulation circuit to which the present invention is applied will be described with reference to FIGS. 1 to 3.
なお、第１図は本発明を利用したフリップフロップ回路
の回路図であり、第２図は回路動作を説明する波形図、
第３図はステレオ復調回路の回路図である。Note that FIG. 1 is a circuit diagram of a flip-flop circuit using the present invention, and FIG. 2 is a waveform diagram explaining the circuit operation.
FIG. 3 is a circuit diagram of a stereo demodulation circuit.
第１図に示すクリップフロップ回路ＦＦ１において、ト
ランジスタＱｌｌ ＃ Ｑｓ を抵抗Ｒ７，Ｒ。In the clip-flop circuit FF1 shown in FIG. 1, the transistor Qll #Qs is connected to the resistors R7 and R.
は強制停止回路として動作し、＋■ｏｃ電源がレベル低
下したときＱ出力、Ｑ出力がデユーティ比５０％を保持
した状態で、上記ＦＦ、を停止し得るようになされてい
る。operates as a forced stop circuit, and is configured to be able to stop the above-mentioned FF while the Q output and the Q output maintain a duty ratio of 50% when the level of the +■oc power supply drops.
いま仮りに、＋ｖｃｃ電源が正常な電圧レベルにあり、
端子Ｔ、にトリガー信号が供給されたとする。この場合
、トランジスタＱ、、、Ｑ、のコレクタ電圧■ｃＱ□は
、第２図囚に示す如（デー−ティ比５０％で変化し、ト
ランジスタＱ＝ −Ｑａのコレクタ電圧■ ■ 言い換
えればＱ出力とＱＣＱ３１ ＣＱ４−
出力とは第２図のバＣ）の如き極性を変化する。この際
、端子Ｔ、から制御信号Ｐ、が供給されない限り、トラ
ンジスタＱ、、Ｑ、はオフ状態を保持し、上記回路動作
に何等の影響も及ぼさない。Now, suppose the +vcc power supply is at a normal voltage level,
Assume that a trigger signal is supplied to terminal T. In this case, the collector voltage ■cQ□ of the transistors Q, , Q, changes at a duty ratio of 50%, as shown in Figure 2, and the collector voltage of the transistor Q= -Qa■ ■ In other words, the Q output and QCQ31 CQ4- outputs change polarity as shown in Fig. 2 (C). At this time, unless the control signal P is supplied from the terminal T, the transistors Q, , Q, maintain an off state and do not have any influence on the circuit operation.
一方、■ｃｃ電源が低下すると、Ｑ出力とＱ出力とがハ
イレベル又はローレベルに変化してもその電圧差が小と
なって、トランジスタＱ、、Ｑ、を充分にオン又はオフ
に切換えためのベース・エミッタ間電圧ＶＢＫを供給す
ることができず、このまま放置すると微小なノイズ成分
によりでもトランジスタＱｓ 、Ｑ４が反転することが
ある。この反転現象は、言わばクリップフロップ回路Ｆ
Ｆが発振状態になることであり、その発振周波数が他の
回路に対し妨害電波となる。On the other hand, when the cc power supply decreases, even if the Q output and the Q output change to high or low levels, the voltage difference between them becomes small and the transistors Q, Q, are turned on or off sufficiently. It is not possible to supply the base-emitter voltage VBK, and if left as is, even a minute noise component may cause the transistors Qs and Q4 to be inverted. This reversal phenomenon is, so to speak, a clip-flop circuit F.
F is in an oscillation state, and its oscillation frequency becomes an interference radio wave to other circuits.
しかる罠１本実施例では＋■ｃｏ電源のレベルが所定レ
ベル以下に低下する１と、後述する電源電圧検出回路か
ら制御信号Ｐ。が供給され、トランジスタＱ、、Ｑ、を
オン状態に駆動する。In this embodiment, when the level of the +■co power supply falls below a predetermined level, a control signal P is generated from a power supply voltage detection circuit, which will be described later. is supplied, driving transistors Q, , Q, to the on state.
この結果、トランジスタＱ、、Ｑ、のベースが強制的に
ＧＮＤに接続されたようになり、上記異常発振現象の発
生が未然に防止される。ここで注目目すべきは、トラン
ジスタＱｓ 、Ｑ４が同時にオフ状態になされる点であ
る。すなわち、トランジスタＱｓ ＝ Ｑ４の何れか一
方がオフにされても、他方のトランジスタが動作し、Ｑ
出力及びＱ出力のデユーティ比が異るという不都合がな
い。As a result, the bases of the transistors Q, , Q are forcibly connected to GND, and the occurrence of the abnormal oscillation phenomenon described above is prevented. What should be noted here is that transistors Qs and Q4 are turned off at the same time. In other words, even if one of the transistors Qs = Q4 is turned off, the other transistor operates and Q
There is no problem that the duty ratios of the output and Q output are different.
次に、上記７リツプフロツプ回路ＦＦを利用したステレ
オ復調回路の回路動作を述べる。なお、第３図に示すス
テレオ復調回路においては、ｌ／２分周器６． ７．
８に上記フリップフロップ回路ＦＦが利用され、電池Ｅ
から供給される＋Ｖｃｃ電源がレベル低下すると電圧検
出器２０から得られる制御信号Ｐ。によって、１／２分
周器６． ７． ８につき上記同様の回路動作が行われ
、上記発振現象等は発生しない。Next, the circuit operation of the stereo demodulation circuit using the above seven lip-flop circuit FF will be described. Note that in the stereo demodulation circuit shown in FIG. 3, the l/2 frequency divider 6. 7.
8, the flip-flop circuit FF is used, and the battery E
A control signal P obtained from the voltage detector 20 when the +Vcc power supply supplied from the +Vcc power supply decreases in level. 1/2 frequency divider 6. 7. 8, the same circuit operation as above is performed, and the above-mentioned oscillation phenomenon does not occur.
また、前置増幅器ｌ２位相検波器２．ローパスフィルタ
３．直流増幅器４．電圧制御発振器１０゜ステレオデコ
ーダ１１．ステレオスイッチ１２゜更にローパスフィル
タ１３．ヒステリシストリガー回路１４．ステレオラン
プドライバー回路１５の回路構成と回路動作とは当業者
において周知であるので、その説明を省略する。しかし
、＋Ｖ、。Also, the preamplifier l2 phase detector 2. Low pass filter 3. DC amplifier 4. Voltage controlled oscillator 10° stereo decoder 11. Stereo switch 12° and low pass filter 13. Hysteresis trigger circuit 14. Since the circuit configuration and circuit operation of the stereo lamp driver circuit 15 are well known to those skilled in the art, their explanation will be omitted. However, +V.
電源のレベル低下時においては、１／２分周器６゜７．
８として設げられ７リツプフロツプ回路の発振現象が防
止され、しかもステレオスイッチ１２がインバータ２１
の出力によって完全にオフ状態になされるので、ステレ
オスイッチ１２おら３８ＫＨｚ副搬送波信号がデコーダ
１１に供給されない。従って、上記ステレオ復調回路に
おいては、十■。。When the power level drops, the 1/2 frequency divider 6°7.
8, the oscillation phenomenon of the 7 lip-flop circuit is prevented, and the stereo switch 12 is connected to the inverter 21.
Since the stereo switch 12 is completely turned off by the output of the stereo switch 12, no 38 KHz subcarrier signal is supplied to the decoder 11. Therefore, in the above-mentioned stereo demodulation circuit, 1. .
電源がレベル低下してもＲ信号とＬ信号間の分離度が低
下することもない。Even if the level of the power supply decreases, the degree of separation between the R signal and the L signal does not decrease.
（１）ステレオ復調回路を構成する分周器の動作を電源
電圧のレベル低下を検出して強制的に完全停止さること
により、分局器として設けられたフリップフロップ回路
の発振現象にもとづ（妨害波の発生等を完全に防止する
ことができる。(1) The operation of the frequency divider constituting the stereo demodulation circuit is forcibly stopped completely by detecting a drop in the level of the power supply voltage, and the operation is based on the oscillation phenomenon of the flip-flop circuit provided as the divider. The generation of interference waves can be completely prevented.
（２）上記（１）の回路動作と同時に、ステレオスイッ
チ１２の回路動作を完全に停止することにより、デコー
ダへの副搬送信号の供給がなく、Ｒ信号とＬ信号間の分
離度の低下を防止することができる。(2) By completely stopping the circuit operation of the stereo switch 12 at the same time as the circuit operation in (1) above, the subcarrier signal is not supplied to the decoder, and the degree of separation between the R signal and the L signal is reduced. It can be prevented.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野であるステレオ復調回路
について説明したが、それに限定されるものではない。In the above description, the invention made by the present inventor has mainly been described with respect to a stereo demodulation circuit, which is the field of application behind the invention, but the invention is not limited thereto.
例えば、上記フリップフロップ回路は、各種計数回路に
利用することができる。For example, the flip-flop circuit described above can be used in various counting circuits.
第１図は本発明の一実施例を示すフリップフロップ回路
の回路図を示し、
第２図（５）ＣＢ）（Ｃ）は上記フリップフロップ回路
の回路動作を説明する波形図を示し、
第３図は上記フリップフロップ回路を分局器として用い
たステレオ復調回路の回路図を示す。
ＦＦ・・・フリップフロップ回路、６，７．８・・・分
周器、２０・・・電圧検出回路、Ｑ、 、 Ｑ２． Ｑ
３． Ｑ、。
Ｑ、、Ｑｌ・・１ランジスタ、Ｐｏ・・・制御信号、Ｅ
・・・バッテリ。
−１−FIG. 1 shows a circuit diagram of a flip-flop circuit showing an embodiment of the present invention, FIG. 2 (5) CB) (C) shows a waveform diagram explaining the circuit operation of the flip-flop circuit, and The figure shows a circuit diagram of a stereo demodulation circuit using the above-mentioned flip-flop circuit as a divider. FF...Flip-flop circuit, 6, 7.8... Frequency divider, 20... Voltage detection circuit, Q, , Q2. Q
3. Q. Q, ,Ql...1 transistor, Po...control signal, E
···Battery. -1-
Claims (1)
ンジスタと、上記一対のトランジスタに対しそれぞれ設
けられ、上記一対のトランジスタを強制的に動作停止と
なす一対のスイッチングトランジスタと、電源電圧のレ
ベル低下を検出し上記一対のスイッチングトランジスタ
を駆動する電圧検出回路とからなるフリップフロップ回
路により分局動作を行うことを特徴とするステレオ復調
回路。1.) A pair of transistors that obtain a phase-inverted output in response to a trigger signal, a pair of switching transistors that are provided for each of the pair of transistors and forcibly stop the operation of the pair of transistors, and a pair of switching transistors that forcibly stop the operation of the pair of transistors, and A stereo demodulation circuit characterized in that a channel splitting operation is performed by a flip-flop circuit comprising a voltage detection circuit that detects a voltage and drives the pair of switching transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7856584A JPS60223348A (en) | 1984-04-20 | 1984-04-20 | Fm multiplex demodulating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7856584A JPS60223348A (en) | 1984-04-20 | 1984-04-20 | Fm multiplex demodulating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60223348A true JPS60223348A (en) | 1985-11-07 |
| JPH0451100B2 JPH0451100B2 (en) | 1992-08-18 |
Family
ID=13665416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7856584A Granted JPS60223348A (en) | 1984-04-20 | 1984-04-20 | Fm multiplex demodulating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60223348A (en) |
-
1984
- 1984-04-20 JP JP7856584A patent/JPS60223348A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0451100B2 (en) | 1992-08-18 |
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