JPS60214536A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60214536A
JPS60214536A JP12297384A JP12297384A JPS60214536A JP S60214536 A JPS60214536 A JP S60214536A JP 12297384 A JP12297384 A JP 12297384A JP 12297384 A JP12297384 A JP 12297384A JP S60214536 A JPS60214536 A JP S60214536A
Authority
JP
Japan
Prior art keywords
chip
back surface
grooves
stage
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12297384A
Other languages
Japanese (ja)
Inventor
Nobuhiko Mizuo
水尾　允彦
Noboru Ando
昇 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12297384A priority Critical patent/JPS60214536A/en
Publication of JPS60214536A publication Critical patent/JPS60214536A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Abstract

PURPOSE:To prevent void generation in the back surface of the chip, to improve the thermal conduction to conduct from the chip and to suppress it for the IC to be broken due to heat by a method wherein grooves, which respectively intersect orthogonally the central part of the back surface of the chip, are formed in the back surface of the semiconductor chip, and after that, the back surface is fusion-welded with the stage of the semiconductor package. CONSTITUTION:Grooves 2 have been formed in a cross configuration across the central point of the back surface of a chip. A chip 1, wherein such the grooves 2 have been provided, is used when this semiconductor device is manufactured. A gold-silicon pellet 11 is made to interpose between the stage 10 of a package and the chip 1 and the pellet 11 is made to melt by heating the package. When the chip 1 is made to slidingly move in that condition, the melted pellet adheres on the lower surface of the chip 1 and the upper surface of the stage 10 and the chip 1 and the stage 10 are fusion-welded. When there exist the grooves 2 in the lower surface of the chip 1, the wettability of the chip 1 is improved and the generation of voids is decreased.

Description

【発明の詳細な説明】 ＋ａ）　発明の技術分野 本発明は半導体装置の製造方法にかかり、特に半導体チ
ップのチップ付け（ダイス付け）方法に関する。DETAILED DESCRIPTION OF THE INVENTION +a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for attaching (dicing) a semiconductor chip.

（ｂｌ　従来技術と問題点 周知のように、ＩＣなどの半導体装置はウェハー面に多
数の素子が形成され、これを裁断して半導体チップとし
た後、半導体パッケージ（半導体容器）に取付けが行な
われている。これをチップ付は又はダイス付は工程と呼
んでいるが、それは一般に金シリコンの共晶点を利用し
た金シリコン溶着法で接着させている。(bl) Prior Art and Problems As is well known, in semiconductor devices such as ICs, a large number of elements are formed on a wafer surface, which are cut into semiconductor chips and then attached to a semiconductor package (semiconductor container). This is called a chip attaching or die attaching process, and it is generally bonded using a gold-silicon welding method that utilizes the eutectic point of gold-silicon.

即ち、金（Ａｕ）とシリコン（Ｓｔ）の合金は３７０℃
に共晶点を持つために、例えばシリコンチップの場合に
は、半導体パンケージを４００〜４５０℃に加熱し、パ
ンケージのステージとシリコンチップとの間に金ペレッ
ト（金薄板）を挟んで、シリコンチップに機械的な摺動
を与え、共晶合金を作成してシリコンチップをパンケー
ジに溶着させる。That is, the alloy of gold (Au) and silicon (St) is heated to 370°C.
For example, in the case of a silicon chip, in order to have a eutectic point at Apply mechanical sliding to create a eutectic alloy and weld the silicon chip to the pancage.

又、シリコシ以外のチップ、例えばガリウム砒素チップ
では金ベレットの代わりに金シリコンペレット（正確に
は金シリコン共晶合金ベレット）を用いて、パンケージ
に溶着がなされ、またシリコンチップにも金シリコンペ
レットが使用されており、更にペレットの代わりに銀ペ
ーストも使用されている。In addition, chips other than silicon chips, such as gallium arsenide chips, are welded to the pan cage using gold-silicon pellets (more precisely, gold-silicon eutectic alloy pellets) instead of gold pellets, and gold-silicon pellets are also used for silicon chips. silver paste is also used instead of pellets.

ところで、ＩＣの集積度の向上に伴って、半導体チップ
は益々大きくなっており、汎用されているＩＣチップが
３〜５鰭角程度、更に大きなチップでは一辺が１０ｍ１
近いものまで現れ、著しく大形化してきた。そのために
摺動して溶着しても、チップ背面が完全に濡れず（溶着
せず）にボイド（空孔）が多く発生する問題が起こって
いる。この問題は、金ペレットの代わりに融点の低い金
シリコンペレットや銀ペーストを使用しても同様であり
、一般にチップの周縁（エツジ）部分は良く濡れるが、
中央部分に特に多くのボイドが発生し易い問題がある。By the way, with the improvement in the degree of integration of ICs, semiconductor chips are becoming larger and larger.General-purpose IC chips are about 3 to 5 fin angles, and even larger chips have a side of 10 m1.
Even similar ones have appeared and have become noticeably larger. For this reason, even if the chips slide and are welded, the back surface of the chip is not completely wetted (welded) and many voids (holes) are generated. This problem is the same even if gold-silicon pellets or silver paste, which have a low melting point, are used instead of gold pellets; generally, the edges of the chip are well wetted, but
There is a problem in that many voids are likely to occur particularly in the central portion.

このように、チップ背面の中央部分にボイドが発生する
と、チップからパッケージへの熱の伝導が悪くなってＩ
Ｃ動作中にチップが高温度に熱せられ、ＩＣが破壊する
重大な欠陥となる。When a void occurs in the center of the back of the chip, heat conduction from the chip to the package becomes poor and the I
During C operation, the chip is heated to a high temperature, resulting in a serious defect that can destroy the IC.

ｆｃｌ　発明の目的 本発明は、このようなチップ背面のボイドを解消させる
チップ付は方法を提案するものである。fcl OBJECTS OF THE INVENTION The present invention proposes a chip mounting method that eliminates such voids on the back surface of the chip.

（ｄ＋　発明の構成 その目的は、半導体チップの背面に、中央部分を通る溝
を形成し、しかる後に半導体パッケージに溶着するよう
にした半導体装置の製造方法によって達成される。(d+) Structure of the Invention The object is achieved by a method of manufacturing a semiconductor device, in which a groove passing through the center portion is formed on the back surface of a semiconductor chip, and the groove is then welded to a semiconductor package.

（ｅｌ　発明の実施例 以下１図面を参照して実施例によって詳細に説明する。(el　Embodiments of the invention An embodiment will be described in detail below with reference to one drawing.

第１図は本発明にがかる一実施例を示しており、同図は
チップ１の背面図である。２が本発明にかかる溝で、本
例ではチップ中心点を横切って十字形状にａ２が形成さ
れている。このような溝２を設けたチップ１を用いて、
第２図に示すようにパッケージのステージ１０とチップ
１との間に金シリコンペレット１１を介在させ、パンケ
ージを加熱してペレット１１を溶解させる。その状態で
、チップを摺動すれば溶解ペレットがチップ１とステー
ジ１０とに付着し、両者が溶着される。この場合、チッ
プ１に溝２が存在すると、濡れが良くなってボイドの発
生が少なくなる。これは、チップ周囲のエツジと同様に
、溝両側のエツジが速く濡れ易くて、しかも溝内を通っ
てガスが逃げ易いからと考えられる。FIG. 1 shows an embodiment according to the present invention, and this figure is a rear view of a chip 1. As shown in FIG. 2 is a groove according to the present invention, and in this example, a2 is formed in a cross shape across the center point of the chip. Using the chip 1 provided with such a groove 2,
As shown in FIG. 2, gold silicon pellets 11 are interposed between the stage 10 of the package and the chip 1, and the pellets 11 are melted by heating the pan cage. If the chip is slid in this state, the molten pellets will adhere to the chip 1 and the stage 10, and the two will be welded together. In this case, the presence of the groove 2 in the chip 1 improves wetting and reduces the occurrence of voids. This is thought to be because, like the edges around the chip, the edges on both sides of the groove tend to get wet quickly and gas easily escapes through the groove.

このような溝の形成は、チップに裁断する前の工程で、
第３図に示すようにウェハー３の状態ままダイシングま
たはエツチングによって行なうのが望ましく、例えば溝
２の形状を幅０．５　ｔｍ前後。Formation of such grooves is done in the process before cutting into chips.
As shown in FIG. 3, it is preferable to perform dicing or etching while the wafer 3 is in the state. For example, the grooves 2 are shaped to have a width of about 0.5 tm.

深さ５〜１０μｍの直線状に形成する。この程度の深さ
に形成すれば、チップ裁断の時にも悪影響は与えない。Form in a straight line with a depth of 5 to 10 μm. If the depth is formed to this extent, there will be no adverse effect when cutting the chip.

尚、図の点線はチップ形状を示す。Note that the dotted line in the figure indicates the chip shape.

第４図（ａ）、　（ｂ）は本発明にかかる他のチップ背
面図で、満４，５の形状を例示している。同図ｉａｌの
ように１本の溝４だけでもその効果がある。要するに、
本発明のポイントはボイドの発生し易いチップ背面の中
央部分に溝を形成し、そのエツジ部分からの濡れを良く
して、ボイドの発生を防止するものである。FIGS. 4(a) and 4(b) are rear views of other chips according to the present invention, illustrating the shape of 4.5. Even just one groove 4, as shown in FIG. ial, has this effect. in short,
The key point of the present invention is to form a groove in the central part of the back surface of the chip, where voids are likely to occur, and to improve wetting from the edge portion, thereby preventing the occurrence of voids.

（ｆｌ　発明の効果 以上の説明から明らかなように、本発明によればチップ
からの熱伝導が良くなり、ＩＣの熱破壊が抑止されて、
ＩＣの信頼性向上に顕著な効果が得られる。(fl Effects of the Invention As is clear from the above explanation, according to the present invention, heat conduction from the chip is improved, thermal destruction of the IC is suppressed,
A remarkable effect can be obtained in improving the reliability of the IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第４図ｉａ）、　（ｂ）は本発明にかかる
溝を形成したチップの背面図、第２図はチップ付けを説
明する断面図、第３図は本発明にかかる溝を形成する工
程のウェハーの背面図である。 図中、１はチップ、２，４．５は溝、３はウェハー、１
０はパッケージのステージ、　１１は金シリコンペレッ
トを示している。 第１図 第２図 第３図 ７千江〕＼７７゜ 特開昭ＧＯ−２１４５３６（３） 第４ｅ！ｊ ／　１　／Figures 1 and 4 (ia) and 4 (b) are rear views of chips with grooves according to the present invention formed therein, Figure 2 is a sectional view illustrating chip attachment, and Figure 3 shows grooves formed according to the present invention. FIG. 3 is a rear view of the wafer in the step of In the figure, 1 is a chip, 2, 4.5 is a groove, 3 is a wafer, 1
0 indicates the stage of the package, and 11 indicates the gold silicon pellet. Figure 1 Figure 2 Figure 3 7 Chie] ＼77° JP-A-Sho GO-214536 (3) 4th e! j / 1 /

Claims (1)

【特許請求の範囲】[Claims] 半導体チップの背面に、中央部分を通る溝を形成し、し
かる後に半導体パッケージに溶着するようにしたことを
特徴とする半導体装置の製造方法A method for manufacturing a semiconductor device, characterized in that a groove passing through the center of the semiconductor chip is formed on the back surface of the semiconductor chip, and then the semiconductor chip is welded to a semiconductor package.
JP12297384A 1984-04-09 1984-04-09 Manufacture of semiconductor device Pending JPS60214536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12297384A JPS60214536A (en) 1984-04-09 1984-04-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12297384A JPS60214536A (en) 1984-04-09 1984-04-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60214536A true JPS60214536A (en) 1985-10-26

Family

ID=14849163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12297384A Pending JPS60214536A (en) 1984-04-09 1984-04-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60214536A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819857A (en) * 1986-10-17 1989-04-11 Hitachi, Ltd. Method for fabricating composite structure
US5063177A (en) * 1990-10-04 1991-11-05 Comsat Method of packaging microwave semiconductor components and integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819857A (en) * 1986-10-17 1989-04-11 Hitachi, Ltd. Method for fabricating composite structure
US5063177A (en) * 1990-10-04 1991-11-05 Comsat Method of packaging microwave semiconductor components and integrated circuits

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