JPS6020661U - calculation circuit - Google Patents
calculation circuitInfo
- Publication number
- JPS6020661U JPS6020661U JP11232283U JP11232283U JPS6020661U JP S6020661 U JPS6020661 U JP S6020661U JP 11232283 U JP11232283 U JP 11232283U JP 11232283 U JP11232283 U JP 11232283U JP S6020661 U JPS6020661 U JP S6020661U
- Authority
- JP
- Japan
- Prior art keywords
- signals
- numerical
- keyed
- storage device
- calculated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Calculators And Similar Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案に係る計算回路を内蔵した電卓の平面図
、第2図は本考案に係る計算回路のブロック図である。
第3図は記憶装置の記憶内容を示す説明図である。
1・・・表示装置、2・・・キーボード、3・・・デコ
ーダ・レジスタ、4・・・駆動回路、5・・・表示装置
、6・・・制御装置、7・・・計算ユニット、8・・・
記憶装置、9・・・比較器、10・・・点滅回路。FIG. 1 is a plan view of a calculator incorporating a calculation circuit according to the present invention, and FIG. 2 is a block diagram of the calculation circuit according to the present invention. FIG. 3 is an explanatory diagram showing the contents stored in the storage device. DESCRIPTION OF SYMBOLS 1... Display device, 2... Keyboard, 3... Decoder register, 4... Drive circuit, 5... Display device, 6... Control device, 7... Computation unit, 8 ...
Storage device, 9... Comparator, 10... Flashing circuit.
Claims (3)
コーダレジスタと、キーインされた順序により数値信号
、演算信号を記憶する記憶装置と、キーインされた数値
信号、演算信号と記憶装置に記憶された数値信号、演算
信号とを比較する比較回路と、比較の結果下一致桁を含
めて不一致を表示する表示回路と、制御信号により前記
デコーダレジスタ、記憶装置、比較回路、表示回路を制
御する制御回路とからなる計算回路。(1) A decoder register that detects the keyed-in numerical signals and calculated signals, a storage device that stores the numerical signals and calculated signals according to the keyed-in order, and a decoder register that detects the keyed-in numerical signals and calculated signals, and a storage device that stores the keyed-in numerical signals and calculated signals in the storage device. A comparison circuit that compares numerical signals and arithmetic signals, a display circuit that displays a discrepancy including the lower matching digit as a result of the comparison, and a control circuit that controls the decoder register, storage device, comparison circuit, and display circuit using control signals. A calculation circuit consisting of.
する数値信号、演算信号と記憶装置に記憶された数値信
号、演算信号を逐次読る出し、比較器で比較する実用新
案登録請求の範囲第1項記載の計算回路。(2) In the verification mode, the control circuit sequentially reads out the keyed-in numerical signal, the calculated signal, and the numerical signal and calculated signal stored in the storage device, and compares them with a comparator.Claim 1. The calculation circuit described.
コーダ・レジスタにキーインされた数値、演算信号を対
応する記憶装置の内容に置換信号により置換するところ
の実用新案登録請求の範囲第1項又は第2項記−の計算
回路。(3) When the comparison result of the comparator shows a discrepancy, the numerical value and operation signal keyed into the decoder register are replaced with the contents of the corresponding storage device by a replacement signal, Claim 1 2. Calculation circuit for item 2 or item 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11232283U JPS6020661U (en) | 1983-07-21 | 1983-07-21 | calculation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11232283U JPS6020661U (en) | 1983-07-21 | 1983-07-21 | calculation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6020661U true JPS6020661U (en) | 1985-02-13 |
Family
ID=30260427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11232283U Pending JPS6020661U (en) | 1983-07-21 | 1983-07-21 | calculation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6020661U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0626044A (en) * | 1992-04-21 | 1994-02-01 | Toyo Kensetsu Kk | Process for leveling underwater rubble mound |
-
1983
- 1983-07-21 JP JP11232283U patent/JPS6020661U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0626044A (en) * | 1992-04-21 | 1994-02-01 | Toyo Kensetsu Kk | Process for leveling underwater rubble mound |
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