JPS6020651A - Control system of optical multiplex transmitter - Google Patents

Control system of optical multiplex transmitter

Info

Publication number
JPS6020651A
JPS6020651A JP58129079A JP12907983A JPS6020651A JP S6020651 A JPS6020651 A JP S6020651A JP 58129079 A JP58129079 A JP 58129079A JP 12907983 A JP12907983 A JP 12907983A JP S6020651 A JPS6020651 A JP S6020651A
Authority
JP
Japan
Prior art keywords
input
output
group
groups
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58129079A
Other languages
Japanese (ja)
Inventor
Yukio Yoshimoto
幸生 吉本
Yoshiaki Matsudaira
松平　義昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP58129079A priority Critical patent/JPS6020651A/en
Publication of JPS6020651A publication Critical patent/JPS6020651A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To reduce the number of data buses by giving two conrol signals of logical H and L to buses on a mother board and also dividing circuits of modules into two groups so as to apply the level of logical H to one group and logical L to the other. CONSTITUTION:The 16 input/output circuits of the input/output module 1 are divided into two groups (8 each) and 9 data buses 3 are provided on the mother board 2. The 8 input/output circuits of one group are connected in parallel with an output register 4 in the input/output module and the 8 input/output circuits of the other group are connected in parallel with the output register 4. Further, a control bus 5 having two statuses of logical H and L is provided. Then the changeover of one and other groups of the input/output module is executed by the signals H, L given via the control bus 5 on the mother board.

Description

【発明の詳細な説明】 この発明は光多重伝送機の制御方式に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for an optical multiplex transmitter.

従来の光多重伝送機は入出カモジュール玉の入出力点数
と同数のデータバスがマザーボードに用意され、両者は
１対１で接続される。原価低減のため１つのモジュール
に設ける入出力点数が多くなると、マザーボード上のデ
ータバスの本数が多くなるばかりかその限界に達するお
それが発生する。In a conventional optical multiplex transmitter, the motherboard has the same number of data buses as the number of input/output points of the input/output module, and the two are connected one-to-one. If the number of input/output points provided in one module increases in order to reduce costs, the number of data buses on the motherboard will not only increase, but may also reach its limit.

この発明はデータバスをさほど増加させず、逆にモジュ
ール上の点数を増加させることによりデータのＩｌｏを
行う方式を提供しようとするものである。This invention attempts to provide a method for performing Ilo of data by increasing the number of points on a module without significantly increasing the number of data buses.

すなわちこの発明においてはマザーボード上のデータバ
スの数を入出カモジュールの入出力点数の半分たとえば
図に示すように入出カモジュール１の入出力回路１６点
を８点ずつ２つの群に分割し、一方マザーボード２上の
データバス３を８本設ける。そして入出カモジュール１
において一方の群の入出力回路たとえば１〜８の８魚を
並列にまとめて出力レジスタ４に接続するとともに他方
の群の入出力回路たとえば９〜１６の８点を並列に１と
めて出力レジスタ４に接続する。That is, in this invention, the number of data buses on the motherboard is half the number of input/output points of the input/output module.For example, as shown in the figure, the 16 input/output circuits of the input/output module 1 are divided into two groups of 8 points each; Eight data buses 3 on the motherboard 2 are provided. And input/output module 1
Input/output circuits of one group, for example, 8 fishes 1 to 8 are connected in parallel to the output register 4, and input/output circuits of the other group, for example, 8 points of 9 to 16 are connected to 1 in parallel and connected to the output register 4. Connect to.

またコントロールバス５は１本用意され、この：ｌ　７
　）　ｕ−ルバスハ論理的にＨ，Ｌの２つのステイタス
を有している。そして入出カモジュール１の一方の群と
他方の群との切換えはマザーボード２上のコントロール
バス５を経て与えられる信号Ｈ，Ｌにより実行される。Also, one control bus 5 is prepared, this: l7
) The u-ru bus has logically two statuses: H and L. Switching between one group and the other group of input/output modules 1 is executed by signals H and L applied via a control bus 5 on the motherboard 2.

なお上記実施例においては入出カモジュール１の回路点
数を８点ずつ等しく２群に分割したが、その点数は任意
に調整しうることは言うまでもない。In the above embodiment, the number of circuit points of the input/output module 1 is equally divided into two groups of 8 points each, but it goes without saying that the number of circuit points can be adjusted as desired.

この発明はＥ述のようにマザーボード上のバスに論理的
にＨとＬの２つの制御信号を与えるとともに、モジュー
ルの回路を２つの群に分割し、一方の群に対して論理Ｈ
を、また他方の群に対して論理りを作用させ、同一のバ
スを用いて２つの群の回路のデータの受授を一括して行
うので、データバスの数をモジュールの入出力点数の半
分以下に減少させることができ、したがってマザーボー
ド上のバスを減少させることができる。As described in E, this invention logically provides two control signals, H and L, to the bus on the motherboard, divides the module circuit into two groups, and sends a logic H signal to one group.
In addition, logic is applied to the other group, and the same bus is used to receive and receive data from the circuits of the two groups, so the number of data buses can be reduced to half the number of input/output points of the module. The number of buses on the motherboard can therefore be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

図はこの発明の一実施例を示す側面図である。 １・・・入出カモジュール、２・・・マザーボート、３
・・・データバス、４・・・出力レジスタ、５・φ・コ
ントロールバス。The figure is a side view showing an embodiment of the present invention. 1... Input/output module, 2... Motherboard, 3
...Data bus, 4.Output register, 5.φ.Control bus.

Claims (1)

【特許請求の範囲】[Claims] 複数個の入力または出力回路を持つプリント回路板モジ
ュールを必要な数だけ筐体内のマザーボードに組付けて
なる光多重伝送機の入出力部において上記マザーボード
上のバスに論理的にＨとＬの２つの制御信号を与えると
ともに、上記モジュールの回路を２つの群に分割し、一
方の群に対して論理Ｈを、また他方の群に対して論理り
を作用させ、同一のバスを用いて２つの群の回路のデー
タの受授を一括して行なう光多重伝送機の制御方式。In the input/output section of an optical multiplex transmitter, which has a required number of printed circuit board modules each having a plurality of input or output circuits assembled on a motherboard in a housing, two buses, H and L, are logically connected to the buses on the motherboard. At the same time, the circuit of the module is divided into two groups, a logic H is applied to one group, and a logic logic is applied to the other group, and two control signals are applied using the same bus. A control method for optical multiplex transmitters that collectively receives and receives data from a group of circuits.
JP58129079A 1983-07-15 1983-07-15 Control system of optical multiplex transmitter Pending JPS6020651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58129079A JPS6020651A (en) 1983-07-15 1983-07-15 Control system of optical multiplex transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58129079A JPS6020651A (en) 1983-07-15 1983-07-15 Control system of optical multiplex transmitter

Publications (1)

Publication Number Publication Date
JPS6020651A true JPS6020651A (en) 1985-02-01

Family

ID=15000555

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58129079A Pending JPS6020651A (en) 1983-07-15 1983-07-15 Control system of optical multiplex transmitter

Country Status (1)

Country Link
JP (1) JPS6020651A (en)

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