JPS60206218A - Initial clearing circuit - Google Patents
Initial clearing circuitInfo
- Publication number
- JPS60206218A JPS60206218A JP6064584A JP6064584A JPS60206218A JP S60206218 A JPS60206218 A JP S60206218A JP 6064584 A JP6064584 A JP 6064584A JP 6064584 A JP6064584 A JP 6064584A JP S60206218 A JPS60206218 A JP S60206218A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- zener diode
- vcc
- zener
- constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Landscapes
- Structure Of Printed Boards (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、イニシャルクリア回路の改良により、回路定
数の設定が容易になり、またプリント基板の設計上パタ
ーンの引回しが容易になる等の特徴をもつ、イニシャル
クリア回路である。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention has features such as improved initial clear circuits, which make it easier to set circuit constants, and make it easier to route patterns in the design of printed circuit boards. This is an initial clear circuit with
従来のイニシャルクリア回路は、第1図に示すように、
ツェナーダイヤードZi)zのカソード側がVC側に接
続されていたために、イニ/ヤルクリア回路の電源とし
てはVcと+Vccの2戒源が必要となり、プリント基
板のパターン設計時も電源2本を引回してこなければな
らr1パター/設計が複雑になるという欠点があった。The conventional initial clear circuit, as shown in Figure 1,
Since the cathode side of the Zener diamond Zi)z was connected to the VC side, two power sources, Vc and +Vcc, were required as the power supply for the initial clear circuit, and two power sources were routed when designing the printed circuit board pattern. The disadvantage was that the r1 putter/design was complicated.
また、4源投入時の回路の動作を説明すると、ZDlと
ほぼ等しい電圧をもったツェナーダイオードを介し、次
に几Cの時定数回路を通してトランジスタをIK動rる
ことにより、一定期間リセットri号を発生させること
ができる。以上のことを、第6図に示すタイムチャート
により説明すると、VCの電位がツェナーダイオードZ
D2のツェナー成田に達すると、ツェナーダイオードZ
D2に4流が流ればじめ、0点の電位はCルの時定数回
路により上昇しはじめ、トランジスタ1のスレツシコヤ
ド・ノベルを越えたところでトランジスタ1がオンし、
出力としては、第6図に示すように一定期間リセット信
号を発生させることができる。しかし、ツェナーダイオ
ードZDzのツェナー成田は、VCと+Vccの上昇の
時定aVcよし、設定する必要があり、また、RCの時
定数もツェナー成田に関係してくる等、回路定数の設定
がかなり複雑であった。Also, to explain the operation of the circuit when four sources are turned on, the reset signal is reset for a certain period of time by driving the transistor through a Zener diode with a voltage almost equal to ZDl, and then through a time constant circuit of 几C. can be generated. To explain the above using the time chart shown in FIG.
When the Zener Narita of D2 is reached, the Zener diode Z
4 currents begin to flow through D2, the potential at the 0 point begins to rise due to the time constant circuit of C, and when it crosses the threshold of transistor 1, transistor 1 turns on.
As an output, a reset signal can be generated for a certain period of time as shown in FIG. However, the Zener Narita of the Zener diode ZDz requires setting the time constant aVc for the rise of VC and +Vcc, and the RC time constant is also related to the Zener Narita, so setting the circuit constants is quite complicated. Met.
従来のイニシャルクリア回路は電源としてVcと+Vc
cの21を源が必要であった。このことが、ブリット基
板のパターン引回しの複雑化および回路定数設定の複雑
さに起因していることを発見し、電源を+Vccの1つ
にすることにより、上記問題点の解決しようとするのが
本発明である。The conventional initial clear circuit uses Vc and +Vc as power supplies.
A source of 21 c was required. They discovered that this was due to the complexity of the pattern routing and circuit constant settings for the bullet board, and tried to solve the above problem by changing the power supply to +Vcc. is the present invention.
以下、本発明の一実施例全第2.4図によシ、説明する
。Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 2.4.
第2図は、本発明のイニ/ヤルクリア回路である。ツェ
ナーダイオードZD2のツェナー電圧はツェナーダイオ
ードZlhより少し低く設定する。また、ツェナーダイ
オードZD2のカソード−は+Vccに1妾続しである
。第4因は、第2図の回路のタイムチャートである。以
下、本回路の動作説明を行う。電源投入時、VCと+V
ccは第4図のように時定数をもって上昇してくる。+
VccがツェナーダイオードZD2のツェナー電圧に達
するとツェナーダイオードZD2に4流が流れはじめ、
Cルの時定紋により、07点の電位は図のように上昇し
てくる。FIG. 2 shows the initial clear circuit of the present invention. The Zener voltage of the Zener diode ZD2 is set to be slightly lower than that of the Zener diode Zlh. Further, the cathode of the Zener diode ZD2 is connected to +Vcc. The fourth factor is the time chart of the circuit in FIG. The operation of this circuit will be explained below. When power is turned on, VC and +V
cc increases with a time constant as shown in FIG. +
When Vcc reaches the Zener voltage of Zener diode ZD2, four currents begin to flow through Zener diode ZD2,
Due to the time pattern of C, the potential at point 07 rises as shown in the figure.
07点の電位がトランジスタ1のスレソショルト威圧を
越えるとトランジスタ1はオンし、出力としては図のよ
うに、一定期間のリセット信号を発生させることができ
る。以上のように、第1図に示す従来のイニシャルクリ
ア回路と同様なリセット信号が得られている。本実施例
によれば、電源は+Vccの14源で回路構成が可能と
なり、ツェナーダイオードZDzのツェナー電圧の選定
はツェナーダイオードZlhのツエ大−亀圧より少し低
くければ良いので比較的容易に選定でき、Cルの時定数
は、トランジスタ1のシレツショルド電圧より、容易に
設定できるので、回路定数の設定が容易となる利点があ
る。また、従来に比べvC亀源が不要となったので、プ
リント基板のパターン設定も容易になる。When the potential at point 07 exceeds the threshold of transistor 1, transistor 1 is turned on, and as an output, a reset signal for a certain period of time can be generated as shown in the figure. As described above, a reset signal similar to that of the conventional initial clear circuit shown in FIG. 1 is obtained. According to this embodiment, it is possible to configure a circuit with 14 +Vcc power sources, and the Zener voltage of the Zener diode ZDz can be selected relatively easily since it only needs to be a little lower than the Zener voltage of the Zener diode Zlh. Since the time constant of C can be set more easily than the threshold voltage of transistor 1, there is an advantage that the circuit constant can be set easily. Furthermore, since a vC source is no longer required compared to the conventional method, pattern setting of the printed circuit board becomes easier.
本発明によれば、従来のイニシャルクリア回路に比べ、
電源が+Vccの1成源でできるので、プリント基板の
パターン設計が容易になり、回路定数の設定も容易にな
るという効果がある。According to the present invention, compared to the conventional initial clear circuit,
Since the power source can be generated from a single source of +Vcc, the pattern design of the printed circuit board is facilitated, and the setting of circuit constants is also facilitated.
第1図は従来のイニシャルクリア回路、第2図は本発明
のイニシャルクリア回路、第3図は第1図の回路のタイ
ムチャート、第4図は第2図の回路のタイムチャートで
ある。
1・・・トランジスタ、2・・・電源、6・・・電源ト
ランス。
代理人弁理士 高 橋 明 夫
早1図
$20
4ニラマ)し7′ノア(5)ν11 is a conventional initial clear circuit, FIG. 2 is an initial clear circuit of the present invention, FIG. 3 is a time chart of the circuit of FIG. 1, and FIG. 4 is a time chart of the circuit of FIG. 2. 1...Transistor, 2...Power supply, 6...Power transformer. Agent Patent Attorney Akira Takahashi 1 Figure $20 4 Nirama) 7' Noah (5) ν1
Claims (1)
ジスタよ#)成るイニシャルクリア回路において、ツェ
ナーダイオードZDzのカソード側を、−)−Vcc
Kd続したことを特徴とするイニシャルクリア回路。In an initial clear circuit consisting of a Zener diode ZD2, a resistor, a capacitor, and a transistor, the cathode side of the Zener diode ZDz is connected to -) -Vcc.
An initial clear circuit characterized by Kd continuity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6064584A JPS60206218A (en) | 1984-03-30 | 1984-03-30 | Initial clearing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6064584A JPS60206218A (en) | 1984-03-30 | 1984-03-30 | Initial clearing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60206218A true JPS60206218A (en) | 1985-10-17 |
Family
ID=13148267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6064584A Pending JPS60206218A (en) | 1984-03-30 | 1984-03-30 | Initial clearing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60206218A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0300440A2 (en) * | 1987-07-22 | 1989-01-25 | Honeywell Ag | Reset circuit for microprocessors and counters |
-
1984
- 1984-03-30 JP JP6064584A patent/JPS60206218A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0300440A2 (en) * | 1987-07-22 | 1989-01-25 | Honeywell Ag | Reset circuit for microprocessors and counters |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960027301A (en) | Zero voltage switching control circuit | |
JPS60206218A (en) | Initial clearing circuit | |
WO1997008823A2 (en) | Circuit arrangement provided with a voltage - current converter | |
US6756746B2 (en) | Method of delaying and sequencing the starting of inverters that ballast lamps | |
JPH0115173B2 (en) | ||
JPH0119472Y2 (en) | ||
JPH0534230Y2 (en) | ||
KR940002451Y1 (en) | Power supply circuit for power saving | |
JPH0527347B2 (en) | ||
JPH0321082Y2 (en) | ||
KR910010267A (en) | Constant voltage circuit | |
KR970024475A (en) | Multi output control method of the SMPS | |
KR900001904Y1 (en) | Constant current driving circuit for a switching mode power circuit | |
JPH022704A (en) | Driving circuit for semiconductor switching device | |
JP3119585B2 (en) | Reverse current bypass circuit | |
JPH0722935A (en) | Switching circuit | |
JPS5931252B2 (en) | semiconductor switch device | |
KR19990011225A (en) | Frequency conversion circuit of power supply | |
JPH0374923A (en) | High voltage oscillating circuit | |
DE3486061D1 (en) | OSCILLATOR CIRCUIT. | |
JPH07288074A (en) | Relay drive circuit | |
JPH0693621B2 (en) | Two-wire type electronic switch | |
MY120758A (en) | Apparatus using double focusing type fly-back transformer | |
JP2001258262A (en) | Constant-voltage power supply unit | |
JPH0545196A (en) | Exciting circuit of electromagnetic flowmeter |