JPS60201688A - Substrate for thick film thin film hybrid integrated circuit - Google Patents
Substrate for thick film thin film hybrid integrated circuitInfo
- Publication number
- JPS60201688A JPS60201688A JP59057456A JP5745684A JPS60201688A JP S60201688 A JPS60201688 A JP S60201688A JP 59057456 A JP59057456 A JP 59057456A JP 5745684 A JP5745684 A JP 5745684A JP S60201688 A JPS60201688 A JP S60201688A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- thin film
- thick
- film
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔技術分野〕
本発明は基板に厚膜パターン・と薄膜パターンの形成さ
れた厚膜薄膜混成集積回路用基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a thick-film-thin-film hybrid integrated circuit substrate in which a thick film pattern and a thin film pattern are formed on the substrate.
厚膜方式９例えばスクリーン印刷法によれば線幅１００
μｍ以上、厚さ１０μｍ以上の厚膜パターンが形成され
るが、該パターンは導通抵抗が低い。Thick film method 9 For example, line width 100 according to screen printing method
A thick film pattern with a thickness of 10 μm or more is formed, and the conduction resistance of the pattern is low.
大きなパワーの抵抗体が得られる。コストが安い等の長
所がある反面、高密度化、ファインパターンの形成には
限度がある。一方、近年の半導体技術の高集積化の動向
に対応する為に、薄膜方式９例えばマスク蒸着法によれ
ば線幅１００〜３０μｍ、痒さ５μｍ以下の薄膜パター
ンの形成が検討されている。そこで、厚膜、薄膜の両方
式の長所を生かして、基板に、大電力部、アース回路部
を厚膜パターンで、微細回路部、高精度回路部を薄膜パ
ターンで形成する方式、所謂。A resistor with large power can be obtained. Although it has advantages such as low cost, there are limits to high density and formation of fine patterns. On the other hand, in order to respond to the recent trend toward higher integration in semiconductor technology, the formation of thin film patterns with a line width of 100 to 30 μm and an itch of 5 μm or less using a thin film method 9, such as a mask evaporation method, is being considered. Therefore, by taking advantage of the advantages of both thick-film and thin-film methods, we have developed a so-called method in which the high power section and ground circuit section are formed using thick film patterns, and the fine circuit section and high-precision circuit section are formed using thin film patterns.
厚膜薄膜混成パターン形成方式が注目されている。Thick film/thin film hybrid pattern formation methods are attracting attention.
従来、厚膜薄膜混成パターン形成方式の一つとして、第
１図に示されるように、先ず基板（例えば、アルミナ基
板）１０の一方の面に厚膜方式（例えば、スクリーン印
刷法）で厚膜配線電極１１及び厚膜素子（例えば、抵抗
、コンデンサ等）１２からなる厚膜パターンを形成し、
更にこの厚膜パターンの形成された基板１００面に続い
て薄膜方式（例えば、蒸着マスク１３を用いたマスク蒸
着法）で薄膜配線電極（図示せず）及び薄膜素子（図示
せず）からなる薄膜パターンを形成するものがある。し
かし、この方式では。Conventionally, as one of the thick film thin film hybrid pattern forming methods, as shown in FIG. Forming a thick film pattern consisting of wiring electrodes 11 and thick film elements (for example, resistors, capacitors, etc.) 12,
Further, following the surface of the substrate 100 on which the thick film pattern is formed, a thin film consisting of thin film wiring electrodes (not shown) and thin film elements (not shown) is formed by a thin film method (for example, mask vapor deposition method using the vapor deposition mask 13). There are things that form patterns. But with this method.
基板１００表面には厚膜パターンによシ凹凸が生じてお
シ、この凹凸が次工程の薄膜方式による薄膜パターン形
成時に、蒸着マスク１３の基板１０への密着性を阻害し
、ファインパターンの形成を困難にしている。The surface of the substrate 100 has irregularities due to the thick film pattern, and these irregularities inhibit the adhesion of the evaporation mask 13 to the substrate 10 during the next process of forming a thin film pattern using the thin film method, thereby preventing the formation of a fine pattern. making it difficult.
一方、上記従来方式の欠点を解決し、集積度を上げるよ
うに改善するために、第２図に示されるように、基板１
０の一方の面に厚膜パターンを、他方の面に薄膜パター
ンを形成する方式がある（例えば、特開昭５８−６４０
９３号）。 この場合、基板１０の一方及び他方の面に
形成された厚膜パターンと薄膜パターンとの接続は、厚
膜方式により形成されたスルーホールに充填すれた内部
配線導体１４や端面メタライズ１５によって行われる。On the other hand, in order to solve the drawbacks of the above-mentioned conventional method and improve the degree of integration, a substrate 1
There is a method of forming a thick film pattern on one side of the 0 and a thin film pattern on the other side (for example, Japanese Patent Laid-Open No. 58-640
No. 93). In this case, the connection between the thick film pattern and the thin film pattern formed on one and the other surfaces of the substrate 10 is performed by the internal wiring conductor 14 filled in the through hole formed by the thick film method or the end surface metallization 15. .
しかし、この方式でも、薄膜パターン形成側の基板１０
の表面に、内部配線導体１４１Ｃよる盛−上、１）１４
ａが生じておシ、この盛上り１４ａによって蒸着マスク
１３の開孔部１３ａが拡がり。However, even in this method, the substrate 10 on the thin film pattern forming side
On the surface of the internal wiring conductor 141C, 1) 14
a is formed, and the opening 13a of the vapor deposition mask 13 expands due to this bulge 14a.
高密度のパターンの形成障害になる。又、薄膜パターン
の形成される側の基板１０の表面に付着している異物や
その表面の晶凸、キズ及び基板１０の反シ１等によシ、
蒸着マスク１３の基板１ｏへの。It becomes an obstacle to the formation of high-density patterns. In addition, foreign matter adhering to the surface of the substrate 10 on the side where the thin film pattern is formed, crystal convexities on the surface, scratches, and scratches on the substrate 10, etc.
Deposition mask 13 onto substrate 1o.
密着性もまだ不十分で、上記従来方式と同様にパターン
の微細化、高精度の点で問題が生ずる。The adhesion is still insufficient, and similar to the conventional method described above, problems arise in terms of pattern miniaturization and high precision.
本発明の目的は、ファインパターン化が可能な薄膜パタ
ーンを形成し、かつ、該パターンが厚膜パターンとの接
続を良好にした厚膜薄膜混成集積回路用基板を提供する
ことにある。An object of the present invention is to provide a substrate for a thick-thin-film hybrid integrated circuit in which a thin film pattern that can be formed into a fine pattern is formed and the pattern has good connection with the thick film pattern.
本発明による厚膜薄膜混成集積回路用基板は。 A thick film thin film hybrid integrated circuit substrate according to the present invention is a substrate for a thick film thin film hybrid integrated circuit.
互いに対向する２つの主面を有する基板と、前記２つの
主面のうち、一方の主面上に形成された厚膜パターンと
、前記２つの主面の他方の主面上に形成され、前記厚膜
パターンと電気的に接続された薄膜パターンとを備え、
前記他方の主面は研磨されていることを特徴とする。a substrate having two main surfaces facing each other; a thick film pattern formed on one of the two main surfaces; a thick film pattern formed on the other of the two main surfaces; comprising a thick film pattern and an electrically connected thin film pattern,
The other main surface is polished.
以下１図面を参照して本発明の実施例について説明する
。Embodiments of the present invention will be described below with reference to one drawing.
先ず、第３図を参照して９本発明による厚膜薄膜混成集
積回路用基板の製造工程の一例を説明する。First, with reference to FIG. 3, an example of the manufacturing process of a thick-film-thin-film hybrid integrated circuit substrate according to the present invention will be described.
第３図（、）を参照すると、アルミナ基板１０の一方の
面に厚膜方式（スクリーン印刷法）で厚膜配線電極１１
及び厚膜素子（抵抗、コンデンサ等）１２かもなる厚膜
パターンが形成され、スルーホールに充填された内部配
線導体１４がその一端が厚膜配線電極１１と接続されて
アルミナ基板１０の内部を通シ、他方の面まで延在して
いる。この他方の面には、内部配線導体１４の盛上ｐ１
４ａができる。ここで、厚膜配線電極１１及び内部配線
導体１４は、Ｗ（タングステン）またはＡｇ／Ｐｄ（銀
／パラジウム）などの金属からなる。Referring to FIG. 3(,), a thick film wiring electrode 11 is formed on one side of the alumina substrate 10 by a thick film method (screen printing method).
A thick film pattern consisting of a thick film element (resistor, capacitor, etc.) 12 is formed, and an internal wiring conductor 14 filled in a through hole is connected to the thick film wiring electrode 11 at one end and passes through the inside of the alumina substrate 10. It extends to the other side. On this other surface, a ridge p1 of the internal wiring conductor 14 is provided.
4a can be done. Here, the thick film wiring electrode 11 and the internal wiring conductor 14 are made of metal such as W (tungsten) or Ag/Pd (silver/palladium).
第３図（ｂ）を参照すると、アルミナ基板１０の厚膜パ
ターンの形成されていない側の面、即ち内部配線導体１
４の盛上ｊｐ１４ａのある面の表面を研磨によシ平坦に
する。この研磨により９表面粗さは、平均値で０．７μ
ｍＲａ〜０．１８μｍＲａ程度に改善された。この研磨
の一例として、形成されるべき薄膜パターンが比較的粗
くて良い場合には、 ＋ａＯＯ砥粒で１０〜２０分間研
磨し、パターンの精度が要求される場合には、２μダイ
ヤモンド砥粒で鏡面研磨する。なお、研磨するときは。Referring to FIG. 3(b), the surface of the alumina substrate 10 on which the thick film pattern is not formed, that is, the internal wiring conductor 1
The surface of the surface of the raised jp14a of No. 4 is made flat by polishing. As a result of this polishing, the surface roughness of 9 is 0.7μ on average.
It was improved to about mRa to 0.18 μmRa. As an example of this polishing, if the thin film pattern to be formed is relatively rough, it can be polished for 10 to 20 minutes with +aOO abrasive grains, and if pattern precision is required, it can be polished to a mirror-like surface with 2μ diamond abrasive grains. Grind. In addition, when polishing.
前記アルミナ基板１０の厚膜パターンの形成されていな
い側の面を研磨面に当接し、その反対側に形成された厚
膜パターンを保護するために。The surface of the alumina substrate 10 on which the thick film pattern is not formed is brought into contact with the polishing surface to protect the thick film pattern formed on the opposite side.
ビニールシートやポリエステルフィルムなどでカバーし
研磨する。Cover with vinyl sheet or polyester film and polish.
第３図（Ｃ）を参照すると、研磨された面に蒸着マスク
１３を密着して、第３図（ｄ）に示されるような薄膜配
線電極１６を含む薄膜パターンを形成する。Referring to FIG. 3(C), a vapor deposition mask 13 is closely attached to the polished surface to form a thin film pattern including a thin film wiring electrode 16 as shown in FIG. 3(d).
このような製造工程によシ１例えば第４図に示されるよ
うな、厚膜薄膜混成集積回路用基板が作られる。図にお
いて、１７は薄膜素子で、抵抗やコンデンサ等からなる
。Through such a manufacturing process, a substrate for a thick-film/thin-film hybrid integrated circuit as shown in FIG. 4, for example, is manufactured. In the figure, numeral 17 is a thin film element consisting of a resistor, a capacitor, etc.
又１本発明に係る厚膜薄膜混成集積回路用基板は、第５
図に示されるような、多層積層基板を使用しても応用で
きる。図において、 １０＝’ｌ。Further, the thick-film-thin-film hybrid integrated circuit substrate according to the present invention is provided in the fifth embodiment.
The present invention can also be applied using a multilayer laminated substrate as shown in the figure. In the figure, 10='l.
１０−２ 、１０−３はアルミナ基板、 １１−１．１
１−２゜１１−３は厚膜配線電極、 １４−１．１４−
２．１４−３はスルーホールに充填された内部配線導体
、１６は薄膜配線電極、１７は薄膜素子を示している。10-2 and 10-3 are alumina substrates, 11-1.1
1-2゜11-3 is a thick film wiring electrode, 14-1.14-
2. 14-3 indicates an internal wiring conductor filled in a through hole, 16 a thin film wiring electrode, and 17 a thin film element.
更に９本発明に係る厚膜薄膜混成集積回路用基板は１例
えば、第６図に示されるような、半導体用パッケージ（
Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ ） としても応用でき
る。図において、 １０−’１．１０−２はアルミナ基
板、 １１−１．１１−２は厚膜配線電極、１４−１゜
１４−２はスルーホールに充填された内部配線導体、１
６は薄膜配線電極、１８はロウ材、１９はピン端子であ
る。なお、第５図及び第６図において。Furthermore, the thick-film-thin-film hybrid integrated circuit substrate according to the present invention can be used in a semiconductor package (for example, as shown in FIG. 6).
It can also be applied as a Pin Grid Array. In the figure, 10-'1.10-2 is an alumina substrate, 11-1.11-2 is a thick film wiring electrode, 14-1°14-2 is an internal wiring conductor filled in a through hole, 1
6 is a thin film wiring electrode, 18 is a brazing material, and 19 is a pin terminal. In addition, in FIGS. 5 and 6.
アルミナ基板１０−１．１０−２．１０−３．厚膜配線
電極１１−１．１１−２．１１−３及び内部配線導体１
４−１゜１４−２ 、１４−３は、同時焼成によシ作ら
れる。Alumina substrate 10-1.10-2.10-3. Thick film wiring electrode 11-1.11-2.11-3 and internal wiring conductor 1
4-1°14-2 and 14-3 are made by simultaneous firing.
以上の説明で明ら力・なように２本発明では。 As is clear from the above description, there are two aspects of the present invention.
厚膜パターンの形成された面と反対側の基板面を、研磨
することによシ平坦面とし、スルーホールに充填された
内部配線導体の盛上シが取除かれるので蒸着マスクの開
孔部を狭くすることができ仝。したがって高密度の薄膜
パターンを形成できる効果がある。又、同時に、内部配
線導体の盛り上り部が研磨されるとき、基板の材研磨に
よシ、基板表面に付着している異物が除去されて蒸着マ
スクの基板との密着性が増すので薄膜パターンの精度が
一段と向上する。又。The surface of the substrate opposite to the surface on which the thick film pattern is formed is polished to make it a flat surface, and the raised area of the internal wiring conductor filled in the through hole is removed, making the opening of the vapor deposition mask You can make it narrower. Therefore, there is an effect that a high-density thin film pattern can be formed. At the same time, when the raised portion of the internal wiring conductor is polished, the polishing of the substrate material removes foreign matter adhering to the substrate surface and increases the adhesion of the vapor deposition mask to the substrate, resulting in a thin film pattern. The accuracy will be further improved. or.
基板表面の凹部やキズも除去されるので形成された薄膜
パターンの断線も防止できる。さらに。Since recesses and scratches on the substrate surface are also removed, disconnection of the formed thin film pattern can also be prevented. moreover.
焼成後の基板の凹凸９反りの多い多層積層基板の場合、
研磨によシ前記凹凸９反シを無くすことができるので、
蒸着マスクと基板との密着性が増し、ファインパターン
化が可能である。なお、フォトリングラフイー法によっ
ても、蒸着マスク法と同一効果が得られる。Irregularities of the substrate after firing 9 In the case of a multilayer laminated substrate with a lot of warpage,
Since the above-mentioned unevenness can be eliminated by polishing,
The adhesion between the vapor deposition mask and the substrate is increased, and fine patterning is possible. Note that the same effect as the vapor deposition mask method can also be obtained by the photophosphorography method.
第１図は従来の厚膜薄膜混成ノくターン形成方式の一例
を示した断面図、第２図は従来の厚膜薄膜混成パターン
形成方式の他の例を示した断面図、第６図は本発明によ
る厚膜薄膜混成集積回路用基板の製造工程の一例を示し
た断面図。
第４図乃至第６図はそれぞれ本発明に係る厚膜薄膜混成
集積回路用基板の応用例を示した断面図である。
１０、１０−１．、１０−２．１０−３・・・基板、
１１．１１−１゜１１−２．１１−３・・・厚膜配線電
極、１２・・・厚膜素子。
１３・・・蒸着マスク、 １４．１４−１．１４−２．
１４−３・・・スルーホールに充填された内部配線導体
、１５・・・端面メタライズ、１６・・・薄膜配線電極
、１７・・・薄膜素子、１８・・・ロウ材、１９・・・
ピン端子。FIG. 1 is a cross-sectional view showing an example of a conventional thick-thin film hybrid pattern forming method, FIG. 2 is a cross-sectional view showing another example of a conventional thick-thin film hybrid pattern forming method, and FIG. 1 is a cross-sectional view showing an example of the manufacturing process of a thick-film-thin-film hybrid integrated circuit substrate according to the present invention. 4 to 6 are cross-sectional views showing application examples of the thick-film-thin-film hybrid integrated circuit substrate according to the present invention. 10, 10-1. , 10-2.10-3... substrate,
11.11-1゜11-2.11-3... Thick film wiring electrode, 12... Thick film element. 13... Vapor deposition mask, 14.14-1.14-2.
14-3... Internal wiring conductor filled in through hole, 15... End face metallization, 16... Thin film wiring electrode, 17... Thin film element, 18... Brazing material, 19...
pin terminal.
Claims (1)
パターンと、前記２つの主面の他方の主面上に形成され
、前記厚膜パターンと電気的に接続された薄膜パターン
とを備え、前記他方の主面は研磨されていることを特徴
とする厚膜薄膜混成集積回路用基板。[Claims] 1. A substrate having two main surfaces facing each other. A thick film pattern formed on one of the two main surfaces, and a thin film pattern formed on the other of the two main surfaces and electrically connected to the thick film pattern. 1. A thick-film-thin-film hybrid integrated circuit substrate, characterized in that the other main surface is polished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59057456A JPS60201688A (en) | 1984-03-27 | 1984-03-27 | Substrate for thick film thin film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59057456A JPS60201688A (en) | 1984-03-27 | 1984-03-27 | Substrate for thick film thin film hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60201688A true JPS60201688A (en) | 1985-10-12 |
Family
ID=13056168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59057456A Pending JPS60201688A (en) | 1984-03-27 | 1984-03-27 | Substrate for thick film thin film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60201688A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6428948A (en) * | 1987-07-24 | 1989-01-31 | Taiyo Yuden Kk | Thin-film and thick-film hybrid circuit substrate and manufacture thereof |
| US4827328A (en) * | 1986-03-17 | 1989-05-02 | Fujitsu Limited | Hybrid IC device |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
| US5897724A (en) * | 1986-05-19 | 1999-04-27 | Nippondenso Co., Ltd. | Method of producing a hybrid integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586183A (en) * | 1978-12-22 | 1980-06-28 | Tokyo Shibaura Electric Co | Substrate |
| JPS5864093A (en) * | 1981-10-14 | 1983-04-16 | 日本電気株式会社 | Multilayer circuit board |
-
1984
- 1984-03-27 JP JP59057456A patent/JPS60201688A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586183A (en) * | 1978-12-22 | 1980-06-28 | Tokyo Shibaura Electric Co | Substrate |
| JPS5864093A (en) * | 1981-10-14 | 1983-04-16 | 日本電気株式会社 | Multilayer circuit board |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4827328A (en) * | 1986-03-17 | 1989-05-02 | Fujitsu Limited | Hybrid IC device |
| US5897724A (en) * | 1986-05-19 | 1999-04-27 | Nippondenso Co., Ltd. | Method of producing a hybrid integrated circuit |
| JPS6428948A (en) * | 1987-07-24 | 1989-01-31 | Taiyo Yuden Kk | Thin-film and thick-film hybrid circuit substrate and manufacture thereof |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
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