JPS60198856A - Manufacture of semiconductor memory element - Google Patents

Abstract

PURPOSE:To contrive reduction in element area by a method wherein the gate part of a controlling transistor is buried in a substrate without increasing the element area. CONSTITUTION:The part where an N type Si layer 2, a P type Si substrate 1 and a P type Si layer 5 are overlapped constitutes a capacitor to be used for accumulation of electricity. As this capacitor is increased in size in proportion to the area indicated by the product of the circumferential length of a pole-formed part and the height of the overlapped layers 2 and 5 and the sum of the cross-sectional area of the pole-formed part, a sufficient accumulation capacitance can be obtained by increasing the height of the overlapped layers 2 and 5 even when the area of the layer 2 is reduced. Also, a P type layer 3 constitutes the channel part of a controlling transistor (TR), and an N type Si layer 7 is used as a gate electrode and it is buried in an insulator 6 through the intermediary of a thin insulating layer in such a manner that the layer 7 will be overlapped on the P type layer 3 of the pole-formed region and the N type layers 2 and 4 located on both sides of the layer 3. The layers 2 and 4 correspond to the drain and source electrodes of the TR. If the standard of design is set at F, 2FX3F which is 6F in other words is obtained in the highest density state, thereby enabling to make the element area smaller in size, if the above-mentioned structure is used.

Description

【発明の詳細な説明】 （産業上の利用分野） に関する。[Detailed description of the invention] (Industrial application field) Regarding.

（従来技術とその問題点） 近来半導体記憶素子の高集積化、高密度化の傾向が盛ん
であシ、それに伴って素子の微細化が進められているが
、微細加工技術の進展はりソグラフィ技術等を始めとし
て多くの面で各種技術的困難に直面している。また、特
にダイナミック型ランダムアクセスメモリ（以下ＤＲＡ
Ｍと略記する）の代表的構造であるトランジスタを１つ
と蓄電用容量１つからなる１トランジスタメモリセルに
於ては、蓄電容量を小さくし得ないため、その微細化は
さらに難しい問題に直面しており、各種新技法が検討さ
れているものの、１９８２年１２月に米国ワシントンで
開催されたＩＥＤＭ（国際電子素子会議）論文予稿集８
０６ページから８０７ページにｒＡ　Ｃ０ＲＲＵＧＡＴ
ＥＤ　ＣＡＰＡＣＩＴＡＮＣＥＣＥＬＬ　（ＣＣＣ）Ｆ
ＯＲＭＥＧＡＢＩＴ　ＤＹＮＡＭＩＣＭＯ８ＭＢＭＯＲ
ＩＥＳＪと題してＨ，ＳＵＮＡＭＩ等によシ発表された
論文においては、蓄電用容量の−少をはかると共に約１
ミクロン程度の設計基準を採用して従来のダイナミック
型ＭＯ８半導体記憶素子より素子面積を大幅に減少して
いるものの、その素子面積は、周辺の分離領域を含めて
約２１平方ミクロン程度であシ、かシにこの構造を用い
て４百万素子の記憶回路を作成しようとすると記憶素子
部分だけで８４平方ミリ程度と、かなシ大面積になって
しまう。(Prior art and its problems) In recent years, there has been a growing trend toward higher integration and higher density of semiconductor memory elements, and the miniaturization of elements is progressing accordingly. We are facing various technical difficulties in many aspects, including the following. In particular, dynamic random access memory (hereinafter referred to as DRA)
In the case of a one-transistor memory cell consisting of one transistor and one storage capacitor, which is a typical structure of the 1-transistor memory cell (abbreviated as M), the storage capacity cannot be made small, so miniaturization faces an even more difficult problem. Although various new techniques are being considered, the Proceedings of the IEDM (International Electronic Devices Conference) held in Washington, USA in December 1982.
rA C0RRUGAT from page 06 to page 807
ED CAPACITANCECELL (CCC)F
ORMEGABIT DYNAMICMO8MBMOR
In a paper published by H. SUNAMI et al. entitled IESJ, the power storage capacity was reduced to about 1
Although the device area is significantly reduced compared to the conventional dynamic MO8 semiconductor memory element by adopting a design standard on the order of microns, the device area is approximately 21 square microns including the peripheral isolation region. If one were to create a memory circuit with 4 million elements using this structure, the area for the memory elements alone would be approximately 84 square millimeters, which would be quite large.

（発明の目的） 本発明はこのような従来の欠点を除去せしめて、同−設
計基準で従来の素子よシ圧倒的に素子面積を減少させる
ことの可能な半導体記憶素子構造並びにその製造方法を
提供することにある。(Objective of the Invention) The present invention provides a semiconductor memory element structure and a manufacturing method thereof that can eliminate such conventional drawbacks and reduce the element area overwhelmingly compared to the conventional element based on the same design standard. It is about providing.

（発明の構成） 本発明によれば第１導電型シリコン単結晶基板の表面に
、少なくとも第２導電型の第１の単結晶シリコン層、そ
の上に存在する第１導電型の第１の単結晶シリコン層、
更にその上に存在する第２導電型の第２の単結晶シリコ
ン層で構成された柱状の構造を有し、該柱状結晶領域の
表面の内少くとも第２導電型の第１の単結晶層の表面の
少くとも一部分領域が絶縁物でおおわれているか又は全
くおおわれていない状態であシ、更にその柱状構造の周
辺部が基板単結晶と電気的に接続された第１導電型単結
晶ないしは多結晶シリコンないしは金属ないしはそれら
のくみあわせて第２導電型のび第２の第２導電型シリコ
ン層の各々の一部分をも含む領域の表面の少くとも１部
分に薄い絶縁膜が形成され、この絶縁膜上に導体膜が形
成されておシ、その他の部分は絶縁物で取シかこまれて
いることを特徴とする半導体記憶素子が得られる。(Structure of the Invention) According to the present invention, on the surface of the first conductivity type silicon single crystal substrate, at least the first single crystal silicon layer of the second conductivity type and the first single crystal silicon layer of the first conductivity type existing thereon are formed. crystalline silicon layer,
It further has a columnar structure composed of a second single crystal silicon layer of a second conductivity type existing thereon, and at least a first single crystal layer of the second conductivity type on the surface of the columnar crystal region. At least a partial region of the surface of the substrate is covered with an insulating material or not covered at all, and furthermore, the peripheral part of the columnar structure is a first conductivity type single crystal or a polycrystalline material which is electrically connected to the substrate single crystal. A thin insulating film is formed on at least a portion of the surface of a region of crystalline silicon, metal, or a combination thereof that extends to a second conductivity type and includes a portion of each of the second second conductivity type silicon layers, and this insulating film A semiconductor memory element is obtained, which is characterized in that a conductive film is formed on top of the semiconductor memory element, and other parts are surrounded by an insulating material.

更に本発明によれば、第１導電型シリコン基板の表面に
少くとも第２導電型の第１の単結晶シリコン層、その上
に存在する第１導電型の第１の単結晶シリコン層、更に
その上に存在する第２導電型の第２の単結晶シリコン層
で構成された柱状の構造を有し、該柱状結晶領域の表面
の内少くとも第ｉ導電型の第１の単結晶層の表面の少く
とも１部分領域が絶縁物でおおわれているか、又は全く
おおわれていない状態であシ、更にその柱状構造の周辺
部が基板単結晶と電気的に接続された第１導電型単結晶
ないし多結晶シリコンないし金属ないしそれらのくみあ
わせて第２導電型の第１のシリコン層の途中迄環まって
おジ、しかも第１導電型の第１のシリコン層およびそれ
に接する第２導電型の第１のシリコン層の一部分を含む
領域以上の部分において柱状構造の側壁の少なくとも一
部分が、下部の柱状構造の側壁よシ内側に退いており、
その退いた側壁を含む領域で、かつ第１導電型の第１の
シリコン層およびそれに接する第１及び第２の第２導電
型シリコン層の各々の１部分をも含む領域に薄い絶縁膜
が形成され、この絶縁膜上に導体膜が形成されておシ、
かつ、退いていな部分は絶縁物で取ルかこまれているこ
とを特徴とする半導体記憶素子が得られる。Further, according to the present invention, at least a first single crystal silicon layer of the second conductivity type is formed on the surface of the first conductivity type silicon substrate, a first single crystal silicon layer of the first conductivity type existing thereon, and further It has a columnar structure composed of a second single crystal silicon layer of a second conductivity type existing thereon, and at least a portion of the first single crystal layer of an i-th conductivity type within the surface of the columnar crystal region. At least a partial region of the surface is covered with an insulator or not covered at all, and the peripheral part of the columnar structure is electrically connected to the substrate single crystal. Polycrystalline silicon, a metal, or a combination of these forms a circle around the first silicon layer of the second conductivity type, and furthermore, the first silicon layer of the first conductivity type and the second silicon layer of the second conductivity type in contact with the first silicon layer of the first conductivity type. At least a portion of the sidewall of the columnar structure is recessed inwardly from the sidewall of the lower columnar structure in a region larger than or equal to a region including a portion of the silicon layer 1;
A thin insulating film is formed in a region including the receded sidewall and also including a portion of the first silicon layer of the first conductivity type and a portion of each of the first and second silicon layers of the second conductivity type in contact with the first silicon layer. A conductive film is formed on this insulating film.
In addition, a semiconductor memory element is obtained in which the recessed portion is surrounded by an insulating material.

！　Ｉ／ｒ＋　ｆｉ　００　Ｉｆ　）　Ｊ、ｌ　ｔＪｌ
■第１導電型単結晶シリコン基板上に第２導電型、第１
導電型単結晶シリコン層が形成されたものに対して所望
の領域を柱状に残して基板に届く迄シリコン層を除去し
、 ＠露出されたシリコン面を絶縁膜でおおい、Ｏ前記基板
から柱状化した第２導電型領域にかけての領域の絶縁膜
の少くとも一部分を除去し、Ｏ柱状部の第２導電型領域
の途中迄、凹部に第１導電型の単結晶もしくは多結晶シ
リコンもしくは金属もしくはそれらのくみあわせを埋込
み、■残された凹部を絶縁物で埋め込み、 ０表面から第２導電型層の一部までの柱状領域でかつこ
の領域に接する部分の絶縁物を少なくとも除去し、 ■露出シリコン表面に薄い絶縁膜を形成し、■堀込まれ
た部分に柱状構造の頂点以下の高さになるように導体を
埋込み、 ■柱状槽構造第１導電型領域頂点部全面に第２導電型不
純物を導入し第２導電型領域を、前記導＆ｎＴｌ１占？
ｈｉＬａ！／　−Ａ、つ”Ｔ　Ｉｇ　ａｚ　ｋｌｒ　Ｑ
道蕾荊首繍に届かないように作成する、 ことを特徴とする半導体記憶素子の製造方法が得られる
。! I/r+ fi 00 If ) J, l tJl
■The second conductivity type and the first conductivity type are placed on the first conductivity type single crystal silicon substrate.
On the conductive single crystal silicon layer formed thereon, the silicon layer is removed until it reaches the substrate, leaving a desired region in the form of a column, and the exposed silicon surface is covered with an insulating film. At least a part of the insulating film in the region extending to the second conductivity type region is removed, and the first conductivity type single crystal or polycrystalline silicon or metal or the like is injected into the concave part up to the middle of the second conductivity type region of the O columnar part. ■Fill the remaining recesses with an insulator, remove at least the insulator in the columnar region from the 0 surface to a part of the second conductivity type layer and in contact with this region, and ■remove the exposed silicon. A thin insulating film is formed on the surface, ■ a conductor is embedded in the dug part to a height below the top of the columnar structure, and ■ a second conductivity type impurity is applied to the entire top of the first conductivity type region of the columnar tank structure. A second conductivity type region is introduced into the conductive &nTl1?
hiLa! / -A,tsu”T Ig az klr Q
A method for manufacturing a semiconductor memory element is obtained, which is characterized in that the semiconductor memory element is manufactured so as not to reach the road bud neck embroidery.

更に本発明によれば、 ■第１導電型単結晶シリコン基板上に第２導電聾、第１
導電型単結晶シリコン層が形成されたものに対して所望
の領域を柱状に残して基板に届く迄シリコン層を除去し
、 ＠霧出されたシリコン面を絶縁膜でおおい、θ前記基板
から柱状化した第２導電型領域にかけての領域の絶縁膜
の少くとも１部分を除去し、Ｏ柱状部の第２導電型領域
の途中迄、凹部に第１導電型の単結晶もしくは多結晶シ
リコンもしくは金属もしくはそれらのくみあわせを埋込
み、■少くとも第１導電型シリコン層の表面に第１導電
型不純物を導入し、 θ残された凹部を絶縁物で埋め込み、 ■柱状部分の１部分を含みこれに接する絶縁物領域の１
部分をも含む領域を第２導電型層に届く迄の深さに除去
し、 ■露出シリコン表面に薄い絶縁膜を形成し、■埋込まれ
た部分に柱状構造の頂点以下の高さになるように導体を
埋込み、 ■柱状槽構造第１導電型領域頂点部に第２導電型不純物
を導入し、第２導電型領域を、前記導体の頂点よシも深
くかつ下層の第２導電型領域に届かないように作成する
。Furthermore, according to the present invention, (1) a second conductive deaf, a first conductive
From the conductive single crystal silicon layer formed thereon, the silicon layer is removed until it reaches the substrate, leaving a desired region in the form of a column, and the atomized silicon surface is covered with an insulating film. At least a portion of the insulating film in the area extending into the second conductivity type region is removed, and single crystal or polycrystalline silicon or metal of the first conductivity type is injected into the concave part up to the middle of the second conductivity type region of the O columnar part. Or by embedding a combination of these, ■ introducing impurities of the first conductivity type into at least the surface of the silicon layer of the first conductivity type, filling the recesses left by θ with an insulating material, and ■ including a part of the columnar part. 1 of the contacting insulator area
1. Remove the region including the 2nd conductivity type layer to a depth that reaches the second conductivity type layer, 1. Form a thin insulating film on the exposed silicon surface, and . . . 1) Introduce a second conductivity type impurity into the apex of the first conductivity type region of the columnar tank structure, and form the second conductivity type region deeper than the apex of the conductor and in the lower layer. Create it so that it does not reach.

ことを特徴とする半導体記憶素子の製造方法が得られる
。A method for manufacturing a semiconductor memory element is obtained.

（従来技術との相違点） 本発明の従来技術に対する改革的な点は、■在来技術で
の各素子周辺の分離領域及び蓄電容量領域を、新規な構
造を採用することによシ、合体化していること。(Differences from the prior art) The innovative points of the present invention over the prior art are: ① By adopting a new structure, the isolation region and capacitor region around each element in the conventional technology are combined. that it has become

■上記合体領域の上部面を有効利用することによシ、在
来技術では別途面積を必要とした制御用トランジスタの
ゲート部分を、素子面積を増すことなく基板内に埋め込
んだこと。(2) By effectively utilizing the upper surface of the above-mentioned merging region, the gate portion of the control transistor, which required a separate area in conventional technology, is embedded in the substrate without increasing the device area.

■ゲート部分を埋め込んだことによル在来技術では別途
面積を必要としていた、制御トランジスタの入力部分を
、ゲートとの分離領域を不必要とすることをも含めて蓄
電容量領域の上に設けることによシ余分な面積を不必要
にしたこと。■By embedding the gate part, the input part of the control transistor, which required an additional area in conventional technology, is placed above the capacitor area, including eliminating the need for a separate area from the gate. In particular, it made the extra area unnecessary.

■上記構造を実現する製造方法を実現したこと。■A manufacturing method that realizes the above structure has been realized.

等である。etc.

（実施例） 以下本発明の実施例について図面を参照して詳細に説明
する。(Example) Examples of the present invention will be described in detail below with reference to the drawings.

第１図は本発明の実施例の１つを示す平面図で、図中破
線で囲まれた領域が１つの半導体記憶素子の占める部分
である。まえ図中の線分Ａ＋＋Ｂ　。FIG. 1 is a plan view showing one embodiment of the present invention, and the area surrounded by broken lines in the figure is the portion occupied by one semiconductor memory element. Line segment A++B in the previous figure.

Ｃ→Ｄ　、　Ｅ、、Ｆ　、　Ｇ→Ｈにそっての断面図を
各々第２図、第３図、第４図、第５図に示している。Cross-sectional views along C→D, E, , F, and G→H are shown in FIGS. 2, 3, 4, and 5, respectively.

第１図から第５図迄図中の同じ符号は全て同じものを表
わしておシ、１はｐ型シリコン単結晶基板、２は柱状の
ｎ型単結晶シリコン層、３は柱状ｐ型巣結晶シリコン層
、４は柱状ｎ型単結晶シリコン層、５は埋め込まれたｐ
型シリコン、６は埋込まれた絶縁物、７は柱状領域のｐ
型層３及びその両部のｈ剤層９　Ａの一部を寸〒舌鳴ス
Ｆ＾ｆ薄い絶縁層２０を介して埋込まれたｎ型シリコン
層、８は絶縁層、９は配線用金属、１１．１２，１３゜
１４、はｐ型シリコン５を埋込む前に作製され、次に一
部を除去した絶縁物層のいろいろな残シ方をしたもので
ある。実際には隣ｂｓったメモリセル間でこれほど極端
に残シ方が異なることはなく、少なくとも１つのチップ
内では残り方はほぼ同じである。The same symbols in the figures from FIG. 1 to FIG. 5 all represent the same thing. 1 is a p-type silicon single crystal substrate, 2 is a columnar n-type single crystal silicon layer, and 3 is a columnar p-type nest crystal. silicon layer, 4 is a columnar n-type single crystal silicon layer, 5 is a buried p
type silicon, 6 is the buried insulator, 7 is the p of the columnar region.
A part of the mold layer 3 and the h-agent layer 9 A on both sides is an n-type silicon layer embedded through a thin insulating layer 20, 8 is an insulating layer, and 9 is for wiring. The metals 11, 12, 13, and 14 are fabricated before implanting the p-type silicon 5, and are then partially removed to leave various residues of the insulator layer. In reality, adjacent memory cells do not have such extreme differences in their remaining positions, and within at least one chip, their remaining positions are almost the same.

第１図から第５図よシ明らかなように本発明では、ｎ型
シリコ７層２とｐ型シリコン基板１及びｐ型シリコン層
５の重なシ合った部分が蓄電用容量となり−Ｆ）特に基
板１とｎ型層２０間では接合型、基板１とｐ型シリコン
層５の重なシの場合は、１１〜１４を介した場合はＭＩ
Ｓ型の容量、１１〜１４を介しない場所では接合型の容
量となっている。この容量は柱状部分の周辺長と、ｎ型
層２とｐ型層５の重なシ合う高さの積で表わされる面積
と柱状部分の断面積の和の大きさに従って増大するため
、ｎ型層２の断面積を小さくしても、ｎ型層２とｐ型層
５０重々力合う高さを大きくするととによシ充分な蓄電
容量が得られる利点がある。As is clear from FIGS. 1 to 5, in the present invention, the overlapping portions of the n-type silicon 7 layer 2, the p-type silicon substrate 1, and the p-type silicon layer 5 serve as a storage capacity -F) In particular, in the case of a junction type between the substrate 1 and the n-type layer 20, and in the case of an overlapping layer between the substrate 1 and the p-type silicon layer 5, the MI
The capacitor is an S-type capacitor, and a junction-type capacitor is provided at a location not passing through the capacitors 11 to 14. This capacitance increases according to the sum of the cross-sectional area of the columnar portion and the area represented by the product of the circumferential length of the columnar portion and the overlapping heights of the n-type layer 2 and p-type layer 5, so the n-type Even if the cross-sectional area of the layer 2 is made smaller, there is an advantage that a more sufficient storage capacity can be obtained by increasing the height at which the n-type layer 2 and the p-type layer 50 meet.

また図中ｐ型層３０部分は制御トランジスタのチャンネ
ル部を構成し、７は制御用のゲート電極であシ薄い絶縁
膜２０はゲート絶縁膜である。ｎ型層４と２はトランジ
スタのソース、ドレイン電極に相当し、ｎ型層４に金属
配線９を接続することによシ、７と９はダイナミック型
メモリのワード線及びビット線に対応することになシ、
図から明らかなように、本構造を用いれば、設計基準を
Ｆとすると、最も高密度化した場合には、２ＦＸ３Ｆ、
即ち６Ｆ”に迄小さくすることが可能である。Further, in the figure, a p-type layer 30 portion constitutes a channel portion of a control transistor, 7 is a gate electrode for control, and a thin insulating film 20 is a gate insulating film. The n-type layers 4 and 2 correspond to the source and drain electrodes of the transistor, and by connecting the metal wiring 9 to the n-type layer 4, 7 and 9 correspond to the word line and bit line of the dynamic memory. Nashi,
As is clear from the figure, if this structure is used, and the design standard is F, at the highest density, 2FX3F,
In other words, it is possible to reduce the size to 6F''.

但し、製造性、信頼性其の他の理由で６Ｆ”以上の面積
にしても本構造を基本的に変えない限り、本発明の有効
性が失なわれるわけではない。However, even if the area is increased to 6F'' or more for manufacturability, reliability, or other reasons, the effectiveness of the present invention will not be lost as long as the structure is not fundamentally changed.

このような変型の一例を第６図から第１０図までに示し
である。此処で図面の表わし方及び記号は、第１図から
第５図までと等価である。この変型に於ては先に述べた
説明に比べて、ゲート電極７が、柱状チャンネル部３の
周辺を完全におおっている点であシ、このため、制御ト
ランジスタのチャンネル幅が大きくなっているため、記
憶素子の動作速度が大きくなると共に、更には、ゲート
電極に薄い絶縁膜を介して接していない、ｐ型層３０表
面をリーク電流が流れる可能性を防ぐと云う利点がある
半導体記憶素子が得られる。An example of such a modification is shown in FIGS. 6 to 10. The drawing representations and symbols used here are equivalent to those in FIGS. 1 to 5. In this modification, compared to the above explanation, the gate electrode 7 completely covers the periphery of the columnar channel portion 3, and therefore the channel width of the control transistor is increased. Therefore, the operating speed of the memory element is increased, and the semiconductor memory element also has the advantage of preventing the possibility of leakage current flowing through the surface of the p-type layer 30 that is not in contact with the gate electrode through a thin insulating film. is obtained.

第１１図から第１６図は、第２の発明に関して示したも
のであシ、本発明の基本的な原理は第１の発明のそれと
同様であるが本発明では第１２図に明らかな通［ｎ型シ
リコ７層２の下部が上部に比べて大きくなっているため
、周辺のｐ型シリコン層５との接触面積が同−設計基準
では第１の発明に比して大きくなっている利点があると
共に、ゲート電極７と対向しないｐ型シナコン層３の表
面の不純物濃度がゲート電極７に対向する部分のそれよ
シ高くなりているため、制御トランジスタのリーク特性
が改善されていると云う利点をも有している。11 to 16 are shown in relation to the second invention, and the basic principle of the present invention is the same as that of the first invention, but in the present invention, as shown in FIG. Since the lower part of the n-type silicon 7 layer 2 is larger than the upper part, the contact area with the surrounding p-type silicon layer 5 is larger than the first invention based on the same design standard. In addition, since the impurity concentration on the surface of the p-type Cinnacon layer 3 that does not face the gate electrode 7 is higher than that on the part that faces the gate electrode 7, the leakage characteristics of the control transistor are improved. It also has

以下本実施例の具体例を本発明の製造方法の説明と共に
示す。A specific example of this example will be shown below along with a description of the manufacturing method of the present invention.

先ず第１の発明の実現方法について記述する。First, a method for realizing the first invention will be described.

初めに用いた単結晶シリコン基板は、ホウ素を含む（約
ｌＸｌ０”原子／ｄ）ｐ型巣結晶基板上に砒素を約２Ｘ
１０”原子／−程度含む口型シリコン層を厚さ約５ｐｍ
　、更にその上にホウ素を約１０１ｓ原子／−程度含む
ｐ型シリコン層を厚さ約１．５μｍ程度備えたエピタキ
シャル基板であシ、その表面を熱酸化し厚さ約２０ｎｍ
の二酸化シリコン膜を作シ、その上に約１１００ｎの窒
化シリコン膜更にその上に厚さ５００ｎｍの二酸化シリ
コン膜を堆積し、横方向４．５μｍピッチ、縦方向３ｐ
ｍピッチは配置された５ｐｍ角の柱状領域となる部分に
のみ残して、除去し、レジストを残したまま、リアクテ
ィブイオンエツチング（ＲＩＥと略す）で柱状以外の部
分のシリコンを８μｍの深さにエツチングした。次に、
レジストを除去し、全体を熱酸化し厚さ１０ｎｍ程度の
熱酸化膜を成長し、減圧ＣＶＤ法で窒化シリコン層を全
面に厚さ１０ｎｍ付着し、更にＲＩＥを行い柱状頂点の
絶縁膜の一部並びに溝底部の絶縁層全てを除去した。次
に選択エピタキシャル法を用いて底部シリコン面にホウ
素をｌＸｌ０”原子／−程度含むｐ型シリコン層を５．
５ｐｍ成長させ次に表面に現われている柱状側面の窒化
シリコン及び二酸化シリコン膜をウェットエツチングで
除去した。この時柱状部頂点の上部の二酸化シリコン層
はエッチされ頂部には二酸化シリコンと窒化シリコン膜
からなる二層構造が残った。次に、全体を熱酸化し、更
Ｋまわシ込みの良い減圧ＣＶＤ法で二酸化シリコンを残
った凹みに埋め込んだ。The single-crystal silicon substrate used initially was a p-type nested crystal substrate containing boron (approximately 1X10" atoms/d), and arsenic was added at approximately 2X.
A mouth-shaped silicon layer containing approximately 10" atoms/- is approximately 5 pm thick.
The epitaxial substrate was further provided with a p-type silicon layer containing about 101s atoms/- of boron to a thickness of about 1.5 μm, and its surface was thermally oxidized to a thickness of about 20 nm.
A silicon dioxide film of approximately 1,100 nm is deposited on top of the silicon nitride film, and a silicon dioxide film of 500 nm in thickness is deposited on top of this, with a pitch of 4.5 μm in the horizontal direction and 3p in the vertical direction.
The m pitch was removed leaving only the part that would become the 5 pm square columnar area, and with the resist remaining, the silicon in the non-columnar area was etched to a depth of 8 μm using reactive ion etching (RIE). Etched. next,
The resist is removed, the whole is thermally oxidized to grow a thermal oxide film with a thickness of about 10 nm, a silicon nitride layer is deposited with a thickness of 10 nm on the entire surface by low pressure CVD, and RIE is performed to partially remove the insulating film at the top of the column. In addition, the entire insulating layer at the bottom of the trench was removed. Next, using a selective epitaxial method, a p-type silicon layer containing about 1X10'' boron atoms/- is formed on the bottom silicon surface.
After growing to a thickness of 5 pm, the silicon nitride and silicon dioxide films on the columnar side surfaces appearing on the surface were removed by wet etching. At this time, the silicon dioxide layer above the apex of the columnar portion was etched, leaving a two-layer structure consisting of silicon dioxide and silicon nitride film on the top. Next, the entire structure was thermally oxidized, and silicon dioxide was filled into the remaining recesses by low-pressure CVD, which allows for better etchability.

その結果柱状部表面にも二酸化シリコンが厚く堆積し更
に表面に激しい凹凸が発生したので、表面に二酸化ケイ
素系の液を塗布し固化して、表面を平坦化し次に、素材
による選択性の少いイオンエッチを全面に行い、ＣＶＤ
二酸化シリコン膜の平坦面を得、次に二酸化シリコンの
選択性のあるエツチングを行い柱状シリコン表面迄二酸
化シリコンを除去した。次に横方向４．５ｐｍピッチに
配置された１、５μｍの帯状のマスクを用いてレジスト
工程を行い柱状部の端が約０．５μｍかかる程度に１．
５ｐｍ幅の帯状領域のレジストを除去し、その開口部を
利用して二酸化シリコンを深さ約２μｍ除去した。As a result, a thick layer of silicon dioxide was deposited on the surface of the columnar part, and severe unevenness occurred on the surface. Therefore, a silicon dioxide-based liquid was applied to the surface, solidified, and the surface was flattened. Perform ion etching on the entire surface and CVD
A flat surface of the silicon dioxide film was obtained, and then selective etching of silicon dioxide was performed to remove silicon dioxide up to the surface of the columnar silicon. Next, a resist process is performed using a band-shaped mask of 1.5 μm arranged at a pitch of 4.5 pm in the horizontal direction, and the ends of the columnar portions are coated with a mask of 1.5 μm so that the edges of the columnar portions are approximately 0.5 μm thick.
The resist in a band-shaped region with a width of 5 pm was removed, and the silicon dioxide was removed to a depth of about 2 μm using the opening.

次にレジストを除去して、熱酸化し露出された柱状シリ
コンの側面にゲート酸化膜となる厚さ２゜ｎｍの二酸化
シリコン膜を成長させ、続いてＣＶＤ法によｌンを５Ｘ
１０”原−７−／ｄ程度含む多結晶シリコンを堆積し、
凹部をうめた。この多結晶シリコンがゲート電極となる
。次に、再度二酸化シリコンを含む液の塗布を用いて全
面を平坦化し、選択性の無いイオンエツチングで、多結
晶シリコン面を平坦化し、液によるシリコンエッチを行
ない、柱状シリコン頂点からｏ、３ｐｍ程度下った所に
ゲートになる多結晶シリコン表面が来るようにした。Next, the resist was removed, and a 2-nm-thick silicon dioxide film was grown on the side surface of the exposed columnar silicon by thermal oxidation, and then a 2-nm-thick silicon dioxide film was grown to become a gate oxide film, and then a 5X irradiation process was performed using the CVD method.
Depositing polycrystalline silicon containing about 10" original -7-/d,
Filled the recess. This polycrystalline silicon becomes the gate electrode. Next, the entire surface is flattened by applying a liquid containing silicon dioxide again, the polycrystalline silicon surface is flattened by non-selective ion etching, and silicon etching is performed with a liquid to a depth of about 3 pm from the top of the columnar silicon. I made sure that the polycrystalline silicon surface that would become the gate was at the bottom.

次に全面に砒素を１０”／ｄ程度イオン注入し、熱酸化
条件で全面の酸化と同時に柱状シリコンの頂点部に注入
された砒素の活性化と拡散を行い、柱状シリコンの頂点
から約０．５μｍ程度の深さ迄をｎ型に変換し、柱状シ
リコン頂点に存在する窒化シリコンの層を除去して、更
に全面にＣＶＤで二酸化シリコンを堆積し、次に柱状シ
リコンの頂点の二酸化シリコンをレジスト工程を用いて
除去した。Next, ions of arsenic of about 10"/d are implanted into the entire surface, and the arsenic implanted into the apex of the columnar silicon is activated and diffused at the same time as oxidizing the entire surface under thermal oxidation conditions. Convert to a depth of about 5 μm to n-type, remove the silicon nitride layer present at the top of the columnar silicon, deposit silicon dioxide on the entire surface by CVD, and then apply the silicon dioxide at the top of the columnar silicon with a resist. removed using a process.

この場合ゲート多結晶シリコンのリン濃度が高いため、
その上の二酸化シリコンの膜厚は柱状シリコンの上部の
それよシ厚く、たとえ目合せ工程で開口部がずれても柱
状シリコンの頂点部にのみビット線用の開口部を作成す
ることが出来た。次に配線用アルミをまわシ込みの良い
バイアススパッタ法で全面に付着し、レジスト工程でビ
ット線を作成した。また多結晶シリコンからなるワード
線への配線は別途半導体記憶素子のアレーの外側で、レ
ジスト工程で別途上部二酸化シリコン層に開口しておき
ビット線用のアルミ付着工程を共用して行なった。また
、集積化メモリとして必要な周辺回路は、ｎチャンネル
デバイスを用いる場合は上層のｐ型層を用いて作成し、
０ＭＯ８構造の必要な場合は、ｎウェル部分は加工工程
の初めに上層ｐ層にリンを拡散し下のｎ層まで届かせる
ことで実現した。またこれ等の詳細な工程は通常のＭＯ
８加工技術であるので、此処では省略するが、本発明を
実施する製造過程の内共通なものは共用することで実現
した。In this case, since the phosphorus concentration of the gate polycrystalline silicon is high,
The thickness of the silicon dioxide film on top of it was thicker than that on the top of the columnar silicon, so even if the openings were misaligned during the alignment process, it was possible to create an opening for the bit line only at the top of the columnar silicon. . Next, wiring aluminum was deposited on the entire surface using a bias sputtering method with good coverage, and a bit line was created using a resist process. Further, wiring to the word line made of polycrystalline silicon was performed separately outside the array of semiconductor memory elements by separately opening an opening in the upper silicon dioxide layer using a resist process, and also using the aluminum deposition process for the bit line. In addition, when using an n-channel device, the peripheral circuitry required for an integrated memory is created using the upper p-type layer.
When an 0MO8 structure was required, the n-well part was realized by diffusing phosphorus into the upper p-layer at the beginning of the processing process and allowing it to reach the lower n-layer. In addition, these detailed processes are similar to those of normal MO
8 processing techniques, so they are omitted here, but the common manufacturing processes for carrying out the present invention were realized by sharing them.

次に第２の発明の実現方法を第４の発明の製造方法の説
明と共に示す。Next, a method for realizing the second invention will be described together with a description of a manufacturing method for the fourth invention.

初めに用いた単結晶シリコン基板は、ホウ素を含む（約
ｌＸｌ０”原子／ｃｒＩ）ｐ型巣結晶基板上に砒素を約
２Ｘ１０”原子／ｌｒｉ程度含むｎ型シリコン層を厚さ
約５ｐｍ、更にその上にホウ素を約１０１８原子／ｃｒ
／ｌ程度含むｐ型シリコン層を厚さ約１．５ｐｍ程度備
えたエピタキシャル基板であシ、その表面を熱酸化し厚
さ約２０ｎｍの二酸化シリコン膜を作シ、その上に約１
１００ｎの窒化シリコン膜更にその上に厚さ５００ｎｍ
の二酸化シリコン膜を堆積し、横方向４．５μｍピッチ
、縦方向３ｐｍピッチに配置された、／、５μｍＸ２．
２５／ｊｍの柱状領域となる部分にのみ残して、除去し
、レジストを残したまま、リアクティブイオンエツチン
グ（ＲＩＥと略す）で柱状以外の部分のシリコンを８μ
ｍの深さにエツチングした。次に、レジストを除去し、
全体を熱酸化し厚さ１０ｎｍ程度の熱酸化膜を成長し、
減圧ＣＶＤ法で窒化シリコン層を全面に厚さ１０ｎｍ付
着し、更にＲＩＥを行い柱状頂点の絶縁膜の一部並びに
溝底部の絶縁贋金てを除去した。次に選択エピタキシャ
ル法を用いて底部シリコン面にホウ素をｌＸｌ０”原子
／６Ｉ程度含むｐ型シリコン層を５．５μｍ成長させ次
に表面に現われている柱状側面の窒化シリコン及び二酸
化シリコン膜をウェットエツチングで除去した。この時
柱状部頂点の上部の二酸化シリコン層はエッチされ頂部
には二酸化シリコンと窒化シリコン膜からなる二層構造
が残った。次に、全体をｐ型不純物としてホウ素を含む
８００℃程度のガス内に短時間さらし次に全体を熱酸化
して上部ｐ型シリコン層の表面濃度を３Ｘ１０”原子／
−程度にした。此処で表面不純物濃度よシ充分低いこと
が必要である。The single-crystal silicon substrate used at the beginning was a p-type nested crystal substrate containing boron (approximately 1X10" atoms/crI), and an n-type silicon layer containing approximately 2X10" atoms/lri of arsenic with a thickness of approximately 5 pm. About 1018 atoms/cr of boron on top
An epitaxial substrate was prepared with a p-type silicon layer having a thickness of about 1.5 pm, and the surface was thermally oxidized to form a silicon dioxide film with a thickness of about 20 nm.
100n silicon nitride film with a thickness of 500nm on top
A silicon dioxide film was deposited and arranged at a pitch of 4.5 μm in the horizontal direction and a pitch of 3 pm in the vertical direction.
25/jm is left only in the part that will become the columnar area and removed, and with the resist remaining, the silicon in the part other than the columnar area is etched by 8μ by reactive ion etching (abbreviated as RIE).
It was etched to a depth of m. Next, remove the resist and
The whole is thermally oxidized to grow a thermal oxide film with a thickness of about 10 nm.
A silicon nitride layer was deposited to a thickness of 10 nm over the entire surface by low pressure CVD, and RIE was further performed to remove a portion of the insulating film at the columnar apex and the insulating metal at the bottom of the groove. Next, a p-type silicon layer containing about 1X10'' atoms/6I of boron is grown to a thickness of 5.5 μm on the bottom silicon surface using a selective epitaxial method, and then the silicon nitride and silicon dioxide films on the columnar side surfaces appearing on the surface are wet etched. At this time, the silicon dioxide layer above the apex of the columnar part was etched, leaving a two-layer structure consisting of silicon dioxide and silicon nitride film on the top.Next, the entire silicon dioxide layer was etched at 800°C containing boron as a p-type impurity. The surface concentration of the upper p-type silicon layer is reduced to 3×10” atoms/
- About. Here, it is necessary that the concentration of surface impurities be sufficiently lower.

次にまわ）込みの良い減圧ＣＶＤ法で二酸化シリコンを
残った凹みに埋め込んだ。その結果柱状部表面にも二酸
化シリコンが厚く堆積し更に表面に激しい凹凸が発生し
たので、表面に二酸化ケイ素系の液を塗布し固化して、
表面を平坦化し次に、素材による選択性の少いイオンエ
ッチを全面に行い、ＣＶＤ二酸化シリコン膜の平坦面を
得、次に二酸化シリコンの選択性のあるエツチングを行
い柱状シリコン表面迄二酸化シリコンを除去した。Next, silicon dioxide was filled into the remaining recesses using a low-pressure CVD method with good coverage. As a result, silicon dioxide was deposited thickly on the surface of the columnar part, and the surface became extremely uneven, so a silicon dioxide-based liquid was applied to the surface and solidified.
The surface is flattened, and then ion etching with low selectivity depending on the material is performed on the entire surface to obtain a flat surface of the CVD silicon dioxide film. Next, silicon dioxide is etched with selectivity of silicon dioxide to the surface of the columnar silicon. Removed.

次に横方向４．５ｐｍピッチに配置された１、５μｍの
帯状のマスクを用いてレジスト工程を行い柱状部の端が
約０．７５μｍかかる程度に１．５μｍ幅の帯状領域の
レジストを除去し、その開口部を利用して二酸化シリコ
ン及び単結晶シリコンを深さ約２ｐｍ除去した。次にレ
ジストを除去して、熱酸化し露出された柱状シリコンの
面にゲート酸化膜となる厚さ２０ｎｍの二酸化シリコン
膜を成長させ、続いてＣＶＤ法によシリンを５Ｘ１０”
原子／　ｃｒｌ　程度含む多結晶シリコンを堆積し、凹
部をうめた。この多結晶シリコンがゲート電極となる。Next, a resist process was performed using a 1.5 μm strip mask arranged at a pitch of 4.5 pm in the horizontal direction, and the resist in a 1.5 μm wide strip area was removed so that the end of the columnar part was approximately 0.75 μm thick. Using the opening, silicon dioxide and single crystal silicon were removed to a depth of about 2 pm. Next, the resist was removed, a 20 nm thick silicon dioxide film was grown on the exposed columnar silicon surface by thermal oxidation, and then a 5x10" silicon dioxide film was deposited using the CVD method.
Polycrystalline silicon containing about 3 atoms/crl was deposited to fill the recess. This polycrystalline silicon becomes the gate electrode.

次に、再度二酸化シリコンを含む液の塗布を用いて全面
を平坦化し、選択性の無いイオンエツチングで多結晶シ
リコン面を平坦化し、エツチング液によるシリコンエッ
チを行ない、柱状シリコン頂点から０．３　Ｐ　Ｍ程度
下った所にゲートになる多結晶シリコン表面が来るよう
にした。次に全面に砒素を１０１ｓｄ程度イオン注入し
、熱酸化条件で全面の酸化と同時に柱状シリコンの頂点
部に注入された砒素の活性化と拡散を行い、柱状シリコ
ンの頂点から約０．５ｐｍ程度の深さ迄をｎ型に変換し
、柱状シリコン頂点に存在する窒化シリコンの層を除去
して更に全面にＣＶＤで二酸化シリコンを堆積し、次に
柱状シリコンの頂点の二酸化シリコンをレジスト工程を
用いて除去した。この場合ゲート多結晶シリコンのリン
濃度が高いため、その上の二酸化シリコンの膜厚は柱状
シリコンの上部のそれより厚く、たとえ目合せ工程で開
口部がずれても柱状シリコンの頂点部にのみビット線用
の開口部を作成することが出来た。次に配線用アルミを
まわシ込みの良いバイアススパッタ法で全面に付着し、
レジスト工程でビット線を作成した。また多結晶シリコ
ンからなるワード線への配線は別途半導体記憶素子のア
レーの外側で、レジスト工程で別途上部二酸化シリコン
層に開口しておきビット線用のアルミ付着工程を共用し
て行なった。また、集積化メモリとして必要な周辺回路
は、ｎチャンネルデバイスを用いる場合は上層のｐ型層
を用いて作成し、ＣＭＯ８構造の必要な場合は、ｈウェ
ル部分は加工工程の初めに上層ｐ層にリンを拡散し下の
ｎ層まで届かせることで実現した。またこれ等の詳細な
工程は通常のＭＯ３加工技術であるので、此処では省略
するが、本発明を実施する製造過程の内共通なものは共
用することで実現した。Next, the entire surface is planarized again by applying a liquid containing silicon dioxide, the polycrystalline silicon surface is flattened by non-selective ion etching, and silicon is etched using an etching liquid to remove 0.3 P from the top of the columnar silicon. The polycrystalline silicon surface that will become the gate is placed about M below. Next, approximately 101 sd of arsenic is ion-implanted into the entire surface, and at the same time as the entire surface is oxidized under thermal oxidation conditions, the arsenic implanted into the apex of the columnar silicon is activated and diffused. The silicon nitride layer present at the top of the columnar silicon is removed and silicon dioxide is deposited on the entire surface by CVD. Next, the silicon dioxide at the top of the columnar silicon is removed using a resist process. Removed. In this case, since the phosphorus concentration of the gate polycrystalline silicon is high, the thickness of the silicon dioxide film on it is thicker than that on the top of the columnar silicon, and even if the opening is misaligned during the alignment process, the bits will only appear at the top of the columnar silicon. I was able to create an opening for the line. Next, aluminum for wiring is applied to the entire surface using a bias sputtering method with good coverage.
Bit lines were created using a resist process. Further, wiring to the word line made of polycrystalline silicon was performed separately outside the array of semiconductor memory elements by separately opening an opening in the upper silicon dioxide layer using a resist process, and also using the aluminum deposition process for the bit line. In addition, the peripheral circuitry required for an integrated memory is created using the upper p-type layer when using an n-channel device, and when a CMO8 structure is required, the h-well portion is created using the upper p-type layer at the beginning of the processing process. This was achieved by diffusing phosphorus into the layer and allowing it to reach the n-layer below. Further, since these detailed steps are common MO3 processing techniques, they will be omitted here, but the common manufacturing steps for carrying out the present invention were realized by sharing them.

以上本発明を１つの実施例について説明したが、実施例
のｐ型とｎ型を入れ換えても同様の効果の得られること
は自明である。Although the present invention has been described above with reference to one embodiment, it is obvious that the same effect can be obtained even if the p-type and n-type of the embodiment are replaced.

また、ゲート電極７を作成するにあたって、７をタング
ステン、モリブデン等その後の熱処理に耐えられる金属
で作成しても良く、特にその場合は金屑のエツチング剤
がシリコン及び二酸化シリコン等のそれと異なるため成
型は簡単であると云う利点を持つ。但しこの場合は、ゲ
ート電極７を成型した後にＣＶＤ法、スパッタ法等によ
る二酸化シリコンは其の他の絶縁物の堆積が必要であり
さらに柱状シリコン上部開口時に注意を要することは云
うまでもないが、これ等の点は在来技術で解決し得るも
のである。Furthermore, when forming the gate electrode 7, the gate electrode 7 may be formed of a metal that can withstand subsequent heat treatment, such as tungsten or molybdenum. has the advantage of being simple. However, in this case, after forming the gate electrode 7, it is necessary to deposit other insulators on the silicon dioxide by CVD, sputtering, etc., and it goes without saying that care must be taken when opening the upper part of the columnar silicon. , these points can be solved using conventional technology.

また更にゲート電極７の材料にタングステンシリサイド
、チタンシリサイド、モリブデンシリサイド等の金属ケ
イ化物を用いることも可能であシ、その場合は、多結晶
シリコンを用いた場合とほぼ同様の加工方法で製作する
ことが出来る。Furthermore, it is also possible to use metal silicides such as tungsten silicide, titanium silicide, molybdenum silicide, etc. as the material of the gate electrode 7, and in that case, it is manufactured using almost the same processing method as when polycrystalline silicon is used. I can do it.

また、ゲート電極７を作成するにあたり、初めにまわシ
込みの良い減圧ＣＶＤ法等で周辺に薄く多結晶シリコン
を付着し、次にモリブデン等の金属を付着して埋め込み
を行いゲート電極として成型した後更にその上面に多結
晶シリコンの中につつみ込まれたような型状にすること
も可能でｓｂ、更にはこれに熱処理を行いゲート電極７
の中心部のみを金属ケイ化物に変換することも可能であ
る。In addition, to create the gate electrode 7, first a thin layer of polycrystalline silicon was deposited around the periphery using a low-pressure CVD method with good coverage, and then a metal such as molybdenum was deposited and buried to form the gate electrode. After that, it is also possible to form a shape that is embedded in polycrystalline silicon on the upper surface of the gate electrode sb, and then heat-treat this to form the gate electrode 7.
It is also possible to convert only the central part of the metal into a metal silicide.

実施例で述べた多結晶シリコンとここで述べた金属等と
をすべて含めて特許請求の範囲では導体と称している。In the claims, the polycrystalline silicon described in the embodiments and the metals described here are collectively referred to as conductors.

またこれらの実施例ではｐ型シリコン層５の部分を選択
エピタキシャル法で行う場合を述べたが実際には、この
部分のシリコンは単結晶でなくても良いことは自明であ
夛、また側壁の絶縁膜が１３又は１４のような状態の場
合には、ｐ型シリコン層５は、完全な単結晶にはならな
いが、本素すコン層５とｎ型シリコ７層２の間にはＭＩ
８でなく、整流性接合が出来るが、この場合も実際には
ｐ型不純物のホウ素が拡散係数が他のｎ型不純物のそれ
に比べて大きいため接合は柱状単結晶領域内に生成され
接合特性はそこなわれない。但しこの場合には、ｎ型層
２の部分が完全にｐＨ１に変換し々いよう熱処理温度並
びに時間を制御しなければならない。また絶縁膜１４の
状態が極端になって基板１とｐ型層５０間が完全に絶縁
膜でおおわれてしまうと、選択エピタキシャル成長は使
用し得ないので、その場合は多結晶シリコンの埋め込み
が必要とな）、余分な工程が必要となると同時に、ｐ型
層５の電位を固定するための手段が必要となるが、この
場合でもｐ型層５の製作は前述Ｈ，ＳＵＮＡＭＩ等の用
いた方法等在来の技術で充分可能である。またこのｐ型
層５に相当する部分は高融点金属やそのシリサイドある
いはこれらとシリコンとをくみあわせた積層物でもよい
。Furthermore, in these embodiments, the case where the p-type silicon layer 5 is formed by selective epitaxial method is described, but in reality, it is obvious that the silicon in this part does not have to be single crystal. When the insulating film is in the state 13 or 14, the p-type silicon layer 5 does not become a perfect single crystal, but there is an MI between the silicon layer 5 and the n-type silicon layer 2.
However, in this case, the diffusion coefficient of boron, which is a p-type impurity, is larger than that of other n-type impurities, so the junction is formed within the columnar single crystal region, and the junction characteristics are It won't hurt. However, in this case, the heat treatment temperature and time must be controlled so that the n-type layer 2 portion is completely converted to pH 1. Furthermore, if the condition of the insulating film 14 becomes extreme and the space between the substrate 1 and the p-type layer 50 is completely covered with the insulating film, selective epitaxial growth cannot be used, and in that case, filling with polycrystalline silicon is necessary. ), an extra process is required and at the same time a means for fixing the potential of the p-type layer 5 is required, but even in this case, the p-type layer 5 can be manufactured by the method used by H., SUNAMI, etc. This is fully possible with existing technology. Further, the portion corresponding to this p-type layer 5 may be a high melting point metal, its silicide, or a laminate of these and silicon.

また、本発明には他にもいくつもの変型が考えられ、た
とえばｐ型層５０部分を始めに単結晶シリコンで作って
おき、柱状部分を順次選択エピタキシャル法等で作成す
ることも可能であることは自明である。In addition, there are many other variations to the present invention; for example, it is also possible to make the p-type layer 50 portion first with single crystal silicon, and then create the columnar portions sequentially by selective epitaxial method or the like. is self-evident.

また第２の発明において、場合によっては制御トランジ
スタのチャンネル部になるシリコン層３の周辺部の不純
物濃度を高くするのを省略してもリーク電流の増大する
可能性はあるものの、実用上差つかえない場合もある。In addition, in the second invention, even if the impurity concentration in the peripheral part of the silicon layer 3, which becomes the channel part of the control transistor, is omitted in some cases, there is a possibility that the leakage current will increase, but it is not a practical problem. Sometimes there isn't.

また此処ではｐ基板上にｎ型及びｐ型のエピタキシャル
層を持ったものを使用した場合について述べたが、初め
からｐ基板上にｎ型、ｐ型、ｎ型とエピタキシャル層を
持ったものを使用することも可能であるし、更には、ｐ
型基板上にｎ型及び高抵抗ｎ型エピタキシャル層を持つ
ものを使用し、工程中でｐ型及びｎ型不純物を拡散等で
導入して最終構造を得ることも可能である。Also, here we have discussed the case where a device with n-type and p-type epitaxial layers on a p-substrate is used, but from the beginning, a device with n-type, p-type, and n-type epitaxial layers on a p-substrate is used. It is also possible to use p
It is also possible to obtain the final structure by using a substrate having n-type and high-resistance n-type epitaxial layers and introducing p-type and n-type impurities by diffusion or the like during the process.

また本実施例では、ｎ型層４とアルミ配線９の接続を単
にシリコンとアルミの接続で説明したが、場合によれば
この間にｎ型の多結晶シリコンを設けることも可能であ
るし、更に杜、ｎ型層４の部分をその多結晶シリコンか
らのｎ型不純物の拡散によって行なう等の変型は自由で
ある、また絶縁ｉｊｌ　８の開口部の段差を少くするた
め、絶縁膜８の下層を二酸化シリコンとし上層をリン、
ホウソ等（発明の効果） この結果、本実施例では、４．５ＦｆｆｌＸ３μｍの中
に１５μｍ設計基準でダイナミック型半導体記憶素子を
作成することが出来、このような小面積にもかかわらず
、蓄電用容量面積を２４平方μ＃／、制御用トランジス
タの有効チャンネル長を約１．０μｍ程度と双方充分大
きなものにすることが可能となシ、本発明の有効性が証
明された。またこの結果、本発明を１．５μｍ設計基準
で百方素子（１メガビツト）の記憶回路を作成すれば記
憶素子部分だけでは、１３５平方ミリメータ（４，５ｇ
ｍｘ：１ｇ）、１１１ｍ設計基準で４百万素子の場合は
２４平方ミＩＪメータ（６鰭Ｘ４ｍｍ）となシ、周辺回
路を含めたとしても充分現用の６４ＫＤＲＡＭパッケー
ジと同じ程度の大きさのそれに収容可能であることが判
明した。Furthermore, in this embodiment, the connection between the n-type layer 4 and the aluminum wiring 9 was explained simply as a connection between silicon and aluminum, but depending on the case, it is also possible to provide n-type polycrystalline silicon between them. You are free to modify the n-type layer 4 by diffusing n-type impurities from the polycrystalline silicon.Also, in order to reduce the level difference in the opening of the insulating film 8, the lower layer of the insulating film 8 is Silicon dioxide is used as the upper layer, and phosphorus is used as the upper layer.
(Effect of the invention) As a result, in this example, a dynamic semiconductor memory element can be fabricated with a design standard of 15 μm in 4.5 Fffl×3 μm, and despite such a small area, the storage capacity can be reduced. The effectiveness of the present invention was proved by making it possible to make both the area sufficiently large and the effective channel length of the control transistor approximately 1.0 μm. As a result, if a memory circuit with 100 elements (1 megabit) is created using the present invention based on a 1.5 μm design standard, the memory element portion alone will weigh 135 square millimeters (4.5 g).
mx: 1g), in the case of 4 million elements with a 111m design standard, it would be a 24 square mm IJ meter (6 fins x 4 mm), which is about the same size as a current 64K DRAM package even if peripheral circuits are included. It turned out to be accommodating.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は第１の発明の実施例の１つを示す上面図で、図
中破線で囲まれた領域が１つの半導体記憶素子の占める
部分である。また図中の線分Ａ＋４Ｂ　、（，４Ｄ　、
ＥＬＦ　、Ｇ４＋Ｈにそっての断面図を各々第２図、第
３図、第４図、第５図に示している。 第１図から第１６・図迄の各記号は全て同じものを表わ
しておシ、１は基板ｐ型シリコン、２は柱状のｎ型シリ
コン層、３は柱状ｐ型シリコン層、４は柱状ｎ型シリコ
ン層、５は埋め込まれたｐ型シリコン、６は埋込まれた
絶縁物、７は柱状領域のｐ型層及びその両端のｎ型層の
一部にまで重なるように薄い絶縁層を介して埋込まれた
、ｎ型シリコン層、８は絶縁層、９唸配線用金属、１１
゜１２．１３．１４．は５を埋込む前に作製され、次に
一部を除去された絶縁物層のいろいろな残シ方をした場
合の１部である。 第６図から第１０図は第１の発明の他の実施例を示すも
ので、第６図が平面図、第７〜第１０図が断面図であシ
、第１の実施例の説明図の第１図から第５図に対応する
ものである。 第１１図から第１６図は同様第２の発明の１つの実施例
を示すもので、第１１図が平面図、第１２〜１６図が断
面図であシ、同様第１図から第５図に対応する。但しこ
の場合は構造が少し複雑なため断面図を１枚追加しであ
る。 オ　１　図 Ｈ 第２図 第３図 第４図 Ｅ　Ｆ 第５図 第６図 Ｇ Ｈ オフ図 １８図 ＣＤ オ９図 Ｆ 第１０図 Ｈ 第１１図 Ｉ　Ｇ　Ｅ 第１２図 オ　１３　図 第１４図 オ　１５　図FIG. 1 is a top view showing one embodiment of the first invention, and the area surrounded by broken lines in the figure is the portion occupied by one semiconductor memory element. Also, line segments A+4B, (,4D,
Cross-sectional views along ELF and G4+H are shown in FIGS. 2, 3, 4, and 5, respectively. All the symbols from Fig. 1 to Fig. 16 represent the same thing, 1 is the substrate p-type silicon, 2 is the columnar n-type silicon layer, 3 is the columnar p-type silicon layer, and 4 is the columnar n-type silicon layer. 5 is a buried p-type silicon layer, 6 is a buried insulator, and 7 is a thin insulating layer that overlaps the p-type layer of the columnar region and a part of the n-type layer at both ends thereof. 8 is an insulating layer, 9 is a metal for wiring, 11 is an n-type silicon layer embedded in
゜12.13.14. Figure 5 shows some of the various ways in which the insulator layer was fabricated before embedding 5 and then partially removed. Figures 6 to 10 show other embodiments of the first invention, with Figure 6 being a plan view and Figures 7 to 10 being sectional views, and explanatory views of the first embodiment. This corresponds to FIGS. 1 to 5 of FIG. 11 to 16 similarly show one embodiment of the second invention, in which FIG. 11 is a plan view, FIGS. 12 to 16 are sectional views, and similarly, FIGS. 1 to 5 show an embodiment of the second invention. corresponds to However, in this case, the structure is a little complicated, so one cross-sectional view is added. E 1 Figure H Figure 2 Figure 3 Figure 4 E F Figure 5 Figure 6 G H Off Figure 18 CD O Figure 9 F Figure 10 H Figure 11 I G E Figure 12 O 13 Figure 14 Figure 15

Claims (1)

【特許請求の範囲】 （１ン　第１導電型シリコン単結晶基板の表面に、少な
くとも第２導電型の第１の単結晶シリコン層、その上に
存在する第１導電型の第１の単結晶シリコン層、更にそ
の上に存在する第２導電型の第２の単結晶シリコン層で
構成された柱状の構造を有し、該柱状結晶領域の表面の
内少くとも第２導電型の第１の単結晶層の表面の少くと
も一部分領域が絶縁物でおおわれているか又は全くおお
われていない状態であシ、更にその柱状構造の周辺部が
基板単結晶と電気的に接続された第１導電型単結晶ない
しは多結晶シリコンないしは金属ないしはリコン層およ
びそれに接する第１及び第２の第２表面の少くとも１部
分に薄い絶縁膜が形成され、この絶縁膜上に導体膜が形
成されておシ、その他の部分は絶縁物で取シかこまれて
いることを特徴とする半導体記憶素子。 （２）第１導電型シリコン基板の表面に少くとも第２導
電型の第１の単結晶シリコン層、その上に存在する第１
導電型の第１の単結晶シリコン層、更にその上に存在す
る第２導電型の第２の単結晶シリコン層で構成された柱
状の構造を有し、該柱状結晶領域の表面の内少くとも第
２導電型の第１の単結晶層の表面の少くとも１部分領域
が絶縁物でおおわれているか、又は全くおおわれていな
い状態であシ、更にその柱状構造の周辺部が基板単結晶
と電気的に接続された第１導電型単結晶ないし多結晶シ
リコンないし金属ないしそれらのくみあわせて第２導電
型の第１のシリコン層の途中迄域まっておシ、しかも第
１導電型の第１のシリコン層およびそれに接する第２導
電型の第１のシリコン層の一部分を含む領域以上の部分
において柱状の側壁よシ内側に退いておシ、その退いた
側壁を含む領域で、かつ第１導電型の第１のシリコン層
およびそれに接する第１及び第２の第２導電型シリコン
層の各々の１部分をも含む領域に薄い絶縁膜が形成され
、仁の絶縁膜上に導体膜が形成されておシ、かつ、退い
ていない第１導電型シリコンりかこまれていることを特
徴とする半導体記憶素子。 （３）■第１導電型単結晶シリコン基板上に第２導電型
、第１導電型単結晶シリコン層が形成されたものに対し
て所望の領域を柱状に残して基板に届く迄シリコン層を
除去し、 ＠露出されたシリコン面を絶縁膜でおおい、θ前記基板
から柱状化した第２導電型領域にかけての領域の絶縁膜
の少なくとも一部分を除去し。 Ｏ柱状部の第２導電型領域の途中迄、凹部に第１導電型
の単結晶もしくは多結晶シリコンもしくは金属もしくは
それらのくみあわせを埋込み、■残された凹部を絶縁物
で埋め込み、 ０表面から第２導電型層の一部までの柱状領域で、かつ
、この領域に接する部分の絶縁物を少なくとも除去し、 ■露出シリコン表面にうすい絶縁膜を形成し、■堀込ま
れた部分に柱状構造の頂点以下の高さになるように導体
を埋込み、 ■柱状構造の第１導電型領域頂点部全面に第２導電型不
純物を導入し第２導電型領域を、前記導体の頂点よ）も
深く、かつ下層の第２導電型領域に届かないように作成
することを特徴とする半導体記憶素子の製造方法。 （４）■第１導電型単結晶シリコン基板上に第２導電屋
、第１導電型単結晶シリコン層が形成されたものに対し
て所望の領域を柱状に残して基板に届く迄シリコン層を
除去し、 ＠露出されたシリコン面を絶縁膜でおおい、θ前記基板
から柱状化した第２導電型領域にかけての領域の絶縁膜
の少くとも１部分を除去し、Ｏ柱状部の第２導電型領域
の途中迄、四部に第１導電型の単結晶もしくは多結晶シ
リコンもしくは金属もしくはそれらのくみあわせを埋込
み、■少くとも第１導電型シリコン層の表面に第１導電
型不純物を導入し、 θ残された凹部”を絶縁物で埋め込み、■柱状部分の１
部分を含みこれに接する絶縁物領域の１部分をも含む領
域を第２導電型層に届く迄の深さに除去し、 ■露出シリコン表面にうすい絶縁膜を形成し、■堀込ま
れた部分に柱状構造の頂点以下の高さになるように導体
を埋込み、 ■柱状構造の第１導電型領域頂点部に第２導電型不純物
を導入し、第２導電型領域を、前記導体の頂点よシも深
くかつ下層の第２導電型領域に届かないように作成する
、 ことを特徴とする半導体記憶素子の製造方法。[Scope of Claims] It has a columnar structure composed of a silicon layer and a second single-crystal silicon layer of a second conductivity type existing thereon, and at least a first monocrystalline silicon layer of the second conductivity type is formed on the surface of the columnar crystal region. At least a partial region of the surface of the single crystal layer is covered with an insulator or not covered at all, and the peripheral part of the columnar structure is electrically connected to the substrate single crystal. A thin insulating film is formed on at least a portion of the crystal, polycrystalline silicon, metal, or silicon layer and the first and second second surfaces in contact therewith, and a conductive film is formed on the insulating film, and the like. A semiconductor memory element characterized in that the portion is surrounded by an insulator. (2) A first single crystal silicon layer of at least a second conductivity type on the surface of the first conductivity type silicon substrate, and a first single crystal silicon layer of a second conductivity type on the surface of the first conductivity type silicon substrate. the first existing in
It has a columnar structure composed of a first single-crystal silicon layer of a conductivity type and a second single-crystal silicon layer of a second conductivity type existing thereon, and at least the surface of the columnar crystal region is At least a partial region of the surface of the first single crystal layer of the second conductivity type is covered with an insulating material or is not covered at all, and furthermore, the peripheral part of the columnar structure is electrically connected to the substrate single crystal. The first conductivity type single crystal, polycrystalline silicon, metal, or a combination thereof connected to the first conductivity type single crystal or polycrystalline silicon layer, or a combination of these, may be partially connected to the first conductivity type first silicon layer. The columnar sidewall is inwardly retreated in a region larger than the region including the silicon layer and a part of the first silicon layer of the second conductivity type in contact with the silicon layer, and the first conductive region is A thin insulating film is formed in a region including a first silicon layer of the mold and a portion of each of the first and second second conductivity type silicon layers in contact with the first silicon layer, and a conductive film is formed on the core insulating film. 1. A semiconductor memory element characterized by being surrounded by silicon of a first conductivity type which is solid and does not recede. (3)■ For a structure in which a single crystal silicon layer of a second conductivity type and a first conductivity type is formed on a single crystal silicon substrate of a first conductivity type, the silicon layer is deposited until it reaches the substrate, leaving a desired area in a columnar shape. @ Cover the exposed silicon surface with an insulating film, and θ remove at least a portion of the insulating film in a region from the substrate to the columnar second conductivity type region. Fill the recess with the first conductivity type single crystal or polycrystalline silicon, metal, or a combination thereof up to the middle of the second conductivity type region of the O columnar part, and fill the remaining recess with an insulator, starting from the 0 surface. At least the insulating material in the columnar region up to a part of the second conductivity type layer and in contact with this region is removed, ■ a thin insulating film is formed on the exposed silicon surface, and ■ a columnar structure is formed in the dug part. A conductor is embedded so that the height is below the apex, and a second conductivity type impurity is introduced into the entire surface of the apex of the first conductivity type region of the columnar structure to form a second conductivity type region as deep as the apex of the conductor. A method of manufacturing a semiconductor memory element, characterized in that the semiconductor memory element is formed so as not to reach the second conductivity type region below. (4)■ For a structure in which a second conductive layer and a first conductive type single crystal silicon layer are formed on a first conductive type single crystal silicon substrate, the silicon layer is deposited until it reaches the substrate, leaving a desired area in a columnar shape. ＠ Cover the exposed silicon surface with an insulating film, θ remove at least a part of the insulating film in the region from the substrate to the columnar second conductivity type region, and remove the second conductivity type of the O columnar part. Embed single crystal or polycrystalline silicon of the first conductivity type, metal, or a combination thereof in all four parts up to the middle of the region, ■ introduce impurities of the first conductivity type into at least the surface of the silicon layer of the first conductivity type, and θ Fill the remaining recess with insulating material, and
(1) remove a region including a portion of the insulating material region that is in contact with this to a depth that reaches the second conductivity type layer; (1) form a thin insulating film on the exposed silicon surface; A conductor is embedded so that the height is equal to or lower than the apex of the columnar structure. 2) A second conductivity type impurity is introduced into the apex of the first conductivity type region of the columnar structure, and the second conductivity type region is lowered from the apex of the conductor. A method for manufacturing a semiconductor memory element, characterized in that the semiconductor memory element is formed deeply and so as not to reach the underlying second conductivity type region.