JPS6019708B2 - Image signal binarization circuit - Google Patents
Image signal binarization circuitInfo
- Publication number
- JPS6019708B2 JPS6019708B2 JP52034150A JP3415077A JPS6019708B2 JP S6019708 B2 JPS6019708 B2 JP S6019708B2 JP 52034150 A JP52034150 A JP 52034150A JP 3415077 A JP3415077 A JP 3415077A JP S6019708 B2 JPS6019708 B2 JP S6019708B2
- Authority
- JP
- Japan
- Prior art keywords
- image signal
- circuit
- white
- information
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Facsimile Scanning Arrangements (AREA)
- Fax Reproducing Arrangements (AREA)
- Manipulation Of Pulses (AREA)
- Image Input (AREA)
Description
【発明の詳細な説明】
本発明はファクシミリ、光学的文字読取装置等の走査装
置で得た画信号をディジタル信号に変換する画信号２値
化回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal binarization circuit that converts an image signal obtained by a scanning device such as a facsimile machine or an optical character reading device into a digital signal.
ファクシミリ、光学的文字読取装置等の走査装置におい
ては原稿の情報分布によっては同じ線密度の情報であっ
てもその光電変換出力が光学系のＯＴＦ （ ＯＰＴＩ
ＣＡＬ 、 ＴＲＡＮＳＦＥＲ 、ＦＵＮＣＴＩＯＮ）
、又は光電変換装置等の感度により異なるのが普通であ
る。In scanning devices such as facsimiles and optical character readers, depending on the information distribution of the document, even if the information has the same linear density, the photoelectric conversion output may be transferred to the OTF (OPTI) of the optical system.
CAL, TRANSFER, FUNCTION)
Ordinarily, it differs depending on the sensitivity of the photoelectric conversion device, etc.
例えば第１図ａに示すように高い線密度Ｕｘｌｉｎｅ／
柵の情報があった場合これを走査線１に沿って走査し光
電変換して得た画信号は第１図ｂに示すようにポジ上の
黒、しべルＢに比べてネガ上の白レベルＷ２が４・さく
なるという現象が生ずる。従来、走査装置で得た画信号
はコンパレータで基準電圧と比較して２値化し、その基
準電圧は画信号の白レベルを保持して分圧する方法が知
られている。しかしこのような画信号の２値化方法では
基準電圧が原稿の白情報に追従していても上述の現象に
より基準電圧がポジ上の白レベルＷ，と黒レベルＢとの
間にある場合には、ネガ上の白情報が失われ、又は基準
電圧がネガ上の白レベルＷ２と黒レベルＢ２との間にあ
る場合には、ポジ上の黒情報が失われ、いわゆる白抜け
、黒抜けの現象が起る。そこで特公昭４８一１４１２計
号のように白レベル及び黒レベルのピーク値を保持する
ことにより情報密集部分における白抜け現象を補正する
方法や特公昭４９一３３２０２号のようにスペース及び
マークを検出して３段階の基準電圧で最適２値化パター
ンを発生させる方法が提案されているが、これらの方法
は複雑な回路を用いる必要がある。本発明はこのような
点に鑑み、画信号の２値化時における情報の抜けを簡易
な回路で補償することができる画信号２値化回路を提供
しようとするものである。For example, as shown in Figure 1a, high line density Uxline/
When there is fence information, the image signal obtained by scanning it along scanning line 1 and photoelectrically converting it is black on the positive, and white on the negative compared to label B, as shown in Figure 1b. A phenomenon occurs in which the level W2 decreases by 4. Conventionally, a method is known in which an image signal obtained by a scanning device is compared with a reference voltage using a comparator to be binarized, and the reference voltage is divided while maintaining the white level of the image signal. However, in this method of binarizing image signals, even if the reference voltage follows the white information of the original, due to the phenomenon described above, when the reference voltage is between the positive white level W and the black level B, In this case, the white information on the negative is lost, or if the reference voltage is between the white level W2 on the negative and the black level B2, the black information on the positive is lost, resulting in so-called white spots and black spots. A phenomenon occurs. Therefore, there is a method of correcting white spots in information-dense areas by maintaining the peak values of the white and black levels, as in the case of Special Publication No. 48-1412, and a method of detecting spaces and marks, as shown in Special Publication No. 49-33202. Methods have been proposed in which an optimal binarization pattern is generated using three levels of reference voltages, but these methods require the use of complex circuits. In view of these points, it is an object of the present invention to provide an image signal binarization circuit that is capable of compensating for the omission of information when an image signal is binarized using a simple circuit.
以下図面を参照しらがら本発明の一実施例について説明
する。An embodiment of the present invention will be described below with reference to the drawings.
第２図ａは白抜け補償用の基準電圧ＶＲｅｆ２を設定す
るためのチャートであり、その白情報の最も高い線密度
Ｕｃは走査装置における所望の読取り可能な上限の線密
度を与えている。FIG. 2a is a chart for setting the reference voltage VRef2 for white spot compensation, and the highest line density Uc of the white information gives the desired upper limit line density that can be read by the scanning device.
このチャートを走査装置で走査して光電変換して得た画
信号は第２図ｂに示すような白レベルＷｕＣ、黒レベル
Ｂｕｃの信号となる。したがって線密度Ｕｃより低い線
密度の白情報を走査装置で走査し光電変換して得た信号
は上記白レベルＷｕｃより高いレベルとなる。このため
、ネガ上、あるいは情報の密集した部分における所望の
線密度Ｕｃをもつ白情報を確実に再生するためにはコン
パレータの基準入力電圧ＶＭ２をＷｕＣ〉ＶＲ〆２＞Ｂ
比 ，．，（１｝に設定して画信
号を２値化すれば所望の線密度Ｕｃ以下の糠密度を持つ
情報が再生可能となり、その出力で白抜け補正を行うこ
とができる。The image signal obtained by scanning this chart with a scanning device and photoelectrically converting it becomes a signal of white level WuC and black level Buc as shown in FIG. 2b. Therefore, the signal obtained by scanning white information with a linear density lower than the linear density Uc with a scanning device and photoelectrically converting the white information has a level higher than the white level Wuc. Therefore, in order to reliably reproduce white information with a desired linear density Uc on a negative or in a part where information is dense, the reference input voltage VM2 of the comparator must be set to WuC〉VR〆2>B
Ratio ,． , (1} and binarizes the image signal, it becomes possible to reproduce information having a bran density lower than the desired linear density Uc, and white spot correction can be performed using the output.
第３図は本発明の一実施例であり、第４図はそのタイミ
ングチャートである。走査装置で原稿○を走査して光電
変換し得た酉信号Ａは走査装置における光学系のＯＴＦ
、又は光電変換素子の感度等により情報密度の高い部分
の白レベルに比でて情報密度の低い部分の黒レベルがあ
る線密度以上では高くなる。この画信号Ａの白レベルは
白レベル保持回路１で保持されて分圧回路２で分圧され
コンパレータ３に基準電圧ＶＲのとして入力される。コ
ンパレータ３は画信号Ａをこの基準電圧Ｖ船，と比較し
て２値化しディジタル信号を出力する。このディジタル
信号は白抜け補正回路４により白抜けが補償される。す
なわち、画信号Ａは不等式‘１１を満足するように設定
された基準電圧ＶＲ８ｆ２とコンパレータ５で比較され
て２値化される。遅延回路６〜８はクロツクパルスが加
えられて遅延動作を行ない、遅延回路６がコンパレータ
５よりのディジタル信号Ｄを１ビット分遅延させると共
に遅延回路７が遅延回路６の出力信号Ｃを１ビット分遅
延させて信号８を得ている。ところで、画信号の情報密
度が高い部分においては所望の線密度Ｕｃに近い線密度
をもつ白情報の両端の信号はそれよりも低いレベルにあ
るからその白情報を白と判定するためには次の論理式を
満足すればよい。Ｇ＝ＤＣＥ＝Ｄ＋Ｅ・Ｃ
…‘２１この■式に基づいてノア回路９及びアンド回
路１０がＦ＝Ｄ十８、Ｇ：Ｆ・Ｃ
なる演算を行ない、線密度が高い部分の白情報Ｇを得て
いる。FIG. 3 shows one embodiment of the present invention, and FIG. 4 is a timing chart thereof. The signal A obtained by scanning the document ○ with the scanning device and photoelectrically converting it is the OTF of the optical system in the scanning device.
Or, due to the sensitivity of the photoelectric conversion element, etc., the black level of a portion with low information density becomes higher than the white level of a portion with high information density above a certain linear density. The white level of this image signal A is held by a white level holding circuit 1, divided by a voltage dividing circuit 2, and inputted to a comparator 3 as a reference voltage VR. The comparator 3 compares the image signal A with this reference voltage V, binarizes it, and outputs a digital signal. This digital signal is compensated for white spots by the white spot correction circuit 4. That is, the image signal A is compared with the reference voltage VR8f2 set to satisfy inequality '11 by the comparator 5, and is binarized. Delay circuits 6 to 8 perform delay operations when clock pulses are applied, and delay circuit 6 delays digital signal D from comparator 5 by 1 bit, and delay circuit 7 delays output signal C from delay circuit 6 by 1 bit. I am getting signal 8. By the way, in the part where the information density of the image signal is high, the signals at both ends of the white information having a line density close to the desired line density Uc are at a lower level, so in order to determine that white information as white, the following steps are required. It is sufficient to satisfy the logical formula. G=DCE=D+E・C
...'21 Based on this equation (2), the NOR circuit 9 and the AND circuit 10 perform the calculations F=D18, G:F·C, and obtain the white information G of the portion where the line density is high.
遅延回路８はコンパレータ３からのディジタル信号をア
ンド回路１０の出力信号Ｇと同期されるために１ビット
分遅延させる。この遅延回路８からのディジタル信号Ｂ
はオア回路１１でアンド回路１０の出力信号Ｇとのオア
がとられてＨ＝Ｂ＋Ｇとなり、コンパレータ３での２値
化により失われた白情報Ｇが補償される。なお、説明の
都合上、第４図においてＢ〜則ま０、Ａより１ビット分
進めて示してある。以上のように本発明による函信号２
値化回路によれば走査装置で得た画信号を基準電圧と比
較して２値化する場合に函信号を上記基準電圧と異なる
基準電圧と比較してその出力信号の情報密度が高い部分
で情報の抜けを補正するので、画信号の２値化時におけ
る情報の抜けを補償することができ、かつ極めて簡易な
回路を用いて実施することができる。The delay circuit 8 delays the digital signal from the comparator 3 by one bit in order to be synchronized with the output signal G of the AND circuit 10. Digital signal B from this delay circuit 8
is ORed with the output signal G of the AND circuit 10 in the OR circuit 11 to obtain H=B+G, and the white information G lost due to the binarization in the comparator 3 is compensated for. For convenience of explanation, in FIG. 4, B to 0 are shown one bit ahead of A. As described above, the box signal 2 according to the present invention
According to the digitization circuit, when the image signal obtained by the scanning device is compared with a reference voltage and binarized, the box signal is compared with a reference voltage different from the above reference voltage, and the output signal is detected at a portion where the information density is high. Since missing information is corrected, it is possible to compensate for missing information when the image signal is binarized, and it can be implemented using an extremely simple circuit.
第１図ａ，ｂは原稿の情報分布例及びその読取り信号を
示す図、第２図ａ，ｂは本発明の一実施例で用いた基準
電圧設定用チャート及びその議取り信号を示す図、第３
図は本発明の−実施例を示すブロック図、第４図は同実
施例のタイムチャートである。
３，４……コンパレータ、６，７……遅延回路、９・・
・・・・ノア回路、１０・・・・・・アンド回路、１１
．．・．・・オア回路。
椿イ図
第２図
精３図
稀４図1A and 1B are diagrams showing an example of information distribution of a document and its reading signal; FIGS. 2A and 2B are diagrams showing a reference voltage setting chart and its discussion signal used in an embodiment of the present invention; Third
The figure is a block diagram showing an embodiment of the present invention, and FIG. 4 is a time chart of the embodiment. 3, 4... Comparator, 6, 7... Delay circuit, 9...
...NOR circuit, 10...AND circuit, 11
．． ．．・．． ...OR circuit. Camellia I figure 2 Sei 3 figure rare 4 figure
Claims (1)
回路からの基準電圧で前記画信号を２値化する第１の比
較手段と、この第１の比較手段の出力信号を遅延させる
第１の遅延手段と、前記画信号を前記基準電圧とは異な
る基準電圧で２値化する第２の比較手段と、この第２の
比較手段の出力信号を遅延させる第２の遅延手段と、こ
の第２の遅延手段の出力信号を遅延させる第３の遅延手
段と、この第３の遅延手段の出力信号と前記第２の比較
手段の出力信号とのノアをとつてこのノア出力と前記第
２の遅延手段の出力信号とのアンドをとりこのアンド出
力と前記第１の遅延手段の出力信号とのオアをとる手段
とを備えた画信号２値化回路。1. A circuit that generates a reference voltage from an input image signal, a first comparing means that binarizes the image signal using the reference voltage from this circuit, and a first comparing means that delays the output signal of the first comparing means. a second comparison means for binarizing the image signal with a reference voltage different from the reference voltage; a second delay means for delaying the output signal of the second comparison means; a third delay means for delaying the output signal of the second delay means; and a third delay means for delaying the output signal of the second delay means; An image signal binarization circuit comprising means for ANDing the output signal of the delay means and ORing the AND output and the output signal of the first delay means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52034150A JPS6019708B2 (en) | 1977-03-28 | 1977-03-28 | Image signal binarization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52034150A JPS6019708B2 (en) | 1977-03-28 | 1977-03-28 | Image signal binarization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53118917A JPS53118917A (en) | 1978-10-17 |
| JPS6019708B2 true JPS6019708B2 (en) | 1985-05-17 |
Family
ID=12406159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52034150A Expired JPS6019708B2 (en) | 1977-03-28 | 1977-03-28 | Image signal binarization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6019708B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6310215U (en) * | 1986-07-07 | 1988-01-23 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5784670A (en) * | 1980-11-17 | 1982-05-27 | Fujitsu Ltd | Video signal read-in system |
| US5057936A (en) * | 1989-08-21 | 1991-10-15 | Xerox Corporation | Copy quality monitoring |
-
1977
- 1977-03-28 JP JP52034150A patent/JPS6019708B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6310215U (en) * | 1986-07-07 | 1988-01-23 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53118917A (en) | 1978-10-17 |
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