JPS60196910A - Hybrid integrated circuit and manufacture thereof - Google Patents
Hybrid integrated circuit and manufacture thereofInfo
- Publication number
- JPS60196910A JPS60196910A JP5322384A JP5322384A JPS60196910A JP S60196910 A JPS60196910 A JP S60196910A JP 5322384 A JP5322384 A JP 5322384A JP 5322384 A JP5322384 A JP 5322384A JP S60196910 A JPS60196910 A JP S60196910A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- magnetic ceramic
- hole
- hybrid
- coil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000000919 ceramic Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 239000011247 coating layer Substances 0.000 claims description 8
- 239000006247 magnetic powder Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 238000007639 printing Methods 0.000 abstract description 5
- 238000005245 sintering Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2814—Printed windings with only part of the coil or of the winding in the printed circuit board, e.g. the remaining coil or winding sections can be made of wires or sheets
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明はハイブリッドＩＣ特に磁心入り線輪体が搭載さ
れたハイブリ、ラドＩＣ及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a hybrid IC, particularly a hybrid IC equipped with a magnetic core-containing wire ring, and a method for manufacturing the same.
（ｂ）技術の背景
ハイブリッドＩＣは基板上に厚膜或いは薄膜方式で受動
素子と回路パターンを形成し、さらに半導体チップ等の
能動素子を組込むものであるが、厚膜或いは薄膜方式で
形成困難な大容量の線輪体或いはコンデンサ等の受動素
子は、チップ形にして半導体チップ等と同様に組込むの
が一般的である。(b) Background of the technology Hybrid ICs form passive elements and circuit patterns on a substrate using a thick film or thin film method, and then incorporate active elements such as semiconductor chips. Passive elements such as capacitors or capacitors are generally formed into chips and assembled in the same way as semiconductor chips.
（Ｃ）従来技術と問題点
第１図は従来のハイブリッドＩＣの一例を示す図テ、（
イ）（ロ）（ハ）はそれぞれ製造過程を示す断面図、（
ニ）はハイブリッドＩＣの正面図である。(C) Prior art and problems Figure 1 shows an example of a conventional hybrid IC.
A), (B), and (C) are cross-sectional views showing the manufacturing process, respectively.
D) is a front view of the hybrid IC.
従来のハイブリッドＩＣは第１図（イ）のように、角板
状のセラミック基板（例えばアルミナ基板）１の表面に
所望の回路パターン２および受動素子を印刷、焼成して
形成している。そしてチップ形部品を搭載す雇所望の回
路パターン２の表面に、第１図（ロ）のように半田ペー
ストを印刷して半田層３を設けている。A conventional hybrid IC, as shown in FIG. 1(a), is formed by printing and firing a desired circuit pattern 2 and passive elements on the surface of a square plate-shaped ceramic substrate (for example, an alumina substrate) 1. Then, a solder layer 3 is provided by printing solder paste on the surface of the desired circuit pattern 2 on which the chip-shaped component is to be mounted, as shown in FIG. 1(b).
第１図（ハ）において５は大容量のコンデンサなどのチ
ップ部品である。また４は磁心入りチ・ノブ形線輪体（
例えばチップ形コイル）である。In FIG. 1(c), 5 is a chip component such as a large capacity capacitor. 4 is a chi-knob wire ring with a magnetic core (
For example, a chip-shaped coil).
このチップ形線輪体４およびチップ部品５を所望の半田
Ｎ３の上面に仮り止めした上で、熱板や、ベルト炉を通
してリフローさせ、チップ形線輪体４、チップ部品５を
含めて多数のチ・ノブを一度に搭載している。また８は
セラミック基板１０側縁部に突出して設けられた外部端
子であって、セラミンク基板１の表面のリードパターン
部分にチップの半田付は時と同時に半田付けされている
。The chip-shaped wire wheel body 4 and the chip component 5 are temporarily fixed on the upper surface of the desired solder N3, and then reflowed through a hot plate or belt furnace, and a large number of chips including the chip-shaped wire wheel body 4 and the chip component 5 are soldered. It is equipped with a chi knob at once. Reference numeral 8 denotes an external terminal protruding from the side edge of the ceramic substrate 10, and the chip is soldered to the lead pattern portion on the surface of the ceramic substrate 1 at the same time.
このように形成されたハイブリッドＩＣの外部端子８を
除いた全表面を第１図（ニ）のように、ディッピング或
いは流動浸漬法等の手段により樹脂コーテング層７ （
例えばエポキシ樹脂、シリコーン樹脂等）で封止してハ
イブリッドＩＣ６を製造している。As shown in FIG. 1(d), the entire surface of the hybrid IC formed in this way except for the external terminals 8 is coated with a resin coating layer 7 (
For example, the hybrid IC 6 is manufactured by sealing with epoxy resin, silicone resin, etc.).
しかしこのようなハイブリッドＩＣ６は、チップ形線輪
体４が磁心入すのため比較的大形となり、ハイブリッド
ＩＣの小形化を阻止しているという問題点がある。However, such a hybrid IC 6 has a problem in that it is relatively large because the chip-shaped wire ring 4 is inserted into the magnetic core, which prevents miniaturization of the hybrid IC.
（ｄ）発明の目的
本発明の目的は上記従来の問題点に鑑み、基板の一部を
コアとすることにより、小形のハイブリッドＩＣの提供
、及びその製造方法を提供することにある。(d) Object of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a small-sized hybrid IC by using a part of the substrate as a core, and a method for manufacturing the same.
（ｅ）発明の構成
この目的を達成するために本発明は、磁性セラミック基
板に所望にスルーホール用孔を並設し、該スルーホール
用孔の内面および該磁性セラミック基板の表面、裏面を
絶縁層で被覆した後に、該スルーホール用孔内を導体金
属でメッキ或いは導電性ペーストを充填してスルーホー
ルとなし、該磁性セラミック基板の表面および裏面に形
成するコイルパターンにより該スルーホールをコイル状
に連結して、該磁性セラミック基板の一部をコアとする
線輪体を設け、該ハイブリッドＩＣの高さを低くすると
ともに、該線輪体の表面に絶縁層をさらに設けて、該線
輪体の上部にも回路パターンを形成することが可能にし
て小形化にしたものである。また、該ハイブリッドＩＣ
のパッケージの全表面、及びアース用外部端子の根本部
分を磁性粉混入樹脂でコーテングして磁気シールドした
ものである。(e) Structure of the Invention In order to achieve this object, the present invention provides through-hole holes in a magnetic ceramic substrate as desired, and insulates the inner surface of the through-hole holes and the front and back surfaces of the magnetic ceramic substrate. After coating with a layer, the inside of the through hole is plated with a conductive metal or filled with conductive paste to form a through hole, and the through hole is formed into a coil shape by a coil pattern formed on the front and back surfaces of the magnetic ceramic substrate. A wire ring whose core is a part of the magnetic ceramic substrate is provided to reduce the height of the hybrid IC, and an insulating layer is further provided on the surface of the wire ring. This makes it possible to form a circuit pattern on the upper part of the body, making it more compact. In addition, the hybrid IC
The entire surface of the package and the base of the external grounding terminal are coated with resin mixed with magnetic powder to provide magnetic shielding.
（ｆ）発明の実施例
以下図示実施例を参照して本発明について詳細に説明す
る。(f) Embodiments of the Invention The present invention will be described in detail below with reference to illustrated embodiments.
第２図は本発明の一実施例を示す図で、（イ）（ロ）（
ハ）（ニ）（へ）はそれぞれ製造過程を示す断面図、（
ホ）は平面図、（ト）はハイブリッドＩＣの正面図であ
り、第３図は他の一実施例のハイブリッドＩＣの断面図
である。FIG. 2 is a diagram showing an embodiment of the present invention, and shows (a), (b), and
C) (D) and (F) are cross-sectional views showing the manufacturing process, respectively.
(E) is a plan view, (G) is a front view of the hybrid IC, and FIG. 3 is a sectional view of the hybrid IC of another embodiment.
本発明のハイブリッドＩＣｌ０は第２図（イ）のように
、角板状の磁性セラミック基板（例えばフエ、ライト基
板） １１の所望の個所に２列にスルーホール用孔１２
を例えばレーザー加工して並列して設けである。そして
第２図（ロ）のようにスルーホール用孔１２の内面及び
磁性セラミック基板１１の表面、裏面をともにアルミナ
のグリーンシート等で被覆し加熱して絶縁層１３を設け
て絶縁している。As shown in FIG. 2(A), the hybrid ICl0 of the present invention has two rows of through-hole holes 12 at desired locations on a square plate-shaped magnetic ceramic substrate (for example, a Fe, light substrate) 11.
For example, they are processed by laser and arranged in parallel. Then, as shown in FIG. 2(b), the inner surface of the through-hole hole 12 and the front and back surfaces of the magnetic ceramic substrate 11 are both coated with an alumina green sheet or the like and heated to form an insulating layer 13 for insulation.
その後第２図（ハ）のように絶縁層１３で被覆されたス
ルーホール用孔１２の孔に導電性ペーストを充填して、
磁性セラミック基板１１０表面および裏面を連結する導
体層を設け、スルーホール用孔工２をスルーホール１４
にしている。なおこ −の導体層は金属メッキなどして
形成しても良い。Thereafter, as shown in FIG. 2(c), the holes of the through-hole holes 12 covered with the insulating layer 13 are filled with conductive paste.
A conductive layer connecting the front and back surfaces of the magnetic ceramic substrate 110 is provided, and the through-hole drilling 2 is formed into the through-hole 14.
I have to. Note that this conductor layer may be formed by metal plating or the like.
そしてスルーホール１４を形成した後、第２図（ニ）（
ホ）のように磁性セラミック基板１１の表面及び裏面の
絶縁層１３上に、それぞれのスルーホール１４をコイル
状に接続するコイルパターン１５と所望のリードパター
ン１６を印刷し焼成して、２列のスルーホール１４の間
の磁性セラミック基板部分をコアとする所望の線輪体を
完成させる。After forming the through hole 14, FIG.
As shown in (e), on the insulating layer 13 on the front and back surfaces of the magnetic ceramic substrate 11, a coil pattern 15 for connecting each through hole 14 in a coil shape and a desired lead pattern 16 are printed and fired to form two rows. A desired wire ring body having the magnetic ceramic substrate portion between the through holes 14 as a core is completed.
次ぎに第２図（へ）のようにコイルパターン１５の上面
に絶縁層１７を形成する。そして絶縁層１３及び絶縁層
１７の表面に所望の回路パターン１８および受動素子を
印刷、焼成して形成する。Next, as shown in FIG. 2(f), an insulating layer 17 is formed on the upper surface of the coil pattern 15. Then, a desired circuit pattern 18 and passive elements are formed on the surfaces of the insulating layer 13 and the insulating layer 17 by printing and firing.
そしてチップ形部品を搭載する所望の回路パターン１８
の表面に、半田ペーストを印刷して半田層１９を設ける
。そして所望のチップ部品を所望の半田層１９の上面に
仮り止めした上で、熱板や、ベルト炉を通してリフロー
させて搭載する。また８は磁性セラミック基板１１の側
縁部に突出して設けられた外部端子であり、８Ａはアー
ス用外部端子である。外部端子８及びアース用外部端子
８Ａは、磁性セラミック基板１１の表面のリードパター
ン部分にチップの半田付は時と同時に半田付けされてい
る。and a desired circuit pattern 18 on which chip-shaped components are mounted.
A solder layer 19 is provided on the surface by printing a solder paste. After a desired chip component is temporarily fixed on the upper surface of a desired solder layer 19, it is mounted by reflowing it through a hot plate or belt furnace. Further, 8 is an external terminal provided protruding from the side edge of the magnetic ceramic substrate 11, and 8A is an external terminal for grounding. The external terminal 8 and the external grounding terminal 8A are soldered to the lead pattern portion on the surface of the magnetic ceramic substrate 11 at the same time as the chip is soldered.
このように形成されたハイブリッドＩＣの外部端子８及
びアース用外部端子８Ａを除いた全表面を第２図（ト）
のように、ディッピング或いは流動浸漬法等の手段によ
り樹脂コーテング層７ （例えばエポキシ樹脂、シリコ
ーン樹脂等）で封止してハイブリッドＩＣｌ０が完成す
る。The entire surface of the hybrid IC formed in this way, excluding the external terminal 8 and the external grounding terminal 8A, is shown in Figure 2 (T).
The hybrid ICl0 is completed by sealing with a resin coating layer 7 (for example, epoxy resin, silicone resin, etc.) by dipping or fluidized dipping.
上述のようなハイブリッドＩＣｊＯは、基板の表面にチ
ップ形線輪体を搭載する代わりに、磁性セラミック基板
１１内に所望の線輪体が設けられているので、高さが低
くて小形である。また磁性セラミック基板１１内に設け
られた線輪体の上部に、他の平面部分とほぼ同様に所望
の回路パターン及び受動素子を印刷、焼成することがで
きるので、基板面積の有効利用を計ることができ、ハイ
ブリッドＩＣをさらに小形化することが可能である。The above-described hybrid ICjO has a desired wire body inside the magnetic ceramic substrate 11 instead of mounting a chip-shaped wire body on the surface of the substrate, so it is low in height and small in size. Further, since desired circuit patterns and passive elements can be printed and fired on the upper part of the wire ring provided in the magnetic ceramic substrate 11 in almost the same way as on other flat parts, the board area can be used effectively. This makes it possible to further downsize the hybrid IC.
第３図のハイブリッドＩＣ２０は、第２図の如くに形成
されたハイブリッドＩＣｌ０の、樹脂コーテング層７の
全表面、及びアース用外部端子８Ａの根本部分が磁性粉
混入樹脂でコーテングされて、磁性粉混入樹脂コーテン
グ層２１が形成されている。In the hybrid IC 20 shown in FIG. 3, the entire surface of the resin coating layer 7 and the root part of the external earth terminal 8A of the hybrid IC 10 formed as shown in FIG. 2 are coated with magnetic powder-containing resin. A mixed resin coating layer 21 is formed.
このように磁性粉混入樹脂コーテング層２１が設けられ
ているので、ハイブリッドＩＣ２０は磁気シールドされ
ている。このようなハイブリッドＩＣ２０は、金属ケー
ス内に封止して磁気シールドした従来のハイブリッドＩ
Ｃに比較して、構成が簡単で、且つ小形である。Since the resin coating layer 21 containing magnetic powder is provided in this manner, the hybrid IC 20 is magnetically shielded. Such a hybrid IC 20 is a conventional hybrid IC sealed in a metal case and magnetically shielded.
Compared to C, the structure is simpler and smaller.
（ｇ）発明の詳細
な説明したように本発明は、基板とじて磁性セラミック
基板を使用し、そのスルーホールに囲まれた部分をコア
として線輪体を形成したことにより、基板面積の有効利
用が計られ、ハイブリッドＩＣが小形化され、さらにま
た磁気シールドが容易であるなどという実用上で極めて
優れた効果がある。(g) Detailed Description of the Invention As described above, the present invention uses a magnetic ceramic substrate as a substrate, and forms a wire ring with the portion surrounded by through holes as a core, thereby making effective use of the substrate area. It has extremely excellent practical effects, such as reducing the size of the hybrid IC, and making magnetic shielding easier.
第１図は従来のハイブリッドＩＣの一例を示す図で、（
イ）（ロ）（ハ）はそれぞれ製造過程を示す断面図、（
ニ）はハイブリッドＩＣの正面図であり、第２図は本発
明の一実施例を示す図で、（イ）（ロ）（ハ） （ニ）
（へ）はそれぞれ製造過程を示す断面図、（ホ）は平
面図、（ト）はハイブリッドＩＣの正面図、第３図は他
の一実施例のハイブリッドＩＣの断面図である。
図中１はセラミック基板、２，１８は回路パターン、３
．１９は半田層、４はチップ形線輪体、６．１０．２０
はハイブリッドＩＣ，７は樹脂コーテング層、８は外部
端子、８Ａはアース用外部端子、１１は磁性セラミック
基板、１３．１７は絶縁層、１４はスルーホール、１５
はコイルパターン、１６はリードパターン、２１は磁性
粉混入樹脂コーテング層をそれぞれ示す。
察／［
２
番 ？ 唄Figure 1 shows an example of a conventional hybrid IC.
A), (B), and (C) are cross-sectional views showing the manufacturing process, respectively.
D) is a front view of the hybrid IC, and FIG. 2 is a diagram showing an embodiment of the present invention, with (A) (B) (C) (D)
(F) is a cross-sectional view showing the manufacturing process, (E) is a plan view, (G) is a front view of the hybrid IC, and FIG. 3 is a cross-sectional view of the hybrid IC of another embodiment. In the figure, 1 is a ceramic substrate, 2 and 18 are circuit patterns, and 3
．． 19 is a solder layer, 4 is a chip-shaped wire ring, 6.10.20
is a hybrid IC, 7 is a resin coating layer, 8 is an external terminal, 8A is an external terminal for grounding, 11 is a magnetic ceramic substrate, 13.17 is an insulating layer, 14 is a through hole, 15
16 is a coil pattern, 16 is a lead pattern, and 21 is a resin coating layer containing magnetic powder. Inspection/[No. 2? song
Claims (1)
ーホールと、該磁性セラミック基板の表面および裏面に
形成されたコイルパターンとにより該磁性セラミンク基
板をコアとする線輪体が設けられてなることを特徴とす
るハイブリッドＩＣ。 （２） 磁性セラミック基板に並・設して設けられたス
ルーホールと、該磁性セラミック基板の表面および裏面
に形成されたコイルパターンとにより該磁性セラミック
基板をコアとする線輪体が設けられたハイブリッドＩＣ
のパフケージの全表面、及びアース用外部端子の根本部
分に磁性粉混入樹脂コーテング層が設けられてなること
を特徴とするハイブリッドＩＣ。 （３）磁性セラミック基板に所望にスルーホール用孔を
並設し、該スルーホール用孔の内面および該磁性セラミ
ック基板の表面、裏面を絶縁層で被覆した後に、該スル
ーホール用孔内に導体層を設けてスルーホールとなし、
該磁性セラミック基板の表面および裏面に形成するフィ
ルパターンにより該スルーホールをコイル状に連結して
、該磁性セラミック基板の一部をコアとする線輪体を設
けることを特徴とするハイブリッドＩｃの製造方法。[Claims] +11 Through holes provided in parallel on the magnetic ceramic substrate and coil patterns formed on the front and back surfaces of the magnetic ceramic substrate create a wire ring body having the magnetic ceramic substrate as a core. A hybrid IC characterized by being provided with: (2) A wire ring body having the magnetic ceramic substrate as a core is provided by through holes arranged in parallel on the magnetic ceramic substrate and coil patterns formed on the front and back surfaces of the magnetic ceramic substrate. Hybrid IC
A hybrid IC characterized in that a resin coating layer containing magnetic powder is provided on the entire surface of the puff cage and the base of the external grounding terminal. (3) After forming through-hole holes in a magnetic ceramic substrate in parallel as desired, and coating the inner surface of the through-hole holes and the front and back surfaces of the magnetic ceramic substrate with an insulating layer, conductors are inserted into the through-hole holes. Create a layer to create a through hole,
Production of a hybrid IC characterized in that the through holes are connected in a coil shape by fill patterns formed on the front and back surfaces of the magnetic ceramic substrate to provide a wire ring having a part of the magnetic ceramic substrate as a core. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5322384A JPS60196910A (en) | 1984-03-19 | 1984-03-19 | Hybrid integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5322384A JPS60196910A (en) | 1984-03-19 | 1984-03-19 | Hybrid integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60196910A true JPS60196910A (en) | 1985-10-05 |
Family
ID=12936822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5322384A Pending JPS60196910A (en) | 1984-03-19 | 1984-03-19 | Hybrid integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60196910A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690461A1 (en) * | 1994-06-30 | 1996-01-03 | AT&T Corp. | Method for making devices using metallized magnetic substrates |
| EP0880150A2 (en) * | 1997-05-22 | 1998-11-25 | Nec Corporation | Printed wiring board |
| KR100294956B1 (en) * | 1997-05-19 | 2001-07-12 | 가네꼬 히사시 | Reducing electromagnetic noise radiated from a printed board |
| WO2006088146A1 (en) * | 2005-02-21 | 2006-08-24 | Tokyo Electron Limited | Inductance element |
| CN108231371A (en) * | 2016-12-15 | 2018-06-29 | 昆山福仕电子材料工业有限公司 | Two-side film membrane inductor and preparation method thereof |
-
1984
- 1984-03-19 JP JP5322384A patent/JPS60196910A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0690461A1 (en) * | 1994-06-30 | 1996-01-03 | AT&T Corp. | Method for making devices using metallized magnetic substrates |
| KR100294956B1 (en) * | 1997-05-19 | 2001-07-12 | 가네꼬 히사시 | Reducing electromagnetic noise radiated from a printed board |
| EP0880150A2 (en) * | 1997-05-22 | 1998-11-25 | Nec Corporation | Printed wiring board |
| EP0880150A3 (en) * | 1997-05-22 | 1999-08-18 | Nec Corporation | Printed wiring board |
| KR100294957B1 (en) * | 1997-05-22 | 2001-07-12 | 가네꼬 히사시 | Printed wiring board |
| WO2006088146A1 (en) * | 2005-02-21 | 2006-08-24 | Tokyo Electron Limited | Inductance element |
| CN108231371A (en) * | 2016-12-15 | 2018-06-29 | 昆山福仕电子材料工业有限公司 | Two-side film membrane inductor and preparation method thereof |
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