JPS60195957A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS60195957A
JPS60195957A JP59050939A JP5093984A JPS60195957A JP S60195957 A JPS60195957 A JP S60195957A JP 59050939 A JP59050939 A JP 59050939A JP 5093984 A JP5093984 A JP 5093984A JP S60195957 A JPS60195957 A JP S60195957A
Authority
JP
Japan
Prior art keywords
lead frame
resin
lead
semiconductor chip
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59050939A
Other languages
Japanese (ja)
Inventor
Takahiro Tanigawa
谷川　喬太
Hiroshi Nakazawa
中沢　洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59050939A priority Critical patent/JPS60195957A/en
Publication of JPS60195957A publication Critical patent/JPS60195957A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the contacting property between a lead frame and a resin and to enhance the sealability and the reliability by stepwisely forming the side of the lead frame, and increasing the contacting surface with the resin. CONSTITUTION:Projections 8, 15 are formed on tabs 4, 13 of a lead frame, tab hanging lead 5 and the sides of leads 6, 14. The projection 8 is formed by a suitable method. The lead frame 12 is, for example, composed of 42-alloy. A semiconductor chip 9 is formed, for example, of silicon single crystal substrate, many circuit elements are formed in the chip by the know technique, and one circuit function is formed. A resin sealer 11 is formed, for example, of epoxy resin, and molded by a known transfer molding method.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はリードフレームに関し、特に、モールドレジン
との密層性を良くし、封止性のよい樹脂封止型半導体装
置を得ることができるリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a lead frame, and in particular to a lead frame that can improve the tightness with a mold resin and provide a resin-sealed semiconductor device with good sealing performance. .

〔背景技術〕　′ リードフレームの構造の一例としては第１図に示すごと
きものが周知である（工業調査公刊ｒＩＣ化実装技術Ｊ
Ｐ１３７〜Ｐ１５０など）。第１図にて、１は半導体チ
ップをマウントするタブ、２はこのタブを吊りているタ
ブ吊りリード、３は半導体チップの内部配線をコネクタ
ワイヤにより外部に引出するリードである。このリード
側の電極及び半導体チップ側の電極をコネクタワイヤを
用いて、周知の超音波ボンディング法などによりボンデ
ィングして電気的接続を行った後に、樹脂（レジン）を
周知のトランスファーモールド法などにより半導体チッ
プやボンディング部上にモールドし、リード３を切断成
形するなどして樹脂封止型の半導体装置を得ることがで
きる。[Background Art] ' As an example of the structure of a lead frame, the one shown in Fig. 1 is well known (Industrial Research Publication rIC Mounting Technology J
P137 to P150, etc.). In FIG. 1, 1 is a tab for mounting a semiconductor chip, 2 is a tab suspension lead for suspending this tab, and 3 is a lead for leading out the internal wiring of the semiconductor chip to the outside by a connector wire. After electrical connection is made by bonding the electrodes on the lead side and the electrodes on the semiconductor chip side using a connector wire using a well-known ultrasonic bonding method, etc., resin is applied to the semiconductor chip using a well-known transfer molding method etc. A resin-sealed semiconductor device can be obtained by molding on a chip or a bonding portion and cutting and molding the leads 3.

ところで、かかる樹脂封止型半導体装置にあっては、リ
ードフレームとレジンとの密着性を良好圧し、封止性（
耐湿性）を向上させ、信頼度を向上させることが必要で
あり、近時は半導体チップの大形化に伴ない、封止中が
増々狭くなっており、これら事項の重要性も増大してい
る。By the way, in such a resin-sealed semiconductor device, good adhesion between the lead frame and the resin is achieved, and sealing performance (
It is necessary to improve moisture resistance (humidity resistance) and reliability.As semiconductor chips have become larger in recent years, the encapsulation area has become narrower and narrower, and the importance of these matters has also increased. There is.

従来のこのような樹脂封止型の半導体装置に使用される
リードフレームにあっては、その側面がフラットに構成
されており、リードフレームとレジンとの密着性が不足
し、封止性、信頼度の向上という面で問題があることが
わかった。The conventional lead frames used in such resin-sealed semiconductor devices have flat sides, resulting in insufficient adhesion between the lead frame and the resin, resulting in poor sealing performance and reliability. It was found that there was a problem in terms of improving performance.

〔発明の目的〕[Purpose of the invention]

本発明はリードフレームとレジンとの密着（接触）面積
を増大させて、リードフレームとレジンとの密着性を良
好にし、封止性を向上し、信頼度の高い樹脂封止型半導
体装置を得ることができるリードフレームを提供するこ
とを目的としたものである。The present invention increases the adhesion (contact) area between the lead frame and the resin, improves the adhesion between the lead frame and the resin, improves sealing performance, and provides a highly reliable resin-sealed semiconductor device. The purpose is to provide a lead frame that can be used.

本発明の前記ならびＫそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are:
It will become clear from the description of this specification and the accompanying drawings.

〔発明のａ要部 本願において開示される発明のうち代表的なもののｇ＊
を簡単に説明すれば、下記のとおりである。[A main part of the invention (g) representative of the inventions disclosed in this application
A brief explanation is as follows.

すなわち、本発明ではリードフレームの側面に段付けを
行い、レジンとの接触面を増大させ、リードフレームと
レジンとの密着性を良好にし、リードフレーム表面積増
大によるリークパスの伸長をはかって外部からの湿気等
の浸透性異物の侵入の半導体チップへの到達時間を長く
して、封止性を向上させ、製品寿命を延命し、信頼性を
向上させることに成功した。That is, in the present invention, the side surface of the lead frame is stepped to increase the contact surface with the resin, improve the adhesion between the lead frame and the resin, and extend the leak path by increasing the surface area of the lead frame, thereby reducing the leakage from the outside. The company succeeded in lengthening the time it takes for penetrating foreign substances such as moisture to reach the semiconductor chip, improving sealing performance, extending product life, and improving reliability.

〔実施例〕〔Example〕

次に、本発明を実施例に基づき説明する。 Next, the present invention will be explained based on examples.

第２図は本発明リードフレームの要部斜視図、第３図は
第２図Ｉ−Ｉ線断面図を示す。FIG. 2 is a perspective view of a main part of the lead frame of the present invention, and FIG. 3 is a sectional view taken along the line II in FIG. 2.

これら図において、４は半導体チップを搭載するための
タブ、５はタブ吊りリード、６はリード、７は樹脂モー
ルドに必要な樹脂穴である。本発明リードフレームにあ
っては、これら図に例示するように、タブ４．タブ吊り
リード５．及びリード６側面に突出部８を設けて成る。In these figures, 4 is a tab for mounting a semiconductor chip, 5 is a tab suspension lead, 6 is a lead, and 7 is a resin hole necessary for the resin mold. In the lead frame of the present invention, as illustrated in these figures, tab 4. Tab hanging lead 5. A protrusion 8 is provided on the side surface of the lead 6.

この突出部８の形成は、例えば、通常の方法により側面
がフラットに形成されたリードフレームの周端縁から適
宜幅を上下からプレス機械により押圧して当該側面から
突出部が突出するように形成してもよいし、又エツチン
グにより周端縁から適宜幅を上下から適宜の深さでエツ
チング除去することにより形成してもよ（、その他適宜
の方法が採用できる。The protrusion 8 is formed, for example, by pressing an appropriate width from the peripheral edge of a lead frame whose side surface is flat by a normal method using a press machine from above and below, so that the protrusion protrudes from the side surface. Alternatively, it may be formed by etching an appropriate width from the peripheral edge to an appropriate depth from above and below (or any other appropriate method may be employed).

第４図は本発明リードフレームを使用して成る樹脂封止
型半導体装置の断面図を示し、第４図にて、９は半導体
チップ、１０はコネクタワイヤ、１１は樹脂封止体、１
２はリードフレームで半導体チップ９を搭載しているタ
ブ１３、及び半導体チップ９の内部配線をコネクタワイ
ヤ１０を用いて外部に引出するリード１４にはそれぞれ
突出部１５が設けられている。FIG. 4 shows a cross-sectional view of a resin-sealed semiconductor device using the lead frame of the present invention, in which 9 is a semiconductor chip, 10 is a connector wire, 11 is a resin-sealed body, and 1
Reference numeral 2 denotes a lead frame, and a tab 13 on which the semiconductor chip 9 is mounted and a lead 14 for leading out the internal wiring of the semiconductor chip 9 to the outside using a connector wire 10 are each provided with a protrusion 15.

本発明リードフレームは、例えば４２１０イ合金により
構成される。半導体チップ９は、例えばシリコン単結晶
基板より成り、周知の技術によって、このチップ内には
多数の回路素子が形成され、１つの回路機能を与えてい
る。回路素子は例えば絶縁ゲート型電界効果トランジス
タ（ＭＯＳトランジスタ）から成り、これらの回路素子
によって、例えば論理回路およびメモリの回１１！ｒ機
能が形成されている。コネクタワイヤ１０は、例えばア
ルミニウム（ｉ）細線により構成される。The lead frame of the present invention is made of, for example, a 4210 alloy. The semiconductor chip 9 is made of, for example, a silicon single-crystal substrate, and a large number of circuit elements are formed within this chip by well-known techniques to provide one circuit function. The circuit elements consist of, for example, insulated gate field effect transistors (MOS transistors), and these circuit elements enable, for example, logic circuits and memory circuits 11! r function is formed. The connector wire 10 is made of, for example, an aluminum (i) thin wire.

樹脂封止体１１は、例えばエポキシ樹脂により構成され
、周知のトランスファーモールド法などにより形成され
る。次Ｋ、第５図は本発明の他の実施例を示し、第２図
に示すリードフレームのリード６の上面ｋ、さらＫ、適
宜の間隔で横方向に複数の線条の溝部１６を設けて成る
実施例を示す。The resin sealing body 11 is made of, for example, epoxy resin, and is formed by a well-known transfer molding method. 5 shows another embodiment of the present invention, in which a plurality of linear grooves 16 are provided in the horizontal direction at appropriate intervals on the upper surface k and further K of the leads 6 of the lead frame shown in FIG. An example is shown below.

近時、第４図に示すような樹脂封止型半導体装置におい
て、半導体チップ９が大形化し、リード１４の樹脂封止
体１１に埋込まれる長さが次第に短くなりてきている。Recently, in a resin-sealed semiconductor device as shown in FIG. 4, the semiconductor chip 9 has become larger, and the length of the leads 14 embedded in the resin-sealed body 11 has become gradually shorter.

そうすると、リード１４を折曲げて第４図に示すような
折曲げリードとする場合、折曲げ時にリードがゆるみ、
リードがレジンかもスリップし、リードが樹脂封止体外
部によけいに引っばり出されることになる。かかる溝部
１６を設けることにより、より一層、リードフレームと
レジンとの密着性を向上し得る。Then, when the lead 14 is bent to form a bent lead as shown in FIG. 4, the lead becomes loose during bending.
The lead also slips on the resin, and the lead is pulled out to the outside of the resin sealing body. By providing such a groove 16, the adhesion between the lead frame and the resin can be further improved.

〔効　果〕〔effect〕

（１）リードフレームの切断面に段付けを行ない、側面
に突出部を形成するようにしたので、その分リードフレ
ームとレジンとの密着面積が増大し、リードフレームと
レジンの密着性の向上が図られる。(1) The cut surface of the lead frame is stepped and a protrusion is formed on the side surface, which increases the contact area between the lead frame and the resin and improves the adhesion between the lead frame and the resin. It will be planned.

（２）密着面積の増大により、レジン量が増大し、かつ
、側面がフラットである場合に比較して、段が形成され
ているのでリークパスが長くなり、その結果外部からの
半導体装置内部への浸透性異物の侵入が遅くなり封止性
（耐湿性）が向上する。(2) Due to the increased adhesion area, the amount of resin increases, and compared to the case where the side surfaces are flat, the step formation makes the leak path longer, resulting in less leakage from the outside into the inside of the semiconductor device. The intrusion of penetrating foreign substances is slowed down and sealing performance (moisture resistance) is improved.

（３）　リードフレームとレジンとの密着性、封止性の
向上により製品寿命を蔦命し、樹脂封止型半導体装置の
信頼性を著しく向上することができる。(3) The product life can be extended by improving the adhesion and sealing performance between the lead frame and the resin, and the reliability of the resin-sealed semiconductor device can be significantly improved.

（４）半導体チップが大型化し、リードのモールドレジ
ン中へ埋め込まれている部分が増々短くなっている今日
、リードフレームに段付けを行い、リードフレームとレ
ジンとの密層性の向上の図り、封止性を向上し、半導体
装置の信頼性を向上し得ることは工業上極め【有意義で
ある。(4) Nowadays, semiconductor chips are becoming larger and the portion of the lead embedded in the mold resin is becoming shorter and shorter, so the lead frame is stepped to improve the closeness between the lead frame and the resin. The ability to improve sealing performance and the reliability of semiconductor devices is of great industrial significance.

（５）　リードフレームの側面に突出部を設けることに
加えて、第５図に示すように、リードの上面に溝部を形
成することＫより、より一層リードフレームとレジンと
の密着性が向上させることができ、さらにリード折曲げ
成影に際し、リードがゆるんだり、樹脂封止体の外部に
突出したりすることを防止できる。(5) In addition to providing a protrusion on the side surface of the lead frame, forming a groove on the top surface of the lead as shown in Figure 5 further improves the adhesion between the lead frame and the resin. Furthermore, it is possible to prevent the leads from loosening or protruding outside the resin sealing body during lead bending and imaging.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨は逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, the present invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist thereof). Not even.

例えば、前記実施例では、リードフレーム側面全体に突
出部を設けた例を示したが、一部に突出部を設けても差
支えない。又前記実施例では溝部をリード上面のみに設
けた例を示したが、リードの上下面あるいは、下面のみ
に設けてもよい。For example, in the embodiment described above, the protrusion was provided on the entire side surface of the lead frame, but the protrusion may be provided on a portion of the lead frame. Further, in the above embodiment, an example was shown in which the groove portion was provided only on the upper surface of the lead, but it may be provided only on the upper and lower surfaces or the lower surface of the lead.

〔利用分野〕[Application field]

本発明はデニアルインライン（ＤＩＬ）タイプのパッケ
ージの他、フラットパックタイプのパッケージなど他の
樹脂封止型半導体装置にも適用することができ、樹脂封
止型半導体装置全般に適用できる。The present invention can be applied not only to denial in-line (DIL) type packages but also to other resin-sealed semiconductor devices such as flat-pack type packages, and can be applied to resin-sealed semiconductor devices in general.

又電子部品のパッケージ技術にも適用できる。It can also be applied to electronic component packaging technology.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はリードフレームの従来例を示す平面図、第２図
株本発明リードフレームの要部斜視図、第３図は第２図
Ｉ−Ｉ線断面図、 第４図は本発明リードフレームを使用して成る樹脂封止
型半導体装置の断面図、 第５図は本発明の他の実施例を示すリードフレームの平
面図である。 １・・・タブ、２・・・タブ吊りリード、３・・・リー
ド、４・・・タブ、５・・・タブ吊りリード、６・・・
リード、７・・・樹脂穴、８・・・突出部、９・・・半
導体チップ、１０・・・コネクタワイヤ、１１・・・樹
脂封止体、１２・・・リードフレーム、１３・・・タブ
、１４・・・リード、１５・・・突出部、１６・・・溝
部。 第１図 ／Fig. 1 is a plan view showing a conventional example of a lead frame, Fig. 2 is a perspective view of essential parts of the lead frame of the present invention, Fig. 3 is a sectional view taken along line I-I in Fig. 2, and Fig. 4 is a lead frame of the present invention. FIG. 5 is a plan view of a lead frame showing another embodiment of the present invention. 1...Tab, 2...Tab suspension lead, 3...Lead, 4...Tab, 5...Tab suspension lead, 6...
Lead, 7...Resin hole, 8...Protrusion, 9...Semiconductor chip, 10...Connector wire, 11...Resin sealing body, 12...Lead frame, 13... Tab, 14...Lead, 15...Protrusion, 16...Groove. Figure 1/

Claims (1)

【特許請求の範囲】 １、−面に突出部を設けて成ることを特徴とするリード
フレーム。 ２、前記リードフレームがプラスチックモールド用リー
ドフレームである、特許請求の範囲第１項記載のリード
フレーム。[Claims] 1. A lead frame characterized in that a protrusion is provided on the - side. 2. The lead frame according to claim 1, wherein the lead frame is a lead frame for plastic molding.
JP59050939A 1984-03-19 1984-03-19 Lead frame Pending JPS60195957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59050939A JPS60195957A (en) 1984-03-19 1984-03-19 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59050939A JPS60195957A (en) 1984-03-19 1984-03-19 Lead frame

Publications (1)

Publication Number Publication Date
JPS60195957A true JPS60195957A (en) 1985-10-04

Family

ID=12872790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59050939A Pending JPS60195957A (en) 1984-03-19 1984-03-19 Lead frame

Country Status (1)

Country Link
JP (1) JPS60195957A (en)

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EP0989608A3 (en) * 1998-09-21 2001-01-10 Amkor Technology Inc. Plastic integrated circuit device package and method of making the same
JP2002181226A (en) * 2000-10-25 2002-06-26 Behr Thermot-Tronik Gmbh Control valve
US6433277B1 (en) 1998-06-24 2002-08-13 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6448633B1 (en) 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
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US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
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US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
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US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
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US6630728B2 (en) 1998-06-24 2003-10-07 Amkor Technology, Inc. Plastic integrated circuit package and leadframe for making the package
US6433277B1 (en) 1998-06-24 2002-08-13 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6684496B2 (en) 1998-06-24 2004-02-03 Amkor Technology, Inc. Method of making an integrated circuit package
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US6455356B1 (en) 1998-10-21 2002-09-24 Amkor Technology Methods for moding a leadframe in plastic integrated circuit devices
US6521987B1 (en) 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
US6825062B2 (en) 1998-11-20 2004-11-30 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
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US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
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JP2002181226A (en) * 2000-10-25 2002-06-26 Behr Thermot-Tronik Gmbh Control valve
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
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US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
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US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
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US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
US11869829B2 (en) 2009-01-05 2024-01-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with through-mold via
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US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
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