JPS60192553U - frequency conversion circuit - Google Patents
frequency conversion circuitInfo
- Publication number
- JPS60192553U JPS60192553U JP5804385U JP5804385U JPS60192553U JP S60192553 U JPS60192553 U JP S60192553U JP 5804385 U JP5804385 U JP 5804385U JP 5804385 U JP5804385 U JP 5804385U JP S60192553 U JPS60192553 U JP S60192553U
- Authority
- JP
- Japan
- Prior art keywords
- output
- pulse
- pulses
- frequency
- rate multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Measuring Frequencies, Analyzing Spectra (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のフェーズロックループによる周波数変換
回路を示す図、第２図は本考案の周波数変換回路の概要
を示す系統図、第３図は第２図に示したものの具体的な
回路を示す回路図、第４、図はＲＣ積分回路を示す図、
第５図は第３図におけ−１る回路のシュミレーション結
果を示す図である。
−図において゛、１１：ディジタル微分回路、１２：周
波数比較器、１３：Ｍ進アップダウンカウンタ、１４：
タイミング作成回路、１５：Ｍ進し−トマルチプライヤ
、１６：ローパスフィルタ、１７：可変抵抗器、（Ｎ）
３１：入カパルス数信 −４、ｓ２：入力少ロックパ
ルス 、Ｓ３：出力アナログ信号、Ｓ４−′：出力デイ
ジタル信号、Ｆｌ、Ｆ２：フリ 。
ツブフロップ、Ａ、：、ＡＮＤゲート、１１：インバー
タ、Ｆ３．Ｆ４：フリップフロップ、Ａ１〜Ａ４：ＡＮ
Ｄゲート、Ｃ１：Ｍ進アップダウン力つシタ、Ｆ５：フ
リップフロップ、Ａ６．Ａ７：Ｒのゲート、Ｒ１：Ｍ進
し−トマルチプライヤ、ＬＰＦ：ローパスフィルタ、Ｖ
Ｒ：可変抵抗器。尚、図中同一符号は同−或いは相当部
分を示す。Fig. 1 is a diagram showing a frequency conversion circuit using a conventional phase-locked loop, Fig. 2 is a system diagram showing an overview of the frequency conversion circuit of the present invention, and Fig. 3 is a diagram showing a specific circuit of the one shown in Fig. 2. The circuit diagram shown in FIG. 4 is a diagram showing an RC integration circuit.
FIG. 5 is a diagram showing a simulation result of the circuit labeled -1 in FIG. 3. - In the figure, 11: Digital differentiation circuit, 12: Frequency comparator, 13: M-ary up/down counter, 14:
Timing generation circuit, 15: M-adic multiplier, 16: Low-pass filter, 17: Variable resistor, (N)
31: Input pulse number signal -4, s2: Input low lock pulse, S3: Output analog signal, S4-': Output digital signal, Fl, F2: Free. Tubu flop, A,:, AND gate, 11: Inverter, F3. F4: Flip-flop, A1-A4: AN
D gate, C1: M-adic up/down force, F5: flip-flop, A6. A7: R gate, R1: M-adic multiplier, LPF: low pass filter, V
R: variable resistor. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
る第１の入力クロック パルスによりサンプルする微分回路と、この微分回路の
出力が入力される周波数比較器と、この周波数比較器の
出力パルスを計数するアップダウンカウンタと、第２の
入力クロッ、クパルスを受は上記カウンタの計数値に比
例した周期のパルスを発生スるレートマルチプライヤと
を備え、上記周波数比較器にて上記レートマルチプライ
ヤの出力パルスと上記微分回路の出力とのパルス数を比
較り、その比較結果に応じて上記アップダウンカウンタ
の計数値を増減することにより上記出力パル′ −ス数
信号の周波数に対応した大きさのディジタル変換出力お
よび上記レートマルチプライヤの出力パルスをＣＲ積分
することによりアナログ変換出力を発生せしめるように
構成したことを特徴とする周波数変換回路。[Claims for Utility Model Registration] A differentiator circuit that samples an input pulse number signal with a pulse rate H using a first input clock pulse whose curvature is F; a frequency comparator to which the output of the differentiator circuit is input; The frequency comparator includes an up/down counter that counts output pulses of the frequency comparator, a second input clock, and a rate multiplier that receives the clock pulses and generates pulses with a period proportional to the counted value of the counter. The number of output pulses of the rate multiplier and the output of the differentiating circuit are compared in a device, and the count value of the up/down counter is increased or decreased according to the comparison result, thereby generating the output pulse ' - pulse number signal. 1. A frequency conversion circuit configured to generate an analog conversion output by performing CR integration of a digital conversion output having a magnitude corresponding to the frequency of the rate multiplier and the output pulse of the rate multiplier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5804385U JPS60192553U (en) | 1985-04-16 | 1985-04-16 | frequency conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5804385U JPS60192553U (en) | 1985-04-16 | 1985-04-16 | frequency conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60192553U true JPS60192553U (en) | 1985-12-20 |
| JPS6319808Y2 JPS6319808Y2 (en) | 1988-06-02 |
Family
ID=30583163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5804385U Granted JPS60192553U (en) | 1985-04-16 | 1985-04-16 | frequency conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192553U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4417075Y1 (en) * | 1965-12-11 | 1969-07-23 | ||
| JPS5392174A (en) * | 1977-01-25 | 1978-08-12 | Toshiba Corp | Digital frequency converter |
-
1985
- 1985-04-16 JP JP5804385U patent/JPS60192553U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4417075Y1 (en) * | 1965-12-11 | 1969-07-23 | ||
| JPS5392174A (en) * | 1977-01-25 | 1978-08-12 | Toshiba Corp | Digital frequency converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6319808Y2 (en) | 1988-06-02 |
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