JPS6018949A - Semiconductor voltage control resistor - Google Patents

Semiconductor voltage control resistor

Info

Publication number
JPS6018949A
JPS6018949A JP12604083A JP12604083A JPS6018949A JP S6018949 A JPS6018949 A JP S6018949A JP 12604083 A JP12604083 A JP 12604083A JP 12604083 A JP12604083 A JP 12604083A JP S6018949 A JPS6018949 A JP S6018949A
Authority
JP
Japan
Prior art keywords
resistor
voltage control
vcr
semiconductor
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12604083A
Other languages
Japanese (ja)
Inventor
Makoto Ishikawa
誠 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12604083A priority Critical patent/JPS6018949A/en
Publication of JPS6018949A publication Critical patent/JPS6018949A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0738Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with resistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To miniaturize a voltage control resisltor and reduce its cost by constituting the voltage control resistor by integrally combining a diffusion resistor and a MOS element. CONSTITUTION:A diffusion resistor 2 consisting of an N type diffusion layer is formed on the surface of a P type semiconductor base body 1. The resistor 2 is formed as a ?-shaped pattern in which one parts run parallel and are opposed and other sections continue, and Al electrodes 3a, 3b are shaped at both end sections of the resistor 2. A gate electrode 4 is formed on the surface of the base body 1 between these opposite resistor 2 through an insulating film 5. That is, the section constitutes an N channel MOSFET having the electrode 4 while using the layers 2, 2 as a source and a drain, and a voltage control resistor VCR composed of one element in which the diffusion resistor and the MOSFET shown in an equivalent circuit figure are combined integrally is constituted as a whole. According to the constitution, since the VCR can be constituted by one element, the area of a chip can be reduced, and the cost of the VCR can be lowered.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置1%に半導体基体表面の拡散抵抗と
金属酸化物半導体(MOS)構造を利用した電圧制御抵
抗(VCR)装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a voltage controlled resistor (VCR) device that utilizes a diffusion resistance on the surface of a semiconductor substrate and a metal oxide semiconductor (MOS) structure in a semiconductor device.

〔背景技術〕[Background technology]

電子回路においてVCRを構成する場合1例えば抵抗と
トランジスタ等を一つの回路に組合せたドルビーIC(
半導体集積回路)が知られているが、素子数が多く構造
も複雑・でチップ面積も大きくならざるを得ない。
When configuring a VCR in an electronic circuit 1 For example, Dolby IC (which combines resistors, transistors, etc. into one circuit)
Semiconductor integrated circuits (Semiconductor integrated circuits) are well known, but they have a large number of elements, a complex structure, and a large chip area.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体拡散抵抗とMO8構造とを一体化
した一つの複合素子からなり、小型化。
The purpose of the present invention is to form a single composite element that integrates a semiconductor diffused resistor and an MO8 structure, and to miniaturize it.

低価格化できる半導体VORな提供することにある。The aim is to provide a semiconductor VOR that can be lowered in price.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に、説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体の一主表面に一部で平行して対向し他
部で連続する拡散抵抗が形成され、対向する拡散抵抗間
の半導体表面に絶縁膜を介してゲートが形成され、この
ゲートへの電圧印加によって拡散抵抗を制御する一体化
した一つの複合素子からなる半導体VCRを構成するも
のである。
That is, diffused resistors are formed on one main surface of a semiconductor, parallel to each other in some parts and continuous in other parts, and a gate is formed on the semiconductor surface between the opposing diffused resistors with an insulating film interposed therebetween. This constitutes a semiconductor VCR consisting of one integrated composite element that controls diffusion resistance by applying voltage.

〔実施例〕〔Example〕

第1図は本発明の一実施例であって半導体拡散抵抗とM
O8構造とを一体に組合せて一累子としたVCR装置の
平面図であり、第2図は第1図におけるA −A’切断
断面図である。
FIG. 1 shows an embodiment of the present invention, in which a semiconductor diffused resistor and M
FIG. 2 is a plan view of a VCR device in which the O8 structure is integrated into a unit; FIG. 2 is a cross-sectional view taken along the line A-A' in FIG. 1;

1は半導体基体1例えばp型Si(シリコン)基体、2
は基体1表面に形成したn型拡赦層からなる拡散抵抗で
ある。この拡散抵抗は一部で平行して対向し、他部で連
続するコ字形パターンとして形成され、その両端部にコ
ンタクトするアルミニウム電極3a、3bが設けられる
。4はアルミニウム等からなるゲート電極で対向する拡
散抵抗間の半導体表面上に絶縁膜(S r 02膜)5
を介して設けられる。すなわちこの部分はn型拡散層2
゜2をソース・ドレインとし、絶縁ゲート電極4を有す
るnチャネルMO8FET(を界効果トランジスタ)を
構成するものであり、全体としては第3図に等価回路図
で示す拡散抵抗とMOSFETとを一体に組合せたー素
子からなるVCRを構成する。
1 is a semiconductor substrate 1, for example, a p-type Si (silicon) substrate; 2
is a diffused resistor consisting of an n-type ambiguous layer formed on the surface of the substrate 1. This diffused resistor is formed as a U-shaped pattern that faces parallel in some parts and continues in other parts, and aluminum electrodes 3a and 3b are provided in contact with both ends thereof. 4 is a gate electrode made of aluminum or the like, and an insulating film (S r 02 film) 5 is formed on the semiconductor surface between the opposing diffused resistors.
provided through. In other words, this part is the n-type diffusion layer 2
゜ constitutes an n-channel MO8FET (field effect transistor) having a source and drain and an insulated gate electrode 4, and as a whole, the diffused resistor and MOSFET shown in the equivalent circuit diagram in Fig. 3 are integrated. A VCR is constructed from a combination of elements.

このような半導体装置のVCRとしての動作は下記のよ
うにして行われる。
The operation of such a semiconductor device as a VCR is performed as follows.

(1)電極3aをVD、電極3bを接地側(GND)に
接続し、ゲートへの印加電圧VG=0とした場合。
(1) When the electrode 3a is connected to VD, the electrode 3b is connected to the ground side (GND), and the voltage applied to the gate is set to VG=0.

拡散抵抗の抵抗値は■−■−■−■−■の間の直列抵抗
(R+ 十R2+R3+R4+R5+Ra+ R))と
これと並列の抵抗R6=R?とによってあられされる。
The resistance value of the diffused resistor is the series resistance between ■-■-■-■-■ (R+ 1R2+R3+R4+R5+Ra+R)) and the parallel resistance R6=R? It will come by.

しかし、V、=Oであるため、R,、R。However, since V,=O,R,,R.

は無限大の大きさであるから、結果として抵抗値は、R
I+R2+R3+R4+FLs 十Re+R7で表わさ
れる。
has an infinite size, so the resistance value is R
I+R2+R3+R4+FLs Represented by 10Re+R7.

(2)次に■。を印加すると、第3図を参照し、R1゜
Rt * Rs + R4+丁t+、R6,几、が等し
い値Rとし。
(2) Next ■. Referring to FIG. 3, when R1°Rt*Rs+R4+T+, R6, is set to the same value R.

回路を流れる電流を1としたとき、■−■間の電位差は
51Rであり、■−■間の電位差は3IRとなる。■−
■間のMOS)ランジスタと■−■間のMOS)ランジ
スタがオンの状態となり、R6゜Roは有限の値を持つ
。■−■間の電位差が■−■間の電位差より大きいので
■−■間に流れる電流は、■−■間に流れる電流より太
きいつつまり、R8はRoより小さくなる。結果として
抵抗値は。
When the current flowing through the circuit is 1, the potential difference between ■ and ■ is 51R, and the potential difference between ■ and ■ is 3IR. ■−
The MOS) transistor between (2) and the MOS) transistor between (2) and (2) are turned on, and R6°Ro has a finite value. Since the potential difference between ■ and ■ is larger than the potential difference between ■ and ■, the current flowing between ■ and ■ is thicker than the current flowing between ■ and ■, which means that R8 becomes smaller than Ro. As a result, the resistance value is.

第3図においてMOSトランジスタQ、、Q2をR,、
R1+でおきかえた回路の全抵抗値となる。
In FIG. 3, MOS transistors Q, , Q2 are R, ,
This is the total resistance value of the circuit replaced with R1+.

R31Voをさらに大きくするとRs 、Roが(2)
のRs 、RoO値より小さくなり1回路全体の抵抗は
、(21時の回路の全抵抗より小さな値となる。実際に
は■DDとGNDとの間には、無数のMOS)ランジス
タが形成されていると考えられ、voへの印加電圧によ
り、これらのMOS)ランジスタにチャネルを発生させ
電流を流すことにより抵抗値を任意に制御lal]する
ことができる。
If R31Vo is further increased, Rs and Ro become (2)
Rs of , becomes smaller than the RoO value, and the resistance of the entire circuit becomes a value smaller than the total resistance of the circuit at 21:00.In reality, countless MOS transistors are formed between DD and GND. The resistance value can be arbitrarily controlled by generating a channel in these MOS transistors and flowing a current by applying a voltage to vo.

〔効 果〕〔effect〕

以上実施例で述べた本発明によれば、拡散抵抗とMO8
i子とを一体に組合せることによって1紫子でVCRを
構成できるから、従来の抵抗、トランジスタを組合せた
複雑な回路に比して単純化でき、チップ面積も縮小化で
き、低価格で提供できる効果を有する。
According to the present invention described in the embodiments above, the diffusion resistance and the MO8
Since a VCR can be configured with one zigzag by combining it with an i-chip, it can be simplified compared to the conventional complex circuit that combines resistors and transistors, the chip area can be reduced, and it can be provided at a low price. It has the effect of

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが1本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、拡散抵抗の
形状なコ字状とする以外に第4図に示すようにループ状
に形成してもよい。
Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, instead of forming the diffused resistor in a U-shape, it may be formed in a loop shape as shown in FIG.

〔利用分野〕[Application field]

本発明はVCHを使用する半導体装置に適用することが
でき、特にバイポ〜うMOSプロセスにより製造するI
C,LSIにそのま工に応用することができる。
The present invention can be applied to semiconductor devices using VCH, and especially I
It can be applied to C, LSI as is.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による一実施例であって、半導体拡散層
とMO3素子とを一体に組合せたVCHの平面図。 第2図は第1図におけるA−A’視断面図。 第3図はその等価回路図である。 第4図は本発明による他の一実施例であるVCRの平面
図である。 1・・・p型Si基体、2・・・n型拡散抵抗、3a、
3b・・・電極、4・・・ゲート、5・・・絶縁膜。 第 1 図 Aコ 、q/− 第 2 図 第 3 図 第 4 図
FIG. 1 is a plan view of a VCH according to an embodiment of the present invention, in which a semiconductor diffusion layer and an MO3 element are integrally combined. FIG. 2 is a sectional view taken along line AA' in FIG. FIG. 3 is its equivalent circuit diagram. FIG. 4 is a plan view of a VCR which is another embodiment of the present invention. 1...p-type Si substrate, 2...n-type diffused resistance, 3a,
3b...electrode, 4...gate, 5...insulating film. Figure 1 A, q/- Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基体の一主表面に一部で平行して対向し、他
部で連続する拡散抵抗が形成され、対向する拡散抵抗間
の半導体表面に絶縁膜を介してゲートが形成され、上記
ゲートへの電圧印加によって拡散抵抗を制aII+する
ことを特徴とする半導体電圧制御抵抗装置。
1. Diffused resistors are formed on one main surface of a semiconductor substrate, parallel to each other in some parts and continuous in other parts, and a gate is formed on the semiconductor surface between the opposing diffused resistors with an insulating film interposed therebetween. A semiconductor voltage-controlled resistance device characterized in that diffusion resistance is controlled by applying a voltage to aII+.
JP12604083A 1983-07-13 1983-07-13 Semiconductor voltage control resistor Pending JPS6018949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12604083A JPS6018949A (en) 1983-07-13 1983-07-13 Semiconductor voltage control resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12604083A JPS6018949A (en) 1983-07-13 1983-07-13 Semiconductor voltage control resistor

Publications (1)

Publication Number Publication Date
JPS6018949A true JPS6018949A (en) 1985-01-31

Family

ID=14925171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12604083A Pending JPS6018949A (en) 1983-07-13 1983-07-13 Semiconductor voltage control resistor

Country Status (1)

Country Link
JP (1) JPS6018949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003026194A (en) * 2001-07-09 2003-01-29 Kau Pack Kk Packaging bag with string and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003026194A (en) * 2001-07-09 2003-01-29 Kau Pack Kk Packaging bag with string and manufacturing method therefor

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