JPS60187063A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60187063A JPS60187063A JP4353684A JP4353684A JPS60187063A JP S60187063 A JPS60187063 A JP S60187063A JP 4353684 A JP4353684 A JP 4353684A JP 4353684 A JP4353684 A JP 4353684A JP S60187063 A JPS60187063 A JP S60187063A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- junctions
- junction
- conductivity type
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 40
- 230000005684 electric field Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は半導体装置に関し、詳しくはスイッチング素子
として使用されるＰＮ接合型シリコン・ダイオード等の
ＰＮ接合をもつ半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a PN junction such as a PN junction type silicon diode used as a switching element.
口、従来技術
従来の半導体装置、例えばＰＮ接合型シリコン・ダイオ
ードの具体例を第１図に示し説明する。同図に於いて、
（１）は比較的高濃度で低抵抗のシリコン単結晶からな
るＮ＋型サブストレート（以下単にＮ＋層と称す）、（
２）は比較的低濃度で高抵抗のＮ−型車結晶エビタキシ
ャル層（以下単にＮ一層と称す）で、このＮ一層（２）
を上記Ｎ 層（１）上に成長させて形成する。（３）は
上記Ｎ一層（２）上に形成した５ｉ０２の酸化膜で、こ
の酸化膜（３）の所定箇所をフォトエツチング法により
除去して窓孔（４）を選択的に形成する。（５）は上記
酸化膜（３）の窓孔（４）からＮ一層（２）にボロン等
のＰ型不純物を選択拡散して形成したＰ型不純物拡散領
域（以下単にＰ層と称す）で、このＰ層（５）と上記Ｎ
〜層（２）間にＰＮ接合（６）を形成する。（７）は上
記酸化膜（３）の窓孔（４）位置に形成されたＰ層（５
）上にアルミニウム蒸着等により被着した表面電極層、
（８）は前記Ｎ 層（１）の下面に形成した裏面電極層
である。1. Prior Art A specific example of a conventional semiconductor device, for example a PN junction type silicon diode, is shown in FIG. 1 and will be described. In the same figure,
(1) is an N+ type substrate (hereinafter simply referred to as the N+ layer) made of silicon single crystal with relatively high concentration and low resistance;
2) is a relatively low concentration, high resistance N-type car crystal epitaxial layer (hereinafter simply referred to as the N layer);
is grown on the N layer (1). (3) is a 5i02 oxide film formed on the N single layer (2), and predetermined portions of this oxide film (3) are removed by photoetching to selectively form windows (4). (5) is a P-type impurity diffusion region (hereinafter simply referred to as P layer) formed by selectively diffusing P-type impurities such as boron into the N layer (2) from the window hole (4) of the oxide film (3). , this P layer (5) and the above N
- Forming a PN junction (6) between layers (2). (7) is a P layer (5) formed at the window hole (4) position of the oxide film (3).
) a surface electrode layer deposited by aluminum vapor deposition, etc.
(8) is a back electrode layer formed on the lower surface of the N layer (1).
第２図に示すように上記表面電極層（７）と裏面電極Ｎ
（８）間で順バイアス電圧を印加すると、Ｐ層（５）か
らＮ一層（２）及びＮ＋層（１）に電流が流れるが、そ
の通電開始時の電流値が小さい段階では図示破線（ａ）
で示すようにＰＮ接合（６）の略全面から均等に電流が
流れる。上記通電を継続して電流値が大きい段階に達す
ると、第３図破線（ｂ）で示すようにＰＮ接合（６）の
周縁部（６”）では電流が流れ易く、その中央部（６１
）では電流が流れ難くなって上記周縁部（６゛）に電流
が集中する。これは高抵抗のＮ一層（２）が抵抗骨とし
て上記電極Ｆｉ （７） （８）間に介在し、そのＮ一
層（２）の各部分の抵抗値のバラツキや該Ｎ一層（２）
を移動する電子同士での反撥等の原因により生ずるもの
であると考えられている。この電流分布の不均等により
極端な場合、実質上の電流経路が上記ＰＮ接合（６）の
周縁部（６°）のみに減少し、延いてはこの周縁部（６
′）への電流の集中によってＰＮ接合（６）を破壊する
虞があった。上述のように順バイアス電圧を印加した際
、電流値が大きい領域でその電流分布が不均等になると
、第４図に破線（Ａ）で示すような理想的な順方向特性
（ＶＦ 特性）が得られず、図示実線（Ｂ）で示すよう
に順方向特性が低下するという問題点があった。また第
１図に示す表面電極層（７）と裏面電極層（８）間で逆
バイアス電圧を印加すると、ＰＮ接合（６）の隅部（６
”’）が曲率半径 の小さい曲面となっているため、こ
の部分（６”゛）に電界が集中する。As shown in FIG. 2, the front electrode layer (7) and the back electrode N
(8), current flows from the P layer (5) to the N layer (2) and the N+ layer (1), but at the stage where the current value at the start of the current flow is small, the dashed line (a) )
As shown, current flows uniformly from substantially the entire surface of the PN junction (6). When the above-mentioned current supply continues and the current value reaches a large stage, as shown by the broken line (b) in FIG.
), it becomes difficult for the current to flow and the current is concentrated at the peripheral edge (6°). This is because a high-resistance N layer (2) is interposed between the electrodes Fi (7) and (8) as a resistance bone, and the resistance value of each part of the N layer (2) varies and the N layer (2)
It is thought that this phenomenon occurs due to factors such as repulsion between moving electrons. In an extreme case due to this uneven current distribution, the actual current path is reduced to only the periphery (6°) of the PN junction (6), and eventually this periphery (6°)
There was a risk that the PN junction (6) would be destroyed due to concentration of current in the PN junction (6). As mentioned above, when applying a forward bias voltage, if the current distribution becomes uneven in the region where the current value is large, the ideal forward characteristic (VF characteristic) as shown by the broken line (A) in Figure 4 will change. However, as shown by the solid line (B) in the figure, there was a problem in that the forward direction characteristics deteriorated. Furthermore, when a reverse bias voltage is applied between the front electrode layer (7) and the back electrode layer (8) shown in FIG.
Since ``'') is a curved surface with a small radius of curvature, the electric field is concentrated on this part (6'').
即ち、このＰＮ接合（６）の隅部（６°゛）からＮ一層
（２）に対して広がる電界の電位傾度が大きく、空乏層
が形成されにくいためにＰＮ接合（６）が破壊され易く
耐圧の低下を免れ得ないという問題点もあった。In other words, the potential gradient of the electric field that spreads from the corner (6°) of this PN junction (6) to the N layer (2) is large, making it difficult to form a depletion layer, making it easy for the PN junction (6) to be destroyed. There was also the problem that a drop in withstand pressure could not be avoided.
ハ０発明の目的
本発明は上記問題点に鑑み提案されたもので、順方向特
性の改善並びに耐圧の向上を容易に可能ならしめる半導
体装置を提供することを目的とする。OBJECTS OF THE INVENTION The present invention has been proposed in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device that can easily improve forward characteristics and breakdown voltage.
二２発明の構成
本発明は一導電型基板に、アイランド状に分割して形成
した複数の第１の他導電型の不純物拡散領域と、上記第
１の他導電型不純物拡散領域を離隔して囲繞しかつこの
第１の他導電型不純物拡散領域よりも深く形成した第２
の他導電型不純物拡散領域と、上記第１の他導電型不純
物拡散領域間及び第１、第２の両地導電型不純物拡散領
域を連結するように前記第１の他導電型不純物拡散領域
よりも浅く形成した第３の他導電型不純物拡散領域とを
設けたものである。22 Structure of the Invention The present invention provides a plurality of first impurity diffusion regions of a different conductivity type which are divided and formed into islands on a substrate of one conductivity type, and the first impurity diffusion regions of the other conductivity type are separated from each other. A second region surrounding the region and formed deeper than the first impurity diffusion region of a different conductivity type.
from the first other conductivity type impurity diffusion region so as to connect the other conductivity type impurity diffusion region and the first other conductivity type impurity diffusion region and the first and second double conductivity type impurity diffusion regions. A third impurity diffusion region of another conductivity type is also formed shallowly.
ホ、実施例
以下に本発明に係る半導体装置の一実施例を第５図に示
し説明する。この実施例はＰＮ接合型ダイオードへの適
用例であり、第１図と同一符号は同一物を示しその説明
を省略する。同図に於いて、（９ａ） （９ｂ） （９
ｃ）はＮ−１（２）にボロン等のＰ全不純物を選択拡散
して形成した第１〜第３のＰ全不純物拡散領域（以下単
に第１〜第３のＰ層と称す）で、この第１〜第３のＰ層
（９ａ） （９ｂ） （９ｃ）と上記Ｎ一層（２）間に
第１〜第３のＰＮ接合（１０ａ） （１０ｂ）（１０Ｃ
）を形成する。この第１のＰＪｉｉ（９ａ）は上記Ｎ一
層（２）のＰＮ接合形成予定部でアイランド状に複数分
割して拡散形成する。また第２のＰ層（９ｂ）は上記Ｐ
Ｎ接合形成予定部の周縁部で第１のＰ層（９ａ）を囲繞
するように深く拡散形成する。更に第３のＰ層（９Ｃ）
は上記第１のＰ層（９ａ）同士及び第１のＰ層（９ａ）
と第２のＰ層（９ｂ）を連結するように薄膜状に拡散形
成する。これら第１〜第３のＰ層（９ａ） （９ｂ）（
９ｃ）は３回の拡散により形成される。尚、上記第２の
Ｐ層（９ｂ）の上面には、後述するように順バイアス電
圧印加時、この部分に電流が集中しないように酸化膜（
３）が被着されている。E. Example An example of a semiconductor device according to the present invention is shown in FIG. 5 and will be described below. This embodiment is an example of application to a PN junction diode, and the same reference numerals as in FIG. 1 indicate the same components, and the explanation thereof will be omitted. In the same figure, (9a) (9b) (9
c) is the first to third all-P impurity diffusion regions (hereinafter simply referred to as first to third P layers) formed by selectively diffusing all-P impurities such as boron into N-1(2); The first to third PN junctions (10a) (10b) (10C
) to form. The first PJii (9a) is divided into a plurality of islands and diffused in the portion where the PN junction is to be formed in the N layer (2). In addition, the second P layer (9b) is the above-mentioned P layer (9b).
The first P layer (9a) is deeply diffused and formed so as to surround the peripheral edge of the portion where the N junction is to be formed. Furthermore, the third P layer (9C)
is the first P layer (9a) and the first P layer (9a)
and the second P layer (9b) are formed by diffusion in a thin film shape so as to connect the second P layer (9b). These first to third P layers (9a) (9b) (
9c) is formed by three diffusions. Furthermore, as will be described later, an oxide film (
3) is coated.
第６図に示すように表面電極層く７）と裏面を極Ｆｔｉ
（８）間で順バイアス電圧を印加すると、その通電開始
後電流値が大きい領域では図示破線（Ｃ）で示すように
第１、第３のＰＮ接合（１０ａ）（１０ｃ）から均等に
電流が流れる。これは上記第１のＰＮ接合（１０ａ）を
アイランド状に複数分割して形成しているので、各第１
のＰＮ接合（１０ａ）での電流分布が均等になるため、
全体的に第１、第３のＰＮ接合（１０ａ）（１０ｃ）で
の電流分布は均等となる。この全体的なＰＮ接合の面積
も従来と比較して拡張され、実質上の電流経路が拡大さ
れる。尚、第２のＰ層（９ｂ）には酸化膜（３）が被着
されているため、第２のＰＮ接合（１０ｂ ）から流れ
る電流は可能な限り抑止され、この部分での電流の集中
を防止する。As shown in Figure 6, the front electrode layer 7) and the back surface are
(8) When a forward bias voltage is applied between the first and third PN junctions (10a) and (10c), in the region where the current value is large after the start of current flow, the current is uniformly distributed from the first and third PN junctions (10a) and (10c) as shown by the broken line (C) in the figure. flows. This is because the first PN junction (10a) is divided into multiple islands, so each first PN junction (10a)
Since the current distribution at the PN junction (10a) becomes equal,
Overall, the current distribution in the first and third PN junctions (10a) (10c) becomes equal. The overall area of the PN junction is also expanded compared to the conventional one, and the substantial current path is expanded. Furthermore, since the second P layer (9b) is coated with an oxide film (3), the current flowing from the second PN junction (10b) is suppressed as much as possible, and current concentration in this part is prevented. prevent.
上記第２のＰＮ接合（１０ｂ）は、第１、第３のＰＮ接
合（１０ａ）（１０ｃ）よりも深い位置まで拡散形成さ
れているため、前記表面電極層（７）と裏面電極層（８
）間に逆バイアス電圧を印加した際に、ＰＮ接合の破壊
を防止し、耐圧の向上を図る。即ち、上記第２のＰＮ接
合（１０ｂ ）の隅部（１０ｂ’）が曲率半径の大きい
曲面となっているため、電位傾度が小さくなってＮ 層
（２）に対して広がる電界が緩やかな分布を示し、この
部分（１０ｂ”）に電界が集中しない。この結果空乏層
が形成され易く、ＰＮ接合の破壊防止及び耐圧の向上が
可能となる。The second PN junction (10b) is formed by diffusion to a deeper position than the first and third PN junctions (10a) and (10c), so the front electrode layer (7) and the back electrode layer (8
) When a reverse bias voltage is applied between the two electrodes, the PN junction is prevented from being destroyed and the withstand voltage is improved. That is, since the corner (10b') of the second PN junction (10b) is a curved surface with a large radius of curvature, the potential gradient becomes small and the electric field spreading toward the N layer (2) has a gentle distribution. , and the electric field is not concentrated in this portion (10b'').As a result, a depletion layer is easily formed, making it possible to prevent destruction of the PN junction and improve the withstand voltage.
尚、上記実施例ではＰＮ接合型シリコン・ダイオードに
ついて説明したが、本発明はＰＮ接合をもつ半導体装置
の全てに適用可能であることは勿論である。また、第１
、第２、第３の不純物拡散領域は、ＰＮ接合形成予定部
と異なるＰ型又はＮ型のいずれの場合でもよい。Incidentally, in the above embodiment, a PN junction type silicon diode was explained, but it goes without saying that the present invention is applicable to all semiconductor devices having a PN junction. Also, the first
The second and third impurity diffusion regions may be of either P type or N type, which is different from the PN junction formation area.
へ０発明の効果
本発明によれば、ＰＮ接合を複数分割したことにより順
バイアス電圧を印加した際に、上記ＰＮ接合での電流分
布が均等となり、実質上の電流経路が拡大されて順方向
特性が改善される。また上記電流分布の均等によりＰＮ
接合の一部に電界が集中することなく、ＰＮ接合の破壊
を防止することが可能となる。更に上記ＰＮ接合の周縁
部をその中央部よりも深く拡散形成しているため、逆バ
イアス電圧印加時にも上記ＰＮ接合の周縁部での電界の
集中を未然に防止することができ耐圧も大幅に向上する
。Effects of the Invention According to the present invention, by dividing the PN junction into multiple parts, when a forward bias voltage is applied, the current distribution in the PN junction becomes uniform, and the actual current path is expanded, so that the current distribution in the forward direction is Characteristics are improved. Also, due to the uniformity of the current distribution mentioned above, PN
Breakdown of the PN junction can be prevented without the electric field concentrating on a part of the junction. Furthermore, since the peripheral part of the PN junction is diffused deeper than the central part, it is possible to prevent the electric field from concentrating at the peripheral part of the PN junction even when a reverse bias voltage is applied, and the withstand voltage is also significantly increased. improves.
第１図は従来の半導体装置を示す側断面図、第２図及び
第３図は第１図装置に順バイアス電圧を中加した際の動
作を説明するための側断面図、第４図は半導体装置の順
方向特性を示す特性図、第５図は本発明に係る半導体装
置の一実施例を示す側断面図、第６図は第５図装置に順
バイアス電圧を印加した際の動作を説明するための側断
面図である。
（１）（２）−一−−導電型（Ｎ型）の基板、（９ａ）
（９ｂ） （９ｃ）−第１〜第３の他導電型（Ｐ型）
不純物拡散領域。
特許出願人 関西日本電気株式会社
代理人 江 原 省 吾
〃 江 原 秀
（９）
第１図FIG. 1 is a side cross-sectional view showing a conventional semiconductor device, FIGS. 2 and 3 are side cross-sectional views for explaining the operation when a forward bias voltage is applied to the device shown in FIG. 1, and FIG. A characteristic diagram showing the forward characteristics of the semiconductor device, FIG. 5 is a side sectional view showing an embodiment of the semiconductor device according to the present invention, and FIG. 6 shows the operation when a forward bias voltage is applied to the device shown in FIG. It is a side sectional view for explanation. (1)(2)--Conductivity type (N type) substrate, (9a)
(9b) (9c) - 1st to 3rd other conductivity types (P type)
Impurity diffusion region. Patent applicant: Kansai NEC Co., Ltd. Agent: Sho Ehara Hideo Ehara (9) Figure 1
Claims (1)
した複数の第１の他導電型不純物拡散領域と、上記第１
の他導電型不純物拡散領域を離隔して囲繞しかつ第１の
他導電型不純物拡散領域よりも深く形成した第２の他導
電型不純物拡散領域と、上記第１の他導電型不純物拡散
領域同土間及び第１、第２の他導電型不純物拡散領域を
連結するように第１の他導電型不純物拡散領域よりも浅
く形成した第３の他導電型不純物拡散領域とを設けたこ
とを特徴とする半導体装置。(1) - A plurality of first impurity diffusion regions of a different conductivity type formed in island shapes on a substrate of a conductivity type;
a second impurity diffusion region of other conductivity type that surrounds and separates the impurity diffusion region of other conductivity type and is formed deeper than the first impurity diffusion region of other conductivity type; A third impurity diffusion region of other conductivity type formed shallower than the first impurity diffusion region of other conductivity type is provided to connect the dirt floor and the first and second impurity diffusion regions of other conductivity type. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4353684A JPS60187063A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4353684A JPS60187063A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60187063A true JPS60187063A (en) | 1985-09-24 |
Family
ID=12666455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4353684A Pending JPS60187063A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60187063A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489666B1 (en) | 2000-02-23 | 2002-12-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved heat suppression in peripheral regions |
-
1984
- 1984-03-06 JP JP4353684A patent/JPS60187063A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489666B1 (en) | 2000-02-23 | 2002-12-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved heat suppression in peripheral regions |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2003318413A (en) | High breakdown voltage silicon carbide diode and manufacturing method therefor | |
| US4215358A (en) | Mesa type semiconductor device | |
| JPS60187063A (en) | Semiconductor device | |
| JPH08167715A (en) | High breakdown voltage semiconductor device | |
| JP2003031791A (en) | Semiconductor device | |
| JP2003224276A (en) | Semiconductor device and its manufacturing method | |
| JPH08264811A (en) | Schottky barrier diode | |
| JPS60145660A (en) | Manufacture of semiconductor device | |
| JPS6327865B2 (en) | ||
| JP3625380B2 (en) | Schottky barrier semiconductor device and manufacturing method thereof | |
| JPH02202061A (en) | Reverse conduction gate turn off thyristor | |
| JP2583032B2 (en) | Light receiving element | |
| JPH06204232A (en) | Semiconductor device and manufacturing method thereof | |
| JP2002246611A (en) | Semiconductor element | |
| JPH07115211A (en) | Schottky semiconductor device | |
| JPH08167617A (en) | High breakdown voltage semiconductor device | |
| JP3620344B2 (en) | Schottky barrier diode and manufacturing method thereof | |
| KR100320676B1 (en) | Thyristor device | |
| JPH0494572A (en) | Lateral type thyristor | |
| JPS63124567A (en) | Semiconductor device | |
| JPH06350111A (en) | Varactor diode | |
| TW202341501A (en) | Merged pin schottky (mps) diode and method of manufacturing the same | |
| JPS58155769A (en) | Semiconductor rectifier diode | |
| JPH06224410A (en) | Manufacture of schottky barrier diode | |
| JPH03270270A (en) | Semiconductor device with pn-junction and its manufacture |