JPS60179054U - Semiconductor memory mounting structure - Google Patents

Semiconductor memory mounting structure

Info

Publication number
JPS60179054U
JPS60179054U JP6804084U JP6804084U JPS60179054U JP S60179054 U JPS60179054 U JP S60179054U JP 6804084 U JP6804084 U JP 6804084U JP 6804084 U JP6804084 U JP 6804084U JP S60179054 U JPS60179054 U JP S60179054U
Authority
JP
Japan
Prior art keywords
semiconductor memory
leads
mounting structure
memory mounting
storage container
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6804084U
Other languages
Japanese (ja)
Inventor
博 吉野
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP6804084U priority Critical patent/JPS60179054U/en
Publication of JPS60179054U publication Critical patent/JPS60179054U/en
Pending legal-status Critical Current

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  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す断面図、第２図はリード
フレームの平面図、第３図は収納容器を示す斜視図、第
４図は本考案の他の実施例を示す断面図である。 １・・・リード、２，９・・・基台、３，４・・・半導
体メモリ、５・・・フレーム、６・・・貫通孔、７，８
・・・電極端子。Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a plan view of a lead frame, Fig. 3 is a perspective view showing a storage container, and Fig. 4 is a sectional view showing another embodiment of the invention. It is. DESCRIPTION OF SYMBOLS 1... Lead, 2, 9... Base, 3, 4... Semiconductor memory, 5... Frame, 6... Through hole, 7, 8
...Electrode terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リードフレームに設けられたリードを階段状に曲折し、
該リードの少な（とも一部を基台に接着固定し、前記リ
ードフレームからリード部分を切断して収納容器を形成
し、該収納容器内に電極端子の長さが異なる半導体メモ
リを積層し、前記リードの階段部分上に載置された半導
体メモリの電極端子と前記リードとを半田付けすること
を特徴とする半導体メモリの実装構造。By bending the leads provided on the lead frame into a step-like shape,
Adhesively fix a portion of the leads to a base, cut the lead portions from the lead frame to form a storage container, stack semiconductor memories with electrode terminals of different lengths in the storage container, A mounting structure for a semiconductor memory, characterized in that electrode terminals of the semiconductor memory placed on the stepped portions of the leads are soldered to the leads.
JP6804084U 1984-05-09 1984-05-09 Semiconductor memory mounting structure Pending JPS60179054U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6804084U JPS60179054U (en) 1984-05-09 1984-05-09 Semiconductor memory mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6804084U JPS60179054U (en) 1984-05-09 1984-05-09 Semiconductor memory mounting structure

Publications (1)

Publication Number Publication Date
JPS60179054U true JPS60179054U (en) 1985-11-28

Family

ID=30602422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6804084U Pending JPS60179054U (en) 1984-05-09 1984-05-09 Semiconductor memory mounting structure

Country Status (1)

Country Link
JP (1) JPS60179054U (en)

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