JPS60177677A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60177677A JPS60177677A JP3298784A JP3298784A JPS60177677A JP S60177677 A JPS60177677 A JP S60177677A JP 3298784 A JP3298784 A JP 3298784A JP 3298784 A JP3298784 A JP 3298784A JP S60177677 A JPS60177677 A JP S60177677A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- offset
- conductive type
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 abstract description 21
- 239000002344 surface layer Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はオフセ、)・ゲー)MO8型FETのドレイン
披散層構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a drain diffusion layer structure of an MO8 type FET.
r従来技術〕
従来、オフセット・ゲート型高耐圧MOB FF1Tは
第1図の如き断面構造となっているのが通例である。す
なわち、第1の導電型からなる半導体基根1の表面には
、フィールド酸化膜2、ゲート酸化膜3、ゲート電極4
が形成されると共に、ソース拡散領域5、ドレイン拡散
領域6とオフセット・ゲート部7が第2の導電、型から
成る拡散層として形成されて成る。rPrior Art] Conventionally, an offset gate type high voltage MOB FF1T usually has a cross-sectional structure as shown in FIG. That is, on the surface of the semiconductor base 1 of the first conductivity type, a field oxide film 2, a gate oxide film 3, and a gate electrode 4 are formed.
At the same time, a source diffusion region 5, a drain diffusion region 6, and an offset gate portion 7 are formed as a diffusion layer of a second conductive type.
しかし、上記従来技術によると、オフ上9ト・ゲート部
に電圧が分配されて印加されるため1例えば高電圧を印
加しながら高温(250°C程度)に該MO8型FKT
f晒すと、核MOEI型FETのソースとドレイン間の
電流より8が徐々に増加するという特性変動が発生する
欠点がある。However, according to the above-mentioned conventional technology, since the voltage is distributed and applied to the OFF top gate part, for example, the MO8 type FKT is heated to a high temperature (about 250°C) while applying a high voltage.
When exposed to f, there is a drawback that characteristic fluctuation occurs in that 8 gradually increases from the current between the source and drain of the nuclear MOEI type FET.
本発明はかかる従来技術の欠点をなくし、高温、高電圧
バイアス下セも高耐圧MO8FETの特性変動のないM
O8型FKTを提供することを目的とする。The present invention eliminates the drawbacks of the prior art, and eliminates the characteristic fluctuation of the high voltage MO8FET even under high temperature and high voltage bias.
The purpose is to provide O8 type FKT.
上記−目的を達成するだめの本発明の基本的な構成け、
半導体装置に関し、MO8型トランジスタの少なくとも
ドレイン拡散層領域に於て、オフセット拡散抵抗層が半
導体基板内に埋め込まれて成ることを特徴とする。The basic structure of the present invention to achieve the above-mentioned object,
The semiconductor device is characterized in that an offset diffused resistance layer is embedded in the semiconductor substrate at least in the drain diffusion layer region of the MO8 transistor.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
ta2図は本発明の一実施例を示すMOEI型FETの
断面図である。すなわち、第1の導電型力1ら成るSi
基板11の表面には、フィールド酸化膜R、ゲート酸化
膜13、ゲート電極14が形成さね、ると共にソース拡
散層15、ドレイン拡散層16と埋め込みオフセット拡
散層17が第2の導電型の拡散層で形成され、埋め退入
オフセット拡散層17上にけ、第1の導電、型から成る
拡散層18が形成されて成る。Figure ta2 is a cross-sectional view of a MOEI type FET showing one embodiment of the present invention. That is, Si consisting of the first conductivity type force 1
A field oxide film R, a gate oxide film 13, and a gate electrode 14 are formed on the surface of the substrate 11, and a source diffusion layer 15, a drain diffusion layer 16, and a buried offset diffusion layer 17 are formed as second conductivity type diffusion layers. A first conductive type diffusion layer 18 is formed on the buried offset diffusion layer 17.
上記の如く、オフセット拡散抵抗層を坤め込んで形成す
ることにより、オフセ、)部への電圧印加がバルク内で
行なわれ1表面層の界面準位の高温、高電圧バイアスに
よる増加の影響により抵抗値が変化することなく、安定
な電流特性が得られる効果がある。As described above, by embedding and forming the offset diffused resistance layer, voltage is applied to the offset portion () within the bulk, and due to the influence of increase in the interface state of the surface layer due to high temperature and high voltage bias. This has the effect of providing stable current characteristics without changing the resistance value.
本発明はゲート下に埋め退入拡散抵抗層が形成されても
良く、ソースとドレイン両領斌に埋め込みオフセット拡
散抵抗層が形成されても良く、その効果は同じである。In the present invention, a buried offset diffused resistance layer may be formed under the gate, or a buried offset diffused resistance layer may be formed in both the source and drain regions, and the effect is the same.
第1図は従来技術によるオフセット・ゲート型MO8F
ICTの断面図、第2図は本発明の一実施例を示す埋め
通入オフセット・ゲート型MO8Fil:Tの断面図で
ある。
1.11・・・・・・si基板
2・12・・・・・・フィールl’ 酸化M5、13
、、、、、、ゲート酸化膜
4、14 、、、、、、ゲート電極
5.15・・・・・・ソース領域
−6,16・・・・・・ドレイン領域
7・・・・・・オフセット拡散層Figure 1 shows an offset gate type MO8F using conventional technology.
FIG. 2 is a cross-sectional view of a buried through offset gate type MO8Fil:T showing one embodiment of the present invention. 1.11... Si substrate 2, 12... Field l' oxidation M5, 13
, , , , Gate oxide film 4, 14 , , Gate electrode 5.15... Source region -6, 16... Drain region 7... offset diffusion layer
Claims (1)
に於て、オフセット拡散抵抗層が半導体基板内に埋め込
まれて成ることを特徴とする半導体装置。A semiconductor device characterized in that an offset diffused resistance layer is embedded in a semiconductor substrate in at least a drain diffusion layer region of a MOB type transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3298784A JPS60177677A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3298784A JPS60177677A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60177677A true JPS60177677A (en) | 1985-09-11 |
Family
ID=12374222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3298784A Pending JPS60177677A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60177677A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0197501A2 (en) * | 1985-04-12 | 1986-10-15 | General Electric Company | Extended drain concept for reduced hot electron effect |
JPH02106973A (en) * | 1988-10-17 | 1990-04-19 | Nec Corp | Semiconductor device |
EP0414226A2 (en) * | 1989-08-24 | 1991-02-27 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
US5170232A (en) * | 1989-08-24 | 1992-12-08 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
US5567965A (en) * | 1994-05-16 | 1996-10-22 | Samsung Electronics Co., Ltd. | High-voltage transistor with LDD regions |
WO2003017349A3 (en) * | 2001-08-17 | 2003-11-27 | Ihp Gmbh | Dmos transistor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509388A (en) * | 1973-05-22 | 1975-01-30 | ||
JPS55108773A (en) * | 1979-02-14 | 1980-08-21 | Nec Corp | Insulating gate type field effect transistor |
-
1984
- 1984-02-23 JP JP3298784A patent/JPS60177677A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509388A (en) * | 1973-05-22 | 1975-01-30 | ||
JPS55108773A (en) * | 1979-02-14 | 1980-08-21 | Nec Corp | Insulating gate type field effect transistor |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0197501A2 (en) * | 1985-04-12 | 1986-10-15 | General Electric Company | Extended drain concept for reduced hot electron effect |
JPH02106973A (en) * | 1988-10-17 | 1990-04-19 | Nec Corp | Semiconductor device |
EP0414226A2 (en) * | 1989-08-24 | 1991-02-27 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
US5170232A (en) * | 1989-08-24 | 1992-12-08 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
US5567965A (en) * | 1994-05-16 | 1996-10-22 | Samsung Electronics Co., Ltd. | High-voltage transistor with LDD regions |
US5879995A (en) * | 1994-05-16 | 1999-03-09 | Samsung Electronics Co., Ltd. | High-voltage transistor and manufacturing method therefor |
WO2003017349A3 (en) * | 2001-08-17 | 2003-11-27 | Ihp Gmbh | Dmos transistor |
US7304348B2 (en) | 2001-08-17 | 2007-12-04 | Ihp Gmbh - Innovations For High Performance Microelectronics/Institut Fur Innovative Mikroelektronik | DMOS transistor |
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