JPS6017712A - Differential type sensor device - Google Patents
Differential type sensor deviceInfo
- Publication number
- JPS6017712A JPS6017712A JP12633383A JP12633383A JPS6017712A JP S6017712 A JPS6017712 A JP S6017712A JP 12633383 A JP12633383 A JP 12633383A JP 12633383 A JP12633383 A JP 12633383A JP S6017712 A JPS6017712 A JP S6017712A
- Authority
- JP
- Japan
- Prior art keywords
- charge storage
- charge
- photoelectric conversion
- storage section
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C3/00—Measuring distances in line of sight; Optical rangefinders
- G01C3/02—Details
- G01C3/06—Use of electric means to obtain final indication
- G01C3/08—Use of electric radiation detectors
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Length Measuring Devices By Optical Means (AREA)
- Measurement Of Optical Distance (AREA)
- Automatic Focus Adjustment (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は差動型センサ装置に関し、特に被写体に光2投
光し、被写体からの反射光を受光手段により受光して該
受光手段からの信号を用いて被写体までの距離を検出す
る距離検出に用いるときに有効な差動型センサ装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential sensor device, and particularly relates to a differential sensor device that emits two lights onto a subject, receives the reflected light from the subject by a light receiving means, and uses a signal from the light receiving means to detect the subject. The present invention relates to a differential sensor device that is effective when used for distance detection.
従来、距離検出用の光電変換素子おしてはシリコンフォ
トダイオード等の非蓄積型の光電変換素子が使用されて
いるが、これらの光電変換素子より生ずる出力信号は非
常に小さいので、増幅時に回路雑音の影響が大きく、な
かなか良好なるS、/Nk得ることが出来なく、又測距
できる検知距離も短かかった。Conventionally, non-storage type photoelectric conversion elements such as silicon photodiodes have been used as photoelectric conversion elements for distance detection, but since the output signals generated by these photoelectric conversion elements are very small, it is difficult to eliminate circuit noise during amplification. The influence was large, and it was not possible to obtain a very good S,/Nk, and the measurable detection distance was also short.
本発明は信号の読み出し特性が良く、シかもS/N比の
高い信号が得られる差動型センサ装置の提供を目的とし
、更なる目的は距離検出系に用いたときに好ましい信号
出力の得られる。差動型センサ装置の提供を目的とする
。An object of the present invention is to provide a differential sensor device that has good signal readout characteristics and can obtain signals with a high S/N ratio, and a further object is to obtain a preferable signal output when used in a distance detection system. It will be done. The purpose is to provide a differential sensor device.
本発明の目的を達成する為の差動型センサ装置の主なる
特徴は被写体に投光する為の光源と、被写体からの反射
光を受光する為の、入射光量により電荷量が変わる第1
と第2の光電変換部を有する光電変換手段と
前記光源により投光している間前記第1.第2の元′亀
変換部で生ずる電荷全各々蓄積する第1と第2の電荷蓄
積部と
前記光源による非投光時の一定期間、前記第1、駆2の
光電変換部で生ずる電荷全各々蓄積する第3と第4の電
荷蓄積部を有し、第1の電荷蓄積部に蓄積された情報と
第3の電荷蓄積部に蓄積された情報との差及び、第2の
電荷蓄積部に蓄積された情報と第4の電荷蓄積部に蓄積
された情報との差金電荷蓄積手段とゲート手段を介して
演算することである。そして更に好ましくは前記第1の
電荷蓄積部に蓄積された情報と第3の電荷蓄積部に蓄積
された情報の差す第2の電荷蓄積部に蓄積された情報と
第4の電荷蓄積部に蓄積された情報の差との差?電荷蓄
積手段とゲート手段ヶ介して演算しこ・のときの差を用
いることである、
次に本発明の実施例を各図上用いて説明する。The main features of the differential sensor device for achieving the purpose of the present invention are a light source for projecting light onto the subject, and a first sensor for receiving reflected light from the subject, whose charge amount changes depending on the amount of incident light.
and a second photoelectric conversion section, and the light source is emitting light. The first and second charge storage sections each accumulate the entire charge generated in the second photoelectric conversion section, and the total charge generated in the first and second photoelectric conversion sections accumulates for a certain period when the light source does not emit light. The difference between the information stored in the first charge storage part and the information stored in the third charge storage part is determined by the difference between the information stored in the first charge storage part and the information stored in the third charge storage part. The difference between the information stored in the fourth charge storage section and the information stored in the fourth charge storage section is calculated via the charge storage means and the gate means. More preferably, the information stored in the first charge storage section and the information stored in the third charge storage section are the information stored in the second charge storage section and the information stored in the fourth charge storage section. The difference between the information given and the difference? Embodiments of the present invention will be described below with reference to each figure.
第1図(a) 、 (b) 、 (e)は差動型センサ
装置で用いている蓄積型の光電変換手段の説明図である
。FIGS. 1(a), 1(b), and 1(e) are explanatory diagrams of storage type photoelectric conversion means used in a differential type sensor device.
第1図(a)は光源からの投光時、投光による被写体か
らの反射光により2つの光電変換部A4 +B、に生じ
る電荷量A、Bと投光全停止したときに、周囲光により
生ずる電荷量Ao、Bok概念的に示したものであり各
々の電荷量の和A + Ao 。Figure 1 (a) shows the amount of charge generated in the two photoelectric conversion units A4 + B by the reflected light from the subject when the light is emitted from the light source, and the amount of charge generated by the ambient light when the light emission is completely stopped. The generated charge amounts Ao and Bok are shown conceptually, and the sum of each charge amount is A + Ao.
B + Boが各々の光電変換部AI HBHから第1
.i2の電荷蓄積部A2.B2に各々蓄積され、非投光
時、光電変換部A41 BHに生じる電荷A。+BOが
第3、第4の電荷蓄積部As 、 Bsに各々蓄積され
る。B + Bo is the first
.. i2 charge storage section A2. Charges A are accumulated in B2 and generated in the photoelectric conversion unit A41BH when no light is emitted. +BO is accumulated in the third and fourth charge accumulation sections As and Bs, respectively.
これらの蓄積電荷は本発明の差動回路で差が取られるこ
とにより第1図(b)に示す如く、投光による反射光成
分の電荷量A、Bのみが検出され、この結果第1図(C
)の如く電荷量A、BがA=Hの時に、例えは距離検出
系のレンズ系が合焦位置と判断しA>Bの時前ピン状態
、A<Hの時後ピン状態であると判断する。又このとき
電荷1ffl A + Bの値會一定1直に保つように
すると、A−Bの合焦位置付近での傾きがほぼ一定にな
り、合焦精度を一定に保持出来るので好ましい。By taking the difference between these accumulated charges in the differential circuit of the present invention, only the charge amounts A and B of the reflected light components due to the projection of light are detected, as shown in FIG. 1(b), and as a result, as shown in FIG. (C
) When the electric charges A and B are A=H, for example, the lens system of the distance detection system determines that it is the in-focus position, and when A>B it is in the front focus state, and when A<H it is in the back focus state. to decide. At this time, it is preferable to maintain the value of the charge 1ffl A + B at a constant value, since the slope of A-B near the in-focus position becomes approximately constant, and the focusing accuracy can be maintained constant.
第2図は差動型センサ装置で用いる光電変換手段の光電
変換部の一実施例の説明図である、AS 、BSは第1
.第2の光電変換部、AL。FIG. 2 is an explanatory diagram of an embodiment of the photoelectric conversion section of the photoelectric conversion means used in the differential sensor device. AS and BS are the first
.. A second photoelectric conversion unit, AL.
BLは投光時、投光による反射光と周囲光の利金蓄積す
る第1.第2の電荷蓄積部、AD、BDは非投光時、周
囲光全蓄積する第3.第4の電荷蓄積部ICG1.IC
G2はφICGが高レベルの時光電変換部AS、BSよ
り生ずる電荷をクリアするための積分クリアゲート、S
Hl。BL is the first stage that accumulates the interest of the reflected light and ambient light when the light is emitted. The second charge storage parts AD and BD store the entire ambient light when no light is emitted. Fourth charge storage unit ICG1. IC
G2 is an integral clear gate, S, for clearing the charges generated from the photoelectric conversion units AS and BS when φICG is at a high level.
Hl.
5)12は電荷移送ゲートでありφ8H1が高レベルの
時光電変換部AS、BSより生じた電荷?電荷蓄積部A
L、BLに蓄積し、φ8H2が高レベルの時光電変換部
AS、BSより生じた電荷を電荷蓄積部AD、BDに蓄
積する。Di−D4、L1〜L3は電荷転送部でありク
ロックパルスφ1.φ2により電荷蓄積部に蓄積されて
G二
いる電荷全電荷電圧変換部BC転送し信号読み△
出しが行われる。5) 12 is a charge transfer gate, and when φ8H1 is at a high level, charges generated from the photoelectric conversion units AS and BS? Charge storage section A
When φ8H2 is at a high level, the charges generated from the photoelectric conversion units AS and BS are accumulated in the charge accumulation units AD and BD. Di-D4, L1 to L3 are charge transfer parts, and clock pulses φ1. By φ2, all charges G2 accumulated in the charge storage section are transferred to the voltage conversion section BC, and signal reading is performed.
ALとBL及びADとBDに蓄積された電荷(A+Al
l+)+(B+BO)とAo +Boとがフローティン
グゲートFGI 、FGZを介して非破壊に読み出さh
差動増幅回路DA4に介して(A十Ao ) + (B
+ Bo ) (Ao + Bo ) −A + B
の信号VA+Bが出力される。このVA+Hの出方が基
準]直に達した時にイ百号の読み出し全行う。Charges accumulated in AL and BL and AD and BD (A+Al
l+)+(B+BO) and Ao+Bo are read out non-destructively via floating gates FGI and FGZ.
(A0Ao) + (B
+ Bo) (Ao + Bo) -A + B
A signal VA+B is output. When the appearance of VA+H reaches the standard], read out all of I-100.
第3図は光電変換手段全駆動する電気回路の一実施例の
説明図であり第4図は、第3図主要部のタイミングチャ
ートである。FIG. 3 is an explanatory diagram of one embodiment of an electric circuit for fully driving the photoelectric conversion means, and FIG. 4 is a timing chart of the main parts of FIG.
時刻t。で電源スィッチswがオンする古、電源E1が
各部に印加され発振器O8Cが発振を開始し、定電圧電
源REQはVc f出力する。同時にOSCの立上りパ
ルスに同期してコンデンサC20、抵抗R20より決ま
る短時間の間、アンドゲートA N I)の出力は高レ
ベルに反転するのでワンショット回路ONIがワンショ
ットパルス全発生し、オアゲートOR6に介して時刻t
。−t2の間に蓄積型光電変換素子内の光電変換部の不
必要な電荷のり11アが行われる。またこの間にR8T
フリップフロップRFI 、RF5もリセットされる。Time t. When the power switch sw is turned on, the power source E1 is applied to each part, the oscillator O8C starts oscillating, and the constant voltage power source REQ outputs Vc f. At the same time, in synchronization with the rising pulse of OSC, the output of the AND gate A N I) is inverted to a high level for a short time determined by the capacitor C20 and the resistor R20, so the one-shot circuit ONI generates all the one-shot pulses, and the OR gate OR6 at time t
. -t2, unnecessary charge accumulation 11a of the photoelectric conversion section in the storage type photoelectric conversion element is performed. Also during this time R8T
Flip-flops RFI and RF5 are also reset.
更にコンデンサC40,抵抗R4(lより決まる短時間
の間にOSCの立上りパルスに同期してアントゲ−1−
AN3.オアケートOR8、OR9に介してDフリップ
フロップ1) F’ 1力Sイニシャルセットされた後
、OS Cからのパルスが分周されクロックパルスφ1
゜φ2を発生し、電荷蓄積部と転送部内の不必喪市荷の
クリアが行われる。またOSCの高レベル信号によりト
ランジスタTriがオンするので抵抗R1により規制さ
れる電流で発光素子LDが発光し、投光レンズLN1’
に介し被写体OBに投射され、反射光が受光レンズLN
2e介し光電変換素子上に結像する。光電変換部A1と
Blの接する位置の中央部に反射光像が結像すると、光
電変換部A、 、 B、の出力が等しくなり例えば撮影
レンズが合焦位置であるように距離検出系が構成されて
いる。時刻t、でワンショットONIの出力が低レベル
に反転するとO8′Cが高レベルの時投光時の反射光信
号が電荷蓄積部AL。In addition, capacitor C40 and resistor R4 (1)
AN3. After the initial setting of the D flip-flop 1) F' 1 through OR gates OR8 and OR9, the pulse from OS C is divided and the clock pulse φ1
°φ2 is generated, and unnecessary items in the charge storage section and transfer section are cleared. Also, since the transistor Tri is turned on by the high level signal of the OSC, the light emitting element LD emits light with the current regulated by the resistor R1, and the light emitting lens LN1'
The reflected light is projected onto the subject OB through the light receiving lens LN.
An image is formed on the photoelectric conversion element via 2e. When a reflected light image is formed at the center of the contact position of the photoelectric conversion units A1 and Bl, the outputs of the photoelectric conversion units A, , and B become equal, and the distance detection system is configured such that, for example, the photographing lens is in the focused position. has been done. At time t, when the output of the one-shot ONI is inverted to a low level, the reflected light signal when light is emitted when O8'C is at a high level is reflected from the charge storage section AL.
BLに、OSCが低レベルの時、非投光時の信号が電荷
蓄積部AD、BDに交互に蓄積される。When BL and OSC are at a low level, signals at the time of non-emission are alternately stored in charge storage parts AD and BD.
同時にAN3の出力が低レベルに反転するのでDPIへ
のパルスの供給が遮断され、φ2は高レベル、φ1は低
レベルに保持され電荷の蓄積を行う。時刻t3でVAA
3B信号が抵抗R2,R3で決まる基準電圧上越えると
コンパレータCPIの出力は高レベル側に反転するので
時刻t4でOSCのパルスの立上りに同期してオアゲー
トOR1に介してR8TフリップフロップRFIがセッ
トされ、ワンショットON2がワンショットパルス全発
生しφICGe高レベルにして蓄積型の光′1℃変換手
段への画像情報の蓄積全完了する。時刻1.に於いてD
FOのQ出力の立上りに同期してRF5がセットされ、
ワンショット回路ON4がワンショットパルス全発生す
るのでアンドゲートAN10y介してパルスがDFlに
供給されるのでφ1.φ2がオン、オフ駆動され蓄積さ
れた画像情報の読み出しが行われる。OH2の立上りに
同期して、パルス制御回路P CKか駆動され、時刻t
AテφAパルスか発生するとサンプルホールド回路SD
IにADに蓄積されていた情報VADが読み出される。At the same time, the output of AN3 is inverted to a low level, so the supply of pulses to the DPI is cut off, and φ2 is held at a high level and φ1 is held at a low level to accumulate charges. VAA at time t3
When the 3B signal exceeds the reference voltage determined by resistors R2 and R3, the output of the comparator CPI is inverted to the high level side, so at time t4, the R8T flip-flop RFI is set via the OR gate OR1 in synchronization with the rising edge of the OSC pulse. , one-shot ON2 generates all one-shot pulses, sets φICGe to high level, and completes storage of image information in the storage type optical '1°C conversion means. Time 1. D in
RF5 is set in synchronization with the rise of FO's Q output,
Since the one-shot circuit ON4 generates all one-shot pulses, the pulses are supplied to DF1 via the AND gate AN10y, so that φ1. φ2 is turned on and off, and the stored image information is read out. In synchronization with the rising edge of OH2, the pulse control circuit PCK is driven, and at time t
When AteφA pulse occurs, sample and hold circuit SD
Information VAD stored in AD is read out at I.
時刻tBでφBパルスが生ずるとALに蓄積された情報
VALが読み出され差動増幅回路DA5’に介してサン
プルホールド回路SD3にVAL −VADの情報が保
持される。時刻tQでφCパルスが生じると、サンプル
ホールド回路SDIにBDに蓄tl(された情報VHD
が読み出される。時刻tDでφDパルスカ5生じるとサ
ンプルホールド回路SD2にBLに蓄積された情報VB
Lが読み出され、差動増幅回路DA5’e介してサンプ
ルホールド回路SD4にVBL −VBDの情報が保持
され同時に差動増幅回路DA6’に介してサンプルホー
ルド回路SD5に(VAL−VAD ) −(VBL−
VBD )の情報が検出保持される。この情報に基づい
て制御回路CKTk介して撮影レンズの合焦位置への駆
動が行われる。なお電荷電圧変換部に出力された画像情
報は各サンプルホー、ルドの後φR8’に高レベルにす
ることにより各々クリアされる時刻t6に於いてRF5
がDFOのQ出力の立上りに同期してリセットされt。When the φB pulse occurs at time tB, the information VAL stored in AL is read out, and the information VAL - VAD is held in the sample hold circuit SD3 via the differential amplifier circuit DA5'. When a φC pulse occurs at time tQ, the sample and hold circuit SDI outputs the information stored in BD (tl).
is read out. When φD pulse 5 occurs at time tD, the information VB stored in BL is sent to the sample hold circuit SD2.
L is read out, and the information of VBL - VBD is held in the sample and hold circuit SD4 via the differential amplifier circuit DA5'e, and at the same time, the information of (VAL - VAD ) - ( VBL-
VBD ) information is detected and held. Based on this information, the photographing lens is driven to the in-focus position via the control circuit CKTk. Note that the image information output to the charge voltage converter is cleared by setting φR8' to high level after each sample hold and hold at time t6.
is reset in synchronization with the rise of the Q output of the DFO.
−t6と同じ動作が以後繰り返される。- The same operation as t6 is repeated thereafter.
これらの従来例ではサンプルホールド回路、差動増幅回
路を介して時系列的に出力される情報の演算全行ってい
るが、これらの回路は複雑であり、また高精度の演算を
行うためにはバイポーラトランジスタで構成する必要力
3あり、差動型センサ部と一体に構成することは困難で
おる。In these conventional examples, all calculations of information output in a time-series manner are performed via a sample-and-hold circuit and a differential amplifier circuit, but these circuits are complex, and in order to perform high-precision calculations, It requires 3 forces to be constructed using bipolar transistors, and it is difficult to construct it integrally with the differential sensor section.
本発明は、これらの演算を電荷蓄積手段と、ゲート手段
全弁して簡単な回路構成で高精度に行ない、四にこれら
の演算回路を差動型センサ士一体に・は成出来る構造を
提示するものである。The present invention performs these calculations with high precision using a charge storage means and a gate means with a simple circuit configuration, and fourth, presents a structure in which these calculation circuits can be integrated into a differential sensor circuit. It is something to do.
第5し1が本発明の一実施例の6気回路である。The fifth circuit 1 is a 6-air circuit according to an embodiment of the present invention.
CN Tは第3図の光電変換手段SPDを駆動する駆動
回路であり、PDKは第3図のパルス制御回路PCKに
対応するものであり、ゲート手段AGI−AG3 、B
GI〜BG3 、CGI全制御する。CNT is a drive circuit for driving the photoelectric conversion means SPD of FIG. 3, PDK corresponds to the pulse control circuit PCK of FIG. 3, and gate means AGI-AG3, B
GI to BG3, fully controls CGI.
C50〜C54はコンデンサから成る電荷蓄積手段、F
GI 、FG2は電界効果型トランジスタであり、抵抗
R50,R51と共にソースホロワ−回路を構成する。C50 to C54 are charge storage means consisting of capacitors, F
GI and FG2 are field effect transistors, which together with resistors R50 and R51 constitute a source follower circuit.
VCI 、 VO2は適当な電圧の基準電圧である。VCI and VO2 are appropriate reference voltages.
第6図力S第5図の主要部のタイミングチャートであり
これを用いて第5図の作動全具体的に説明する。時刻を
人でVADの情報が■0より出力されるとアナログゲー
トAGI、AG3がオン、AC3がオフしているのでコ
ンデンサC50には、VAD −MCIの電圧情報が蓄
えられる。Figure 6 is a timing chart of the main parts of Figure 5. Using this, the entire operation of Figure 5 will be explained in detail. When the VAD information is output from 10 according to the time, the analog gates AGI and AG3 are on and AC3 is off, so the voltage information of VAD -MCI is stored in the capacitor C50.
時刻tA1でアナログゲートAGI、AG3がオフ、A
C3がオンするとVOTI端子の出力VOTI (A)
は
VOTI (A) = VO2−(VAD −VCI
)となる。At time tA1, analog gates AGI and AG3 are turned off, A
When C3 turns on, the VOTI terminal outputs VOTI (A)
is VOTI (A) = VO2-(VAD -VCI
).
時刻tBでVALの情報が■0より出力されるとアナロ
グゲートAGIがオン、AC3,AC3がオフしている
ので、コンデンサC゛51にVAL −VO2の電圧情
報か蓄えられると同時にVOTI端子の出力VOTI(
B)は
VOTI (B) = VOTI (A) + VAL
−VC2= VAL −VAD + VCl
となり第6図の如く変動する。When the VAL information is output from ■0 at time tB, the analog gate AGI is on and AC3 and AC3 are off, so the voltage information of VAL - VO2 is stored in the capacitor C51 and at the same time the VOTI terminal is output. VOTI(
B) is VOTI (B) = VOTI (A) + VAL
-VC2=VAL -VAD + VCl and changes as shown in FIG.
つまり基準電圧yc12基準にVALとVADO差の出
力が得られることがわかる。In other words, it can be seen that an output of the difference between VAL and VADO can be obtained based on the reference voltage yc12.
また時刻tBで同時にアナログゲートBGI。Also, at time tB, analog gate BGI is activated at the same time.
BG3がオンBG2がオフするので、 VOTI(B)
の情報がrGl、a5oから成るソースホロワ−回路を
介して、コンデンサC52にVAL −VADの電圧情
報が蓄えられる。BG3 is on and BG2 is off, so VOTI(B)
The voltage information of VAL -VAD is stored in the capacitor C52 via a source follower circuit consisting of rGl and a5o.
ソースホロワ−回路のオフセット電圧はバイアス項とし
て入るので、無視する。The offset voltage of the source follower circuit is included as a bias term, so it is ignored.
時刻tB1でアナログゲートBG2がオン、BGI、B
G3がオフするのでVOT2端子の出力VOT2(B)
VO’r2(B) = VO2−(VAL −VAD
)となる。At time tB1, analog gate BG2 is turned on, BGI, B
Since G3 is turned off, the output from the VOT2 terminal is VOT2(B) VO'r2(B) = VO2-(VAL-VAD
).
時刻tCでVBDの情報がVOより出力されるとアナロ
グゲートAGI 、AC3がオン、AC3がオフしてい
るのでコンデンサC501こはVBD−VCIの電圧情
報が蓄えられる。When information on VBD is output from VO at time tC, since analog gates AGI and AC3 are on and AC3 is off, capacitor C501 stores voltage information on VBD-VCI.
時刻tcxでアナログゲートAGI、AG3がオフ、A
C3がオンするとVOT1端子の出力VOTI(C)は
VOTI(C) = VO2−(VBD −Vat )
となる。At time tcx, analog gates AGI and AG3 are turned off, A
When C3 is turned on, the output VOTI(C) of the VOT1 terminal is VOTI(C) = VO2-(VBD-Vat)
becomes.
時刻tDでVBLの情報が出力されるとアナログゲート
AGIがオン、AC3、AC3がオフしているので、コ
ンデンサC51にVBL −VO2の電圧情報が蓄えら
れると同時にVOTI端子の出力yo′rt(1))は
VOTx(D)= VoTt(C)+ VBL −VC
2= VBL −VBD −1−Vct
となる。When the VBL information is output at time tD, the analog gate AGI is on and AC3 and AC3 are off, so the voltage information of VBL - VO2 is stored in the capacitor C51, and at the same time the VOTI terminal output yo'rt (1 )) is VOTx (D) = VoTt (C) + VBL - VC
2=VBL-VBD-1-Vct.
またイ時にアンドゲートBGIがオン、BG2 、BG
3がオフしているのでVOTI(D)の情報がFG2.
R51より成るソースホロワ−回路を介して、コンデン
サC53に
VBL −VBD +VQ1− VO2(D電圧情報ト
シテ蓄えられると同時にVOT2端子の出力VOT2(
D)はVO’l’2(D) =VOT2(B) 十VB
L−VBD+VC1−VC2=(VBL−■D ) −
(VAI、−VAD ) +VC1となり、基準電圧y
cs’2基準として、Bセンサ部の投光信号と周囲光信
号の和信号から非投光時の周囲光信号を差引いた真の投
光信号と、Aセンサ部の投光信号と周囲光(g号の和信
号から非投光時の周囲元信号會差引いた真の投光信号と
の差r出力できる。Also, the AND gate BGI is on, BG2, BG
Since FG2.3 is off, the VOTI (D) information is FG2.
Through the source follower circuit consisting of R51, VBL -VBD +VQ1- VO2 (D voltage information is stored in the capacitor C53, and at the same time, the output VOT2 (
D) is VO'l'2(D) =VOT2(B) 10VB
L-VBD+VC1-VC2=(VBL-■D) -
(VAI, -VAD) becomes +VC1, and the reference voltage y
As a cs'2 standard, the true light emission signal obtained by subtracting the ambient light signal when no light is emitted from the sum signal of the light emission signal of the B sensor section and the ambient light signal, and the light emission signal of the A sensor section and the ambient light ( It is possible to output the difference r between the sum signal of No. g and the true light emitting signal obtained by subtracting the surrounding source signal at the time of non-light emitting.
またコンデンサとゲート手段より成る演算回路は、本実
施例に限るものではなく、各種の変形例が考えられるこ
とは、言うまでもない。Furthermore, it goes without saying that the arithmetic circuit comprising the capacitor and the gate means is not limited to this embodiment, and that various modifications can be considered.
端子VO’r2 に出力されたAセンサとBセンサの真
の投光信号の差は、電界効果型トランジスタFG2と抵
抗R51より成るソースホロワ−回路を介して、コンデ
ンサC54にサンプルホールドパルスφCGIでサンプ
ルホールドされ、開側1回路CKTにより焦点調節か行
われる。The difference between the true light emission signals of the A sensor and the B sensor output to the terminal VO'r2 is sampled and held by the sample and hold pulse φCGI to the capacitor C54 via a source follower circuit consisting of a field effect transistor FG2 and a resistor R51. The focus is adjusted by the open side single circuit CKT.
本実施例の説明は電圧演算タイプで示しであるか電荷演
算タイプでも本発明の構成が成立することは明らかであ
る。Although the explanation of this embodiment is based on the voltage calculation type, it is clear that the configuration of the present invention is also applicable to the charge calculation type.
また本発明は時系列的に出力される情報の演算処理に適
する演算方式である。Further, the present invention is an arithmetic method suitable for arithmetic processing of information outputted in a time-series manner.
以上の如く本発明の差動型センサ装置は、演算用の電荷
蓄積手段とゲート手段’rhoSのプロセスで構成出来
るので、演算部を差動型センサ部と一体に構成して、雑
音の影響を減少し、S/Hの著しく良好な焦点検出信号
を得ることが出来る著しい特徴がある。As described above, the differential type sensor device of the present invention can be constructed by the processes of the charge storage means for calculation and the gate means 'rhoS, so the calculation section can be configured integrally with the differential type sensor section to reduce the influence of noise. There is a remarkable feature that it is possible to obtain a focus detection signal with significantly improved S/H.
第1図(a) 、 (b) 、 (C)は本発明に係る
差動型センサ装置lに用いる蓄積型の光電変換手段の説
明図、第2図は本発明で用いる光電変換手段の一実施例
の説明図、
第3図は本発明で用いる光電変換手段?駆動する為の電
気回路の一実施例の説明図、第4図は第3図の主要部の
タイミングチャートである。
第5図は本発明の一実施例の電気・回路の説明図、
第6図は第5図に示す電気回路の主蚤部のタイミングチ
ャートである。
図中Al 、、 Blは光電変換部、A2 r A3
T B2 + B3は電荷蓄積部、A + B r A
o l Boは電荷量全示す。
特許出願人 キャノン株式会社
イエ直FIGS. 1(a), (b), and (C) are explanatory diagrams of an accumulation-type photoelectric conversion means used in the differential sensor device l according to the present invention, and FIG. 2 is an illustration of one of the photoelectric conversion means used in the present invention. An explanatory diagram of the embodiment, FIG. 3 shows the photoelectric conversion means used in the present invention? FIG. 4 is an explanatory diagram of one embodiment of an electric circuit for driving, and FIG. 4 is a timing chart of the main part of FIG. 3. FIG. 5 is an explanatory diagram of an electric circuit according to an embodiment of the present invention, and FIG. 6 is a timing chart of the main part of the electric circuit shown in FIG. In the figure, Al,, Bl are photoelectric conversion parts, A2 r A3
T B2 + B3 is a charge storage section, A + B r A
o l Bo indicates the total amount of charge. Patent applicant: Canon Co., Ltd.
Claims (2)
光音受光する為の、入射光量により電荷量が変わる第1
と第20光電変換部會有する光電変換手段と 前記光源により投光している間、前記第1、第2の光電
変換部で生ずる電荷全各々蓄積する第1と第2の電荷蓄
積部と 前記光源による非投光時の一定期間、前記第1.Ii2
の光電変換部で生ずる電荷を各々蓄積する第3と第4の
電荷蓄積部を有し、前記第1の′電荷蓄積部に蓄積され
た情報と前記第3の電荷蓄積部に蓄積された情報との差
及び、前記第2の電荷蓄積部に蓄積された情報と前記第
4の電荷蓄積手段こ蓄積された情報との差を電荷蓄積手
段とゲート手段を介して演算することt%徴とする差動
型センサ装置。(1) A light source for projecting light onto the subject, and a first light source for receiving reflected light and sound from the subject, whose charge amount changes depending on the amount of incident light.
and a 20th photoelectric conversion unit, a photoelectric conversion means having a first and a second photoelectric conversion unit, each of which accumulates all charges generated in the first and second photoelectric conversion units while the light source emits light; For a certain period of time when no light is emitted by the light source, the first. Ii2
It has a third and a fourth charge storage section each storing charges generated in the photoelectric conversion section, and information stored in the first charge storage section and information stored in the third charge storage section. and the difference between the information stored in the second charge storage section and the information stored in the fourth charge storage section through the charge storage means and the gate means. Differential type sensor device.
の電荷蓄積部に蓄積された情報の差と第2の電荷蓄積部
に蓄積された情報と第4の電荷蓄積部に蓄積された情報
の差との差?電荷蓄積手段とゲート手段を介して演算す
ること全特徴とする特許請求の範囲第(1)項記載の差
動型センサ装置。(2) The information stored in the first charge storage section and the third charge storage section
The difference between the information stored in the second charge storage section and the information stored in the fourth charge storage section? A differential sensor device according to claim 1, characterized in that the calculation is performed through charge storage means and gate means.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12633383A JPS6017712A (en) | 1983-07-12 | 1983-07-12 | Differential type sensor device |
DE19843411690 DE3411690A1 (en) | 1983-04-01 | 1984-03-29 | PHOTOELECTRIC CONVERTER DEVICE |
US06/595,242 US4681432A (en) | 1983-04-01 | 1984-03-30 | Photo-electric converting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12633383A JPS6017712A (en) | 1983-07-12 | 1983-07-12 | Differential type sensor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6017712A true JPS6017712A (en) | 1985-01-29 |
Family
ID=14932582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12633383A Pending JPS6017712A (en) | 1983-04-01 | 1983-07-12 | Differential type sensor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6017712A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4913567A (en) * | 1987-01-07 | 1990-04-03 | Brother Kogyo Kabushiki Kaisha | Head-pressure mechanism in thermal printer |
US10426882B2 (en) | 2003-12-16 | 2019-10-01 | Baxter International Inc. | Blood rinseback system and method |
-
1983
- 1983-07-12 JP JP12633383A patent/JPS6017712A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4913567A (en) * | 1987-01-07 | 1990-04-03 | Brother Kogyo Kabushiki Kaisha | Head-pressure mechanism in thermal printer |
US10426882B2 (en) | 2003-12-16 | 2019-10-01 | Baxter International Inc. | Blood rinseback system and method |
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