JPS60175499A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS60175499A JPS60175499A JP3068384A JP3068384A JPS60175499A JP S60175499 A JPS60175499 A JP S60175499A JP 3068384 A JP3068384 A JP 3068384A JP 3068384 A JP3068384 A JP 3068384A JP S60175499 A JPS60175499 A JP S60175499A
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- alumina substrate
- radiation fin
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は混成集積回路に関し、特に改良された放熱フィ
ンを有する混成集積回路に関する。TECHNICAL FIELD The present invention relates to hybrid integrated circuits, and more particularly to hybrid integrated circuits having improved heat dissipation fins.
′電子衆器の小形化、薄形化さらに高機能化に伴って、
ＩＣ，ＬＳＩや、抵抗、コンデンサ等のチップ部品を高
密度に実装した混成集積回路が拡大してきている。この
ような混成集積回路においては実装部品の発熱景が多く
なり、いかに有効に熱を逃すかが大きな問題点となって
いる。'As electronic devices become smaller, thinner, and more sophisticated,
2. Description of the Related Art Hybrid integrated circuits in which ICs, LSIs, and chip components such as resistors and capacitors are mounted in high density are expanding. In such hybrid integrated circuits, mounted components generate more heat, and how to effectively dissipate heat has become a major problem.
混成集積回路は、一般には第１図に示すように、導体配
線と抵抗とを印刷法により形成したアルミナ基板１の表
面にＩＣ２，トランジスタ３．チップコンデンサ４等を
取付け、必要に応じて熱発生源、例えばパワートランジ
スタ３を取付けたアルミナ基板１の裏面に単に平板をプ
レスして形成した放熱フィン５を接着剤７によシ固定し
、発生した熱を逃す構造となっている。Generally, a hybrid integrated circuit, as shown in FIG. 1, has an IC 2, transistors 3, . Chip capacitors 4, etc. are attached, and heat dissipation fins 5, formed by simply pressing a flat plate, are fixed with adhesive 7 to the back surface of the alumina substrate 1, on which a heat generation source, for example, a power transistor 3, is attached as necessary. It has a structure that allows the heat to escape.
尚、同図中６は外部接続リードである。Note that 6 in the figure is an external connection lead.
しかしながら、このように構成された混成集積回路にお
いては、放熱フィンとアルミナ基板との熱膨張係数の違
いによりｗＮ面に熱応力を生じ、アルミナ基板にそシや
ひび割れを生ずる欠点がある。その結果としてアルミナ
基板上に形成した導体配線が切断したり、膜抵抗の値が
変化する等の不都合を生ずる。However, the hybrid integrated circuit configured in this manner has the drawback that thermal stress is generated on the wN plane due to the difference in thermal expansion coefficient between the radiation fins and the alumina substrate, causing warps and cracks in the alumina substrate. As a result, inconveniences occur such as the conductor wiring formed on the alumina substrate being cut or the value of film resistance changing.
本発明の目的は、上記欠点を除去し、放熱フィンを接着
してもそりやひび割れを生ずることのない信頼性の高い
混成集積回路を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable hybrid integrated circuit that does not cause warping or cracking even when heat dissipation fins are bonded.
本発明の混成集積回路は、アルミナ基板に放熱フィンを
取付けた混成集積回路であって、この放熱フィンには少
くともアルミナ基板と接着する面に複数本のスリットを
有する構造となっている。The hybrid integrated circuit of the present invention is a hybrid integrated circuit in which a radiation fin is attached to an alumina substrate, and the radiation fin has a structure in which a plurality of slits are provided at least on the surface to be bonded to the alumina substrate.
（実施例の説明〕 次に、本発明の実施例を図面を用いて説明する。(Explanation of Examples) Next, embodiments of the present invention will be described using the drawings.
第２図は本発明の一実施例の斜視図である。FIG. 2 is a perspective view of one embodiment of the present invention.
導体配線や膜抵抗が形成され、パワートランジスタ等が
実装されたアルミナ基板１の裏面にはスリット８が形成
された放熱フィン５Ａが接着バリアによシ固定ぎれてい
る。放熱フィン５Ａは複数のスリット８を形成した銅や
アルミニウム板をアルミナ基板１と接着する而にこれら
スリットが位置するようにプレス加工によシ答易に作る
ことができる。アルミナ基板１と放熱フィン５Ａとの接
着は、例えば耐熱性のエポキシ樹脂系接着Ｉｉす又はシ
リコン樹脂系接着剤を用いて行なう。A radiation fin 5A having a slit 8 formed therein is fixed to the back surface of the alumina substrate 1, on which conductor wiring and film resistance are formed, and a power transistor and the like are mounted, by an adhesive barrier. The radiation fins 5A can be easily made by bonding a copper or aluminum plate with a plurality of slits 8 to the alumina substrate 1, and then press working so that these slits are positioned. The alumina substrate 1 and the radiation fins 5A are bonded using, for example, a heat-resistant epoxy resin adhesive or a silicone resin adhesive.
このように構成された混成集積回路においては、アルミ
ナ基板１と放熱フィン５Ａの熱膨張（１の違いによりそ
の接着面に熱応力を生ずるが、この熱応力はスリット８
によシ緩和されるためアルミナ基板１にそりやひび割れ
を生ずることはなくなる。In the hybrid integrated circuit configured in this way, the difference in thermal expansion (1) between the alumina substrate 1 and the radiation fins 5A causes thermal stress on their bonding surfaces.
Since the alumina substrate 1 is relaxed, warping and cracking will not occur in the alumina substrate 1.
これについて、＠３図を用いて説明する。第３図（ａ）
、 （ｂ）は従来の混成集積回路と本発明の一実施例
におけるアルミナ基板と放熱フィンの接着部における熱
応力を示す図である。第３図ｆａ）に示すように、従来
の混成集積回路においては、放熱フィン５とアルミナ基
板１の接着部には熱応力により矢印Ａ 、 Ａ’力方向
膨張力が働くため、アルミナ基板１には矢印Ｂ、Ｂ’方
向の力が加わり、その結果アルミナ基板１にはそシやひ
び割れが発生ずる。This will be explained using Figure @3. Figure 3(a)
, (b) is a diagram showing thermal stress at the bonded portion between the alumina substrate and the radiation fin in a conventional hybrid integrated circuit and an embodiment of the present invention. As shown in FIG. 3 fa), in the conventional hybrid integrated circuit, expansion force in the directions of arrows A and A' acts on the bond between the radiation fin 5 and the alumina substrate 1 due to thermal stress. Forces in the directions of arrows B and B' are applied, and as a result, warps and cracks occur in the alumina substrate 1.
一方、第３図（ｂ）に示す本発明の実施例に２いては、
アルミナ基板１に接着する放熱フィン５Ａにはスリット
８が形成されているため、熱応力による膨張力は矢印Ｃ
に示すようにスリット８によシ分割された小さなものと
なシ、アルミナ基板１にそシやひび割れを発生させるこ
とはない。On the other hand, in the second embodiment of the present invention shown in FIG. 3(b),
Since a slit 8 is formed in the radiation fin 5A that is bonded to the alumina substrate 1, the expansion force due to thermal stress is
As shown in the figure, the small pieces divided by the slits 8 do not cause warping or cracks in the alumina substrate 1.
第４図は本発明の他の実施レリの斜視図であり、放熱フ
ィン５１３０） ’）’ルミナ基板１に接着する一端は
スリット８により分！ｉｊされている。このように構成
された放熱フィン５Ｂにおいてｔま、スリット８により
短冊状に分割された放熱フィン５Ｂの一端は熱応力によ
る膨張力をより多く吸収するため、アルミナ基板１に加
わる熱応力は更に小さいものとなる。FIG. 4 is a perspective view of another embodiment of the present invention, in which a radiation fin 5130) ')' One end to be bonded to the lumina substrate 1 is separated by a slit 8. It has been ij. In the radiation fin 5B configured in this way, one end of the radiation fin 5B, which is divided into strips by the slit 8, absorbs more expansion force due to thermal stress, so the thermal stress applied to the alumina substrate 1 is further reduced. Become something.
上記実施例に示した構造な冶する混成集積回路を用いて
一２５゛υ〜１００℃における熱サイクル試験を行なっ
た結果、従来の混成集積回路がアルミナノ、し板のそり
やひび割れにより不良率が約５０％であったのに対し、
本実施；す１１にぢいてｔま不良率は（）、１％以下で
あった。As a result of thermal cycle tests at temperatures ranging from -25゛υ to 100℃ using the hybrid integrated circuit shown in the above example, it was found that the conventional hybrid integrated circuit had a lower defective rate due to warping and cracking of the aluminum nanoplate. While it was about 50%,
As a result of this implementation, the defect rate was less than 1%.
なお、上記実施例では、放熱フィンの形はＵ字形に形成
したものについ“Ｃ説明したが、これに限定されるもの
ではなくｖ字形、Ｌ字形等であってもよい。尚、スリッ
トの幅は放熱フィンの膨張力を吸収できるＱ、５ ｍｔ
ｇ〜２龍程度が望ましく、狭ずぎると膨張力の吸収が不
十分となり、また広ずぎると放熱効果が減少する。In the above embodiment, the shape of the radiation fin is described as being U-shaped, but it is not limited to this and may be V-shaped, L-shaped, etc. Note that the width of the slit Q, which can absorb the expansion force of the radiation fin, is 5 mt.
It is preferable that the width is about 2.5 g to 2. If the width is too narrow, the expansion force will not be absorbed sufficiently, and if it is too wide, the heat dissipation effect will be reduced.
以上詳細に説明したように、本発明によれは、放熱フィ
ンを接着してもそりやひび割れが生ぜず、信頼性の高い
混成集積回路が得られる。As described above in detail, according to the present invention, a highly reliable hybrid integrated circuit can be obtained without warping or cracking even when heat dissipating fins are bonded.
＠１図は従来の混成集積回路の一例の側面図、第２図は
本発明の一実施例の斜視図、＠３図（ａ）。
ｌｂ）は従来の混成集積回路と本発明の実施例における
アルミナ基板と放熱フィンの接着面における熱応力を示
す図、第４図は本発明の他の実施例の斜視図でおる。
１・・・・・・アルミナ基板、２・・・ＩＣ，３・・・
・・・トランジスタ、４・・・・・・チップコンデンサ
、５，５Ａ。
５Ｂ・・・・・・放熱フィン、６・・・・・・外部接続
リード、７・・・・・・接着剤、８・・・・・・スリッ
ト。 ２．−１、代理人 弁理士 内 原 汗（、Figure 1 is a side view of an example of a conventional hybrid integrated circuit, Figure 2 is a perspective view of an embodiment of the present invention, and Figure 3 (a). lb) is a diagram showing thermal stress at the bonding surface between the alumina substrate and the radiation fin in a conventional hybrid integrated circuit and an embodiment of the present invention, and FIG. 4 is a perspective view of another embodiment of the present invention. 1...Alumina substrate, 2...IC, 3...
...Transistor, 4...Chip capacitor, 5.5A. 5B...Radiation fin, 6...External connection lead, 7...Adhesive, 8...Slit. 2. -1. Agent: Patent attorney Uchihara Kan (,
Claims (1)
集積回路において、前記放熱フィンが少くとも前記アル
ミナ基板との接着面に複数本のスリットを有することを
特徴とする混成集積回路。1. A hybrid integrated circuit having a structure in which a heat dissipation fin is attached to an alumina substrate, wherein the heat dissipation fin has a plurality of slits at least on a surface bonded to the alumina substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3068384A JPS60175499A (en) | 1984-02-21 | 1984-02-21 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3068384A JPS60175499A (en) | 1984-02-21 | 1984-02-21 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60175499A true JPS60175499A (en) | 1985-09-09 |
Family
ID=12310485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3068384A Pending JPS60175499A (en) | 1984-02-21 | 1984-02-21 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60175499A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4768215A (en) * | 1985-05-17 | 1988-08-30 | Hitachi Medical Corporation | X-ray generator with current measuring device |
| JP2014233908A (en) * | 2013-06-03 | 2014-12-15 | コニカミノルタ株式会社 | Optical writing device and image formation device |
-
1984
- 1984-02-21 JP JP3068384A patent/JPS60175499A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4768215A (en) * | 1985-05-17 | 1988-08-30 | Hitachi Medical Corporation | X-ray generator with current measuring device |
| JP2014233908A (en) * | 2013-06-03 | 2014-12-15 | コニカミノルタ株式会社 | Optical writing device and image formation device |
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