JPS60173871A - Mis type semiconductor memory device and manufacture thereof - Google Patents
Mis type semiconductor memory device and manufacture thereofInfo
- Publication number
- JPS60173871A JPS60173871A JP59029711A JP2971184A JPS60173871A JP S60173871 A JPS60173871 A JP S60173871A JP 59029711 A JP59029711 A JP 59029711A JP 2971184 A JP2971184 A JP 2971184A JP S60173871 A JPS60173871 A JP S60173871A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- memory device
- oxide film
- etching
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 6
- 239000004020 conductor Substances 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000001947 vapour-phase growth Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical group I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＭ Ｉ Ｓ型半導体記憶装置およびその製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor memory device and a manufacturing method thereof.
絶縁ゲート型電界効果トランジスタを用いた記憶装置と
して今日最も広く用いられているものは、−個のトラン
ジスタ及びそれに隣接して設けられた容量とによって構
成されたいわゆるパ１トランジスタ型パ記憶装置である
。本記憶装置に於てはトランジスタのゲートはワード線
に連結され、客足ゲート下に蓄積された電荷の有無が反
転情報に対応する。１トランジスタ記憶装置に於ては電
荷蓄積部の容量Ｃ８はＣ３＝εＳ／ｌで与えられる。The most widely used storage device today that uses insulated gate field effect transistors is the so-called 1-transistor type 1-transistor storage device, which is composed of - transistors and a capacitor provided adjacent to them. . In this memory device, the gate of the transistor is connected to a word line, and the presence or absence of charge accumulated under the gate corresponds to inversion information. In a one-transistor memory device, the capacitance C8 of the charge storage section is given by C3=εS/l.
ここでεは絶縁膜の訪電率、Ｓは電極面積、ｔは絶縁膜
の厚さである。Here, ε is the current visiting rate of the insulating film, S is the electrode area, and t is the thickness of the insulating film.
近年、半導体装置の集積化の進展に伴い素子の微細化が
要請されている。ｌトランジスタ型記憶装置の微細化に
於ては情報判定の容易さ、放射線への耐性を維持するた
めに、Ｃ６の値の減少は極力避けなければならない。こ
のため、従来技術に於ては絶縁膜の膜厚を薄くすること
によってＣ８の低下を抑えていたが、この方法も薄膜化
に伴うピンホール密度の増加、或いは制圧の低下等のた
めに必ずしも充分な方法とは言えなかった。In recent years, as the integration of semiconductor devices has progressed, there has been a demand for miniaturization of elements. When miniaturizing an l-transistor type memory device, a decrease in the value of C6 must be avoided as much as possible in order to maintain ease of information determination and resistance to radiation. For this reason, in the conventional technology, the decrease in C8 was suppressed by reducing the thickness of the insulating film, but this method also does not always work because of the increase in pinhole density or the decrease in pressure suppression due to the thinning of the film. It was not a sufficient method.
本発明は、半導体基板内に溝を形成し、政情に多数の突
起を形成することによって表面積の増大をはかり、素子
面積の増加を伴わずにＣ５を増加させる方法を提供する
ものである。本発明に於ては等方性エツチングと異方性
エツチングを組合わせることにより、基板内に多数の突
起を持りた清を形成することができる。The present invention provides a method of increasing C5 without increasing the device area by increasing the surface area by forming grooves in a semiconductor substrate and forming a large number of protrusions. In the present invention, by combining isotropic etching and anisotropic etching, it is possible to form a substrate having a large number of protrusions within the substrate.
次に、図面を用いて本発明の一実施例について説明する
。本実施例ではｎチャネルＭへ１０８トランジスタを用
いた例について説明する。Next, one embodiment of the present invention will be described using the drawings. In this embodiment, an example in which 108 transistors are used for n-channel M will be explained.
第１図に於てｐ型シリコン基板１上には既に通常の選択
酸化工程により厚いフィールド絶縁１１ａ２が形成きれ
ている。次に全面にシリコン酸化膜３を気相成長法で被
着し、フォトエツチング工程により開口を形成する。次
に、第２図に示す様に異方性エツチングにより基板内に
溝全形成する１、異方性エツチングとしては例えばＣＣ
ｌ４カスを用いた反応性イオンエツチングが良い。次に
、酸化により溝内に酸化膜４を成長する。In FIG. 1, a thick field insulator 11a2 has already been formed on a p-type silicon substrate 1 by a normal selective oxidation process. Next, a silicon oxide film 3 is deposited on the entire surface by vapor phase growth, and an opening is formed by a photoetching process. Next, as shown in FIG. 2, the entire groove is formed in the substrate by anisotropic etching.
Reactive ion etching using l4 residue is good. Next, an oxide film 4 is grown in the trench by oxidation.
次に、第３図に示す様に、異方性エツチングにより、溝
底面部のみの酸化膜を除去した後、等方性エツチングを
行い、溝側面方向に窪み１ｏを形成する。前記異方性エ
ツチングとしては例えばＣＰ’ ４ ＋ Ｈｚガスを用
いた反応性イオンエツチングが、また等方性エツチング
としてはＣＦ４＋０２ガスを用いたプラズマエツチング
が適当である。次に、再び酸化を行い、異方性エツチン
グと等方性エツチングを交互に繰り返すことにより第４
図に示す様な側面に突起１０を持った溝１１を形成する
ことができる。Next, as shown in FIG. 3, after removing the oxide film only on the bottom surface of the trench by anisotropic etching, isotropic etching is performed to form a depression 1o in the direction of the side surface of the trench. For example, reactive ion etching using CP' 4 + Hz gas is suitable as the anisotropic etching, and plasma etching using CF4+02 gas is suitable as the isotropic etching. Next, oxidation is performed again, and anisotropic etching and isotropic etching are repeated alternately to obtain a fourth
A groove 11 having a protrusion 10 on the side surface as shown in the figure can be formed.
次に第５図に示す様に、不純物をドーグした多結晶シリ
コンを全面に被着する。この際、気相成長時の圧力を低
下することにより、多結晶シリコンを溝側面の窪み内ま
で侵入させることができる。Next, as shown in FIG. 5, polycrystalline silicon doped with impurities is deposited over the entire surface. At this time, by lowering the pressure during vapor phase growth, the polycrystalline silicon can penetrate into the depression on the side surface of the groove.
次にフォトエツチングにより前記多結晶シリコンからな
る容量電極６を容量誘電体膜４，５′上に形体し、同様
に前記多結晶シリコンからなるゲート電極７ゲート絶縁
膜５上に形成し、ｎ型不純物をイオン注入して、ソース
、ドレイン層８（一方はビット線となる）を形成し、全
面を酸化膜で被榎した後コンタクト開口を形成しワード
線電極９を形成して記憶装置を完成できる。Next, a capacitor electrode 6 made of the polycrystalline silicon is formed on the capacitor dielectric films 4 and 5' by photoetching, and a gate electrode 7 made of the polycrystalline silicon is similarly formed on the gate insulating film 5. Impurity ions are implanted to form source and drain layers 8 (one of which will become a bit line), the entire surface is covered with an oxide film, contact openings are formed, and word line electrodes 9 are formed to complete the memory device. can.
第１図乃至第５図は本発明の一実施例の製造工程順に説
明するための断面図である。
尚、図に於て、１・°“・・・ｐ型シリコン基板、２・
・・・・・フィールド酸化膜、３・・・・・・シリコン
酸化膜、４・・・パ°シリコン酸化膜（誘電体膜）、５
・・・・・・シリコン酸化膜（ゲート絶縁膜）、５′・
・・・・・シリコン酸化膜（誘電体膜）、６・・・・・
・容童側凱 ７・・・・・・ゲート電極、８−＝−゛ソ
ース、ドレイン領域、９パ゛°°ワード線電極である。
第１ 図
一？
牛２１７１
第 ３ 区
／／
第４ 図 ′。１０FIGS. 1 to 5 are cross-sectional views for explaining the manufacturing process order of an embodiment of the present invention. In the figure, 1.°"...p-type silicon substrate, 2.
...field oxide film, 3... silicon oxide film, 4... silicon oxide film (dielectric film), 5
・・・・・・Silicon oxide film (gate insulating film), 5'・
...Silicon oxide film (dielectric film), 6...
・Yodo side Gai 7...Gate electrode, 8-=-' source, drain region, 9' word line electrode. 1st figure 1? Cow 2171 District 3 // Figure 4'. 10
Claims (2)
トランジスタおよびそれに隣接して設けられた容量を情
報単位とする記憶装置に於て、容量部のシリコン基板表
面から内部に向って溝を形成し、政情は更に溝側面と垂
直方向に一個或いは複数個の分枝を有し、前記溝内面は
絶縁膜で被接され、前記溝内部は導電性物質で充満され
、前記導電性物質をもって容量部の電極となすことを特
徴としたＭＩＳ型半専体記憶装置。(1) In a memory device whose information unit is one insulated gate field effect transistor on a silicon substrate and a capacitor provided adjacent to it, a groove is formed inward from the surface of the silicon substrate in the capacitive part. However, the groove further has one or more branches in a direction perpendicular to the side surface of the groove, the inner surface of the groove is covered with an insulating film, the inside of the groove is filled with a conductive material, and the conductive material increases the capacitance. An MIS type semi-dedicated storage device characterized by having a central electrode.
ランジスタおよびそれに隣接して設けられた容量を情報
単位とするＭＩＳ型半導体記憶装置の製造方法に於て、
前記半導体基板上をマスク材で被覆する工程と、前記マ
スク材の所定部に計ｊ口を設ける工程と、異方性エツチ
ングにより前記開口部周縁から半導体基板表面に垂直方
向に側壁を有する溝を形成する工程と、溝内部をマスク
利で被覆する工程と、異方性エツチングにより溝底部の
前記マスク材のみを除去する工程と、等方性エツチング
により前記溝（１１１１面に捕みを形成する工程と、再
びマスク材を溝内部に被覆する工程と、異方性エツチン
グにより溝底部のマスク材のみを除去する工程と、等方
性エツチングにより溝側面に江みを設ける工程とを続け
−ｒ ＜り返すことにより、側面に単−或いは複数個の
窪みを有する溝を形成する工程と、該構内面に絶縁膜を
被着する工程と、該溝内部を導電性物質で充満させる工
程を有することを特徴としたＭＩＳ型半導体記憶装置の
製造方法、１(2) - In a method for manufacturing an MIS semiconductor memory device in which an insulated gate field effect transistor on a conductive semiconductor substrate and a capacitor provided adjacent thereto are used as information units,
A step of covering the semiconductor substrate with a mask material, a step of providing a hole in a predetermined portion of the mask material, and a step of forming a groove having a side wall in a direction perpendicular to the surface of the semiconductor substrate from the periphery of the opening by anisotropic etching. a step of covering the inside of the groove with a masking material; a step of removing only the mask material at the bottom of the groove by anisotropic etching; and a step of forming a trap in the groove (1111 plane) by isotropic etching. This step is followed by the step of again covering the inside of the groove with the mask material, the step of removing only the mask material at the bottom of the groove by anisotropic etching, and the step of providing a recess on the side surface of the groove by isotropic etching. <By repeating the method, the method includes a step of forming a groove having one or more depressions on the side surface, a step of depositing an insulating film on the surface of the structure, and a step of filling the inside of the groove with a conductive material. A method for manufacturing an MIS type semiconductor memory device characterized by the following: 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029711A JPS60173871A (en) | 1984-02-20 | 1984-02-20 | Mis type semiconductor memory device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029711A JPS60173871A (en) | 1984-02-20 | 1984-02-20 | Mis type semiconductor memory device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60173871A true JPS60173871A (en) | 1985-09-07 |
Family
ID=12283690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59029711A Pending JPS60173871A (en) | 1984-02-20 | 1984-02-20 | Mis type semiconductor memory device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60173871A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4906590A (en) * | 1988-05-09 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a trench capacitor on a semiconductor substrate |
| JPH0433377A (en) * | 1990-05-30 | 1992-02-04 | Shiyoudenriyoku Kosoku Tsushin Kenkyusho:Kk | Manufacture of semiconductor device |
| US5153813A (en) * | 1991-10-31 | 1992-10-06 | International Business Machines Corporation | High area capacitor formation using dry etching |
| US5155657A (en) * | 1991-10-31 | 1992-10-13 | International Business Machines Corporation | High area capacitor formation using material dependent etching |
| US9927182B2 (en) | 2012-05-22 | 2018-03-27 | Valeo Systemes Thermiques | Heat exchanger tube, heat exchanger tube bundle, heat exchanger comprising such a bundle and method for producing a plate of a heat exchanger tube |
-
1984
- 1984-02-20 JP JP59029711A patent/JPS60173871A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4906590A (en) * | 1988-05-09 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a trench capacitor on a semiconductor substrate |
| JPH0433377A (en) * | 1990-05-30 | 1992-02-04 | Shiyoudenriyoku Kosoku Tsushin Kenkyusho:Kk | Manufacture of semiconductor device |
| US5153813A (en) * | 1991-10-31 | 1992-10-06 | International Business Machines Corporation | High area capacitor formation using dry etching |
| US5155657A (en) * | 1991-10-31 | 1992-10-13 | International Business Machines Corporation | High area capacitor formation using material dependent etching |
| US9927182B2 (en) | 2012-05-22 | 2018-03-27 | Valeo Systemes Thermiques | Heat exchanger tube, heat exchanger tube bundle, heat exchanger comprising such a bundle and method for producing a plate of a heat exchanger tube |
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