JPS60164840A - Register save/recover system - Google Patents
Register save/recover systemInfo
- Publication number
- JPS60164840A JPS60164840A JP2110384A JP2110384A JPS60164840A JP S60164840 A JPS60164840 A JP S60164840A JP 2110384 A JP2110384 A JP 2110384A JP 2110384 A JP2110384 A JP 2110384A JP S60164840 A JPS60164840 A JP S60164840A
- Authority
- JP
- Japan
- Prior art keywords
- register
- save
- arrow
- register save
- contents
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Executing Machine-Instructions (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明はレジスタセーブ、リカバ一方式、特に蓄積制御
プログラムシステムにおける中央制御装置の各種レジス
タ自答のセーブ、リカバ一方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a register save/recovery method, and particularly to a register save/recovery method for various registers of a central control unit in an accumulation control program system.
（従来技術）
従来、レジスタのセーブ、リカバーはロード又はストア
命令を用いてレジスタの内容を主記憶装置の特定のエリ
アへストア（セーブノ、又はロード（リカパーンし、且
つ、レジスタが複数個の場合その個数回分、ロード又は
ストア命令を繰り返すことによ多行なっていた。(Prior art) Conventionally, saving and recovering registers uses a load or store instruction to store the contents of a register to a specific area of the main memory. This was done by repeating the load or store command several times.
ロード、ストア命令の実行には通常、命令７エヅチと、
データ転送の２回、中央制御装置と主記憶装置との間で
情報のやシ取りがある。従ってｎ個のレジスタのセーブ
、ストアにはＺＸｎ回中央制御装置と主記憶装置のや９
取シが必要とな９、本来の仕事であるデータ処理が遅く
なるという欠点があった。To execute load and store instructions, the instruction 7 is usually used.
During data transfer, information is exchanged between the central controller and the main memory twice. Therefore, saving and storing n registers requires ZXn times in the central controller and main memory.
The drawback was that the data processing, which is the original job, was slowed down.
（発明の目的）
本発明は中央制御装置内の汎用レジスタ群ｔシフトメモ
リを用いて３次元的に配置し、３次元のうち１次元ｔレ
ジスタのセーブ、リカバーとして用いることにより％セ
ーブ、リカバー命令実行時にレジスタの内容を主記憶装
置へ転送する時間を不要とし、中央制御装置のデータ処
理速度を向上させるレジスタのセーブ、リカバ一方式を
提供す ゛ることにある。(Object of the Invention) The present invention uses a general-purpose register group t-shift memory in a central control unit to arrange it three-dimensionally, and uses it as a save and recover for one dimension of the three-dimensional t-register. The object of the present invention is to provide a register saving and recovery system that eliminates the need for transferring the contents of registers to the main memory during execution and improves the data processing speed of a central control unit.
（発明の構成）
本発明によると中央制御装置内の汎用レジスタ群ｔシフ
トメモリを用いてレジスタ番号方向、レジスタのビット
方向、レジスタセーブ方向の３次元的な配置に構成し、
レジスタセーブ又はリカバリー命令により得られる情報
により指定レジスタ又はレジスタ群の全ビットの内容ｔ
レジスタセーブ方向またはその逆方向に７７トさせるこ
とｔ特徴トスるレジスタセーブ、リカバ一方式が得られ
る。(Structure of the Invention) According to the present invention, a general-purpose register group t-shift memory in the central control unit is used to configure a three-dimensional arrangement in the register number direction, register bit direction, and register save direction,
The contents of all bits of the specified register or register group are determined by the information obtained by the register save or recovery command.
By tossing the register in the register save direction or the opposite direction, a register save and recovery method can be obtained.
（実施例］
次に図面上参照して、本発明の実施例につ−て説明する
。第１図は本発明の一実施例を示すブロック図である。(Embodiment) Next, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing an embodiment of the present invention.
１０は汎用レジスタ群であ夛、シフトメモリｔレジスタ
番号方向ｘ（ＲＱ〜几ｎハレジスタのビット方向ｙ （
Ｑ ｂｉｔ〜ｍｂｉｔＪ、レジスタのセーブ方向Ｚ（０
〜ｅ回りの３次元的に配置することで構成される。２０
は汎用レジスタ群ｌのレジスタセーブ方向２のＯ番目の
面上平面の、３１はレジスタ几Ｏの０ビツトがセーブさ
れた状態を示す。ＲＱ、 Ｒ１，・・・几ｎは各々汎用
レジスタの／１６０．Ａｔ、４ｎ’に、０，１〜ｍは各
レジスタのビｌト番号’ｔ−，０，１〜ｅはセーブリカ
バーの度合を示す連番である。10 is a group of general-purpose registers, shift memory t register number direction x (RQ ~ 几n register bit direction y (
Q bit~mbitJ, register save direction Z (0
It is constructed by arranging it three-dimensionally around ~e. 20
is a plane on the O-th surface in the register save direction 2 of general-purpose register group l, and 31 indicates the state in which the 0 bit of register O is saved. RQ, R1, . . . n are the /160. At, 4n', 0, 1 to m are bit numbers of each register, and t-, 0, 1 to e are serial numbers indicating the degree of save recovery.
次にこの実施例の動作を説明する。中央制御装置は通常
状態でのレジスタ使用はレジスタセーブ方向２のθ番目
の面２０のみｔ用いている。今、各レジスタの内容がセ
ーブ方向２のＯ番目の面２０に示すとおシに（具体的に
はＲＯの内容が０゜１、・Ｏ，几ｌの内容が１＋ Ｏｒ
・ｓ、Ａｎが０゜０、・・・０）なった時、レジスタ
セーブ命令を受取ったとする。制御部はレジスタセーブ
命令を解読して、セーブすべきレジスタ又はレジスタ群
に対してシフト信号を送出する。Next, the operation of this embodiment will be explained. The central control unit uses only the θth plane 20 in the register save direction 2 in the normal state. Now, let us say that the contents of each register are shown on the O-th surface 20 in the save direction 2 (specifically, the contents of RO are 0゜1, the contents of ・O, 几l are 1+ Or
- Suppose that a register save instruction is received when s and An become 0°0, . . . 0). The control unit decodes the register save command and sends a shift signal to the register or register group to be saved.
その時は汎用レジスタ群ＩＯ２はシフトタイプのビット
のみに着目してみると、レジスタ几０の０ビツトの部分
３０に示すパターンから、レジスタＲＯの０ビヤトがセ
ーブされた状態３１のパターンに変わり、レジスタセー
ブ方向２の０は空の状態となる。従ってレジスタセーブ
方向２の０番目の面２０は新たな状態で使用されうる。At that time, if we focus only on the shift type bits in the general-purpose register group IO2, the pattern shown in the 0 bit part 30 of register 0 changes to the pattern 31 in which the 0 bit of register RO is saved, and the register 0 in save direction 2 is empty. Therefore, the 0th plane 20 in the register save direction 2 can be used in a new state.
即ち、レジスタセーブされた仁とになる。In other words, it becomes a register-saved value.
リカバーの場合は同様の手順で、単にシフト方向全レジ
スタセーブ方向２の逆にすれば良い。In the case of recovery, the same procedure can be used by simply reversing the shift direction from the all register save direction 2.
以上に示すようにレジスタのセーブリカバーに主記憶装
置ｔ−Ｏｅ用せず、且つ、一度に最大ロレジスタ分セー
ブリカバーできるので、レジスタセーブ、リカバ一時開
音大幅に短縮することができる。As described above, the main memory t-Oe is not used for register save/recovery, and the maximum number of registers can be saved/recovered at one time, so that the register saving/recovery temporary opening time can be significantly reduced.
（発明の効果）
本発明は、以上に示すように、主記憶装置を使わずに、
且つ、複数のレジスタを同時にセーブ。(Effects of the Invention) As shown above, the present invention provides
Moreover, multiple registers can be saved at the same time.
リカバーで１！、その結果レジスタセーブ、リカバ５−
一に要する時間６（短縮され、処理能力が向上する効果
がある。1 in recovery! As a result, the time required for register save and recovery 5-1 is shortened and the processing capacity is improved.
第１図は本発明において用いる汎用レジスタ群の一実施
例を示す図である。
ｌＯ・・・・・・汎用レジスタ群、２０・・・・・・レ
ジスタセーブ方向の０番目の面、３０・・・・・・レジ
スタ１１１ＯのＱｂｉｔが未セーブの状態％ ３１・・
・・・・レジスタ８０の□ ｂｔｔがセーブされた状態
。
６−FIG. 1 is a diagram showing one embodiment of a general-purpose register group used in the present invention. lO...General-purpose register group, 20...0th plane in register save direction, 30...Qbit of register 111O is in unsaved state % 31...
...Register 80 □ btt is saved. 6-
Claims (1)
用いてレジスタ番号方向、レジスタのビート方向、レジ
スタセーブ方向の３次元的な配置Ｋ１１ｌ成し、レジス
タセーブ又はリカバー命令によル得られる情報により指
定レジスタ又はレジスタ群の全ビットの内容ｔレジスタ
セーブ方向またはその逆方向にシフトさせることｔ特徴
とするレジスタセーブ、リカバ一方式。Using the general-purpose register #t shift type memory of the central control unit, a three-dimensional arrangement K11l is created in the register number direction, register beat direction, and register save direction, and the designated register is created using the information obtained by the register save or recover command. Alternatively, a register save/recover method characterized by shifting the contents of all bits of a register group in the register save direction or the opposite direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2110384A JPS60164840A (en) | 1984-02-08 | 1984-02-08 | Register save/recover system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2110384A JPS60164840A (en) | 1984-02-08 | 1984-02-08 | Register save/recover system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60164840A true JPS60164840A (en) | 1985-08-27 |
Family
ID=12045535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2110384A Pending JPS60164840A (en) | 1984-02-08 | 1984-02-08 | Register save/recover system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60164840A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0421032A (en) * | 1990-05-14 | 1992-01-24 | Matsushita Electric Ind Co Ltd | Multi-task executing device |
| US7117319B2 (en) | 2002-12-05 | 2006-10-03 | International Business Machines Corporation | Managing processor architected state upon an interrupt |
| US7272664B2 (en) | 2002-12-05 | 2007-09-18 | International Business Machines Corporation | Cross partition sharing of state information |
| US7493478B2 (en) | 2002-12-05 | 2009-02-17 | International Business Machines Corporation | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states |
-
1984
- 1984-02-08 JP JP2110384A patent/JPS60164840A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0421032A (en) * | 1990-05-14 | 1992-01-24 | Matsushita Electric Ind Co Ltd | Multi-task executing device |
| US7117319B2 (en) | 2002-12-05 | 2006-10-03 | International Business Machines Corporation | Managing processor architected state upon an interrupt |
| US7272664B2 (en) | 2002-12-05 | 2007-09-18 | International Business Machines Corporation | Cross partition sharing of state information |
| US7493478B2 (en) | 2002-12-05 | 2009-02-17 | International Business Machines Corporation | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states |
| US7849298B2 (en) | 2002-12-05 | 2010-12-07 | International Business Machines Corporation | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states |
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