JPS60163512A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To attain the constitution only with an NPN transistor (Tr) attaining easily a high frequency gain band width product in case of circuit integration by using a differential amplifier in place of an active load. CONSTITUTION:When the differential amplifier comprising NPNTrs 8, 9 is taken as an ideal voltage amplifier with infinite gain, both base potentials of the Trs 8, 9 are mad equal by the feedback operation of a load 10, a Tr11 and resistors 12, 13. An output current i0 when the resistance value of the resistors 12, 13 is equal becomes a current difference between collector currents i1, i2 of the Trs 1, 2 and the amplifier acts like a current mirror circuit. As a result, an active load having been constituted with PNPTrs is constituted with NPNTrs, and a low frequency gain band width product with the PNPTr and a current gain decreased at a large current region are utilized in case of circuit integration.

Description

【発明の詳細な説明】 （技術分野） 本発明は周波数特性、電流特性の改善された能動負荷１
に有する差動増巾回路を提供するものでおり、かつ、集
積回路化に適した差動増巾回路を提供するものである。Detailed Description of the Invention (Technical Field) The present invention provides an active load 1 with improved frequency characteristics and current characteristics.
The present invention provides a differential amplification circuit having the following characteristics, and also provides a differential amplification circuit suitable for integration into an integrated circuit.

（従来技術） 従来より、集積回路においては、内部素子、特に抵抗、
トランジスタの整合が良くとれることから、規動増巾器
が多用されている。特に、高利得を要求される回路等に
おいては差動増巾器の負荷として能動負荷？用いる例が
多い。このような場合、差動増巾器には、ＮＰＮ）ラン
ジスタケ１能動負荷にｒ［ＰＮＰ　トランジスタを（も
しくは逆の組合せン用いて回路を構成してきた。しかし
、かかる回＃５構成においては、ｔ￥ｉに集積回路の場
合、一般にＰＮＰ　）ランジスタの周波数利得帯域中横
７ＴがＮＰＮ　トランジスタの周波数利得帯域中＠ｆＴ
に比べ低いため、充分な周波数特性を得ることが難しく
、高周波の回路には用いられなかった。さらに電流特性
においても、一般にＰＮＰ　）ランジスタの方が、高電
流領域での電流利得ｈｆｅがとりにくいため使用に制限
を受けるという欠点があった。(Prior Art) Traditionally, in integrated circuits, internal elements, especially resistors,
Drive amplifiers are often used because they allow good transistor matching. In particular, in circuits that require high gain, use an active load as a differential amplifier load. There are many examples where it is used. In such a case, a differential amplifier has been constructed using an active load of an NPN transistor and an r[PNP transistor (or the reverse combination). However, in such a circuit #5 configuration, In the case of an integrated circuit, it is generally PNP (7T horizontally in the frequency gain band of a transistor) is NPN in the frequency gain band of a transistor @fT
Because it is low compared to , it is difficult to obtain sufficient frequency characteristics, and it was not used in high-frequency circuits. Furthermore, in terms of current characteristics, PNP transistors generally have a disadvantage in that their use is limited because it is difficult to obtain a current gain hfe in a high current region.

以下図面をもとにさらに詳細に説明を行う。A more detailed explanation will be given below based on the drawings.

第１図はかかる回路の従来例である。ＮＰＮ　）２ンジ
スタ１，２はエミッタが共通接続され、両ベース間が入
力端子４に接続された差動増巾器を形成し、エミッタ共
通接続点には定電流源３が接続されている。ＮＰＮ　）
ランジスタ１のコレクタには、ＰＮＰト？ンジスタ５の
コレクタ、ベースとＰＮＰ　）ランジスタロのベースが
接続され、ＮＰＮトランジスタ２のコレクタとＰＮＰ　
）　９ンジスタ６のコレクタとは共通接続されるととも
に出力端子７に接続されて釣る。またＰＮＰ　トランジ
スタ５と６のエミッタは基準電源ＶＱＱｉＣ接続されて
いる。FIG. 1 shows a conventional example of such a circuit. The NPN)2 transistors 1 and 2 have their emitters connected in common, and form a differential amplifier in which both bases are connected to an input terminal 4, and a constant current source 3 is connected to the common emitter connection point. NPN)
Is there a PNP in the collector of transistor 1? The collector and base of transistor 5 are connected to the PNP) The base of transistor 5 is connected, and the collector and base of NPN transistor 2 are connected to PNP
) 9 are connected in common to the collectors of the registers 6 and also connected to the output terminal 7. Furthermore, the emitters of PNP transistors 5 and 6 are connected to the reference power supply VQQiC.

かかる構成においては、ＰＮＰ　トランジスタ５゜６は
ＮＰＮ　トランジスタ１．２および定電流源３よりなる
差動増巾器の能動負荷として働き入力端子４に印加され
た差動電圧が出力端子７に電流出力として取り出される
。しかし、本構成では、前述のごとく能動負荷として用
いられるトランジスタ５，６がＰＮＰ極性のため、ｈＦ
Ｆｆ−電流特性の伸びが悪く、小を流領域でしか用いら
れないことと周波数利得帯域中横ｆＴが低いことから高
周波領域での使用に制限があるという欠点があった。In this configuration, the PNP transistor 5.6 acts as an active load of the differential amplifier consisting of the NPN transistor 1.2 and the constant current source 3, and the differential voltage applied to the input terminal 4 is outputted as a current to the output terminal 7. is extracted as. However, in this configuration, since the transistors 5 and 6 used as active loads have PNP polarity as described above, hF
The Ff-current characteristic has poor growth, so it can only be used in the small current range, and the transverse fT in the frequency gain band is low, which limits its use in the high frequency range.

（発明の目的） 本発明の目的は、上述の欠点２取り除き、ＩＣ化に際し
て高い周彼数利得帯域中＠ｆＴを出し易いＮＰＮ　トラ
ンジスタの今で４ｖ１１成される差動増巾回路を提供す
るものでおる〇 （発明の構成） 本発明の差動増巾回路は、ｓｔＩ記能動負荷のかわりに
第２の差動増巾器を用ｉることにより、従来例と等価な
能動負荷を実現したものである。(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawback 2 and to provide a differential amplification circuit made of 4v11 NPN transistors that can easily produce @fT in a high frequency gain band when integrated into an IC. 〇 (Structure of the invention) The differential amplifier circuit of the present invention realizes an active load equivalent to that of the conventional example by using a second differential amplifier instead of the active load stI. It is something.

（笑施例） 以下、図面をもとに本発明の差動増巾回路を説明する。(lol example) Hereinafter, the differential amplifier circuit of the present invention will be explained based on the drawings.

本発明の一笑施例を示す第２図によれば、第１図と同じ
素子には同一の番号を付している。第１゜第２のＮＰＮ
　トランジスタ１．２よりなる第１の差動増巾器と第３
．第４のＮＰＮ　）ランジスタ８゜９よＶなる第２の差
動増巾器とを有し第３ＯＮＰＮトランジスタ８のコレク
タに負荷１０ｆｔ接続するとともにコレクタ接地形式の
第５のＮＰＮ　トランジスタ１１のベースｆｃ接続し、
第５のＮＰＮ　）ランジスタ１１のエミッタと第１ＯＮ
ＰＮ）：ｌｙンジスタｌのコレクタとの間に第１の抵抗
１２を、同じく第５のＮＰＮ　）ンンジスタ１１のエミ
ッタと謁２のＮＰＮ　トランジスタ２のコレクタとの間
に第２の抵抗１３をそれぞれ接続し、かつ第１のＮＰＮ
　）ランジスタｌのコレクタと、第１の抵抗１２の共通
接続点に第３のＮＰＮ　）ランジスタ８のベースｆｃ嶺
続し、第２のＮＰＮ　トランジスタ２のコレクタと第２
の抵抗１３との共通接続点を第４のＮＰＮ　）ランジス
メ９のベースに接続し、第１の差動増巾器を構成する２
つのＮＰＮ　ト、７ンジスタ１，２のベース間に入力を
与え、第２のＮＰＮトランジスタ２と第２の抵抗１３と
第４のトランジスタ９０ベースとの共通接続点（出方端
子７）より出力を取り出す。According to FIG. 2, which shows a simple embodiment of the present invention, the same elements as in FIG. 1 are given the same numbers. 1st゜2nd NPN
A first differential amplifier consisting of transistors 1.2 and a third
．． A fourth NPN) transistor 8°9 has a second differential amplifier of V and a load of 10 ft is connected to the collector of the third ONPN transistor 8, and the base of a fifth NPN transistor 11 of collector common type is connected to fc. death,
5th NPN) Emitter of transistor 11 and 1st ON
A first resistor 12 is connected between the collector of the fifth NPN transistor 1 and a second resistor 13 is connected between the emitter of the fifth NPN transistor 11 and the collector of the NPN transistor 2 of the audience 2. and the first NPN
) A third NPN is connected to the common connection point between the collector of the transistor l and the first resistor 12.) A third NPN is connected to the base fc of the transistor 8, and a second NPN is connected to the collector of the transistor
The common connection point with the resistor 13 of
An input is applied between the bases of the two NPN transistors 1 and 7, and an output is output from the common connection point (output terminal 7) between the second NPN transistor 2, the second resistor 13, and the base of the fourth transistor 90. Take it out.

かかる構成においてＮＰＮ　ト、７ンジスタ１，２で構
成される第１の増巾器は第り図の従来の増巾器と同様の
動作全行い、入力電圧によりトランジスタｌとトランジ
スタ２のコレクタにｉ□＋’２なる電流を生ずる。In this configuration, the first amplifier composed of NPN transistors 1 and 7 operates in the same manner as the conventional amplifier shown in FIG. □Produces a current of +'2.

次に説明の簡単のために、　ＮＰＮ　トランジスタ８．
９で構成される第２の差動増巾器を利得無限大の理想電
圧増巾器とすれば、トランジスタ８とトランジスタ９の
両ベース電位は負荷１０．トランジスタ１１．抵抗１２
．１３の帰還動作により等しくなる。従って抵抗１２，
１３の抵抗値をそれぞれ’１２　＋　Ｒ１３を抵抗１２
．１３の両端に生ずる電圧ｔそれぞれ”１２　＃　ｖ１
３とし、出力端に流出する篭流をｉｏとすると υ１２３υ１３　”’　”’　”’　１１１ｕ１ｚ＝　
Ｒ１２１ｌ＝（２１ ｖ１ａ＝Ｒｔａ（ｉ２＋ｉｏ）　＝１３１となる。ｆｉ
ｌ　、　＋２１　、　＋３１式より１３ とな’）　Ｒ１２”ＲｌＢ　の時、出力電流ｉｏは　ト
ランジスタ１，２のコレクタ電流’１　ｔ　’２の差電
流となり第１図のカレントミラー回路と同様の働きをす
る。Next, for ease of explanation, an NPN transistor 8.
9 is an ideal voltage amplifier with infinite gain, the base potentials of both transistors 8 and 9 are equal to the load 10.9. Transistor 11. resistance 12
．． It becomes equal due to the feedback operation of 13. Therefore, the resistor 12,
Each resistance value of 13 is '12 + R13 is resistance 12
．． The voltage t generated at both ends of 13 is 12 # v1, respectively.
3 and the cage flow flowing out to the output end is io, υ123υ13 ”'”'”' 111u1z=
R121l=(21 v1a=Rta(i2+io) =131.fi
13 from equations 1, +21, and +31') When R12''RlB, the output current io becomes the difference current between the collector currents '1 and t'2 of transistors 1 and 2, and functions similarly to the current mirror circuit in Figure 1. do.

従って、従来ＰＮＰ型上２ンジスタで構成されていｆＣ
ｖ、動負荷をＮＰＮ）２ンジスタで構成できるため、前
述のＩＣ化の際ＰＮＰ）７ン°ジスタの持っている低い
周涙数利得帯域中横ｆＴｙ大電流領域で低下するｔｆｉ
利得のｈＦＢＫ関係なく使用することが可能となる。Therefore, conventionally, fC
v, the dynamic load can be configured with NPN)2 transistors, so when implementing the above-mentioned IC, the tfi, which decreases in the lateral fTy large current region, is reduced in the low circumferential tear number gain band of the PNP)7 transistors.
It can be used regardless of hFBK gain.

尚、本説明には第１の差動増巾器として単一の差動増巾
器の場合について説明を行ったが、第１の差動増巾器と
して第３の差動増巾器が並列に接続された、例えは二重
平衡形差１ＥＩＩ増中器を使用しても同様の効果かめる
ことは明らかである。In addition, although this explanation has been made regarding the case where a single differential amplifier is used as the first differential amplifier, it is also possible to use a third differential amplifier as the first differential amplifier. It is clear that a similar effect can be obtained by using, for example, double-balanced differential 1EII intensifiers connected in parallel.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例を説明する回路図、第２図は本発明の一
実施例を説明する回路図でめる。 １．２，５，６，８．９・・・・・・トランジスタ３．
１４・・・・・・定電流源 ４・・・・・・入力端子 ７・・・・・・出力端子 ｌＯ・・・・・・負荷 １２．１３・・・・・・抵抗。FIG. 1 is a circuit diagram for explaining a conventional example, and FIG. 2 is a circuit diagram for explaining an embodiment of the present invention. 1.2, 5, 6, 8.9...transistor 3.
14... Constant current source 4... Input terminal 7... Output terminal lO... Load 12.13... Resistance.

Claims (1)

【特許請求の範囲】[Claims] 第１．第２のトランジスタよりなる第１の差動増巾器と
第３．第４のトランジスタよりなる第２の差動増巾器と
全有し、前記第３のトランジスタのコレクタに負荷を接
続するとともにコレクタ接地形式の第５のトランジスタ
のベースを接続し、前記第５のトランジスタのエミッタ
と前記第１のトランジスタのコレクタ間に第１の抵抗を
、同じく前記第５のトランジスタのエミッタと前記第２
のトランジスタのコレクタ間に第２の抵抗をそれぞれ接
続し、かつ第１のトランジスタのコレクタと第１の抵抗
の共通接続点に第３のトランジスタノヘースを接続し、
第２のトランジスタのコレクタと第２の抵抗の共通１＃
：読点を第４のトランジスタのベースに接続し、前記第
ｌおよび第２のトランジスタのベース間に入力信号ケ与
え、前記第２のトランジスタと第２の抵抗と第４のトラ
ンジスタのベースの共通接続点より出力を取り出すこと
全特徴とする差動増巾回路。1st. a first differential amplifier consisting of a second transistor; a third . a second differential amplifier consisting of a fourth transistor, a load is connected to the collector of the third transistor, and a base of a fifth transistor of common collector type is connected; A first resistor is provided between the emitter of the transistor and the collector of the first transistor, and a first resistor is also provided between the emitter of the fifth transistor and the collector of the first transistor.
A second resistor is connected between the collectors of the transistors, and a third transistor resistor is connected to a common connection point between the collector of the first transistor and the first resistor,
Common 1# between the collector of the second transistor and the second resistor
: Connecting a reading point to the base of a fourth transistor, applying an input signal between the bases of the first and second transistors, and common connection of the second transistor, the second resistor, and the bases of the fourth transistor. A differential amplification circuit characterized by extracting output from a single point.