JPS60149168A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60149168A JPS60149168A JP59244428A JP24442884A JPS60149168A JP S60149168 A JPS60149168 A JP S60149168A JP 59244428 A JP59244428 A JP 59244428A JP 24442884 A JP24442884 A JP 24442884A JP S60149168 A JPS60149168 A JP S60149168A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- film
- layer
- self
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置に関するものである。特に、不揮
発性メモリの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device. In particular, it relates to a method of manufacturing nonvolatile memory.
従来、導体２層構造を持つ半導体メモリ素子は、第１図
の様な第１導体層１を第２導体層２でおおった形か、又
は第２図の様に第２導体層２のソース・ドレイン方向に
平行な幅Ｗ。が、第１導体ｍ】の幅Ｗと較べて小さくな
った形をしていた。第１図（ａ）、 （ｂ）、及び（ｃ
）は従来からのメモリ素子の平面図、ソースドレインに
直角の方向のＡ−Ａ’断面図、ソースドレイン１２平行
方向のＢ−Ｂ’断面図である。また、第２図は第１図と
別なタイプの素子の平面図と断面図であるがいずれも、
第１層の導体２と第２層の導体１のソース・ドレイン方
向の幅が異なっていた。このことにより、以下に示す種
々の欠陥が見い出された。Conventionally, semiconductor memory devices with a two-layer conductor structure have either a first conductor layer 1 covered with a second conductor layer 2 as shown in FIG. 1, or a source of the second conductor layer 2 as shown in FIG. - Width W parallel to the drain direction. However, the width W of the first conductor m was smaller than that of the first conductor m. Figure 1 (a), (b), and (c
) is a plan view of a conventional memory element, a sectional view taken along the line AA' in a direction perpendicular to the source and drain, and a sectional view taken along the line BB' in a direction parallel to the source and drain 12. In addition, FIG. 2 is a plan view and a cross-sectional view of a different type of element from FIG.
The widths of the first layer conductor 2 and the second layer conductor 1 in the source/drain direction were different. As a result, the following various defects were discovered.
第１に、第１導体層１と第２導体層２を別々の工程で、
形成することにより、これら２層の相対的位置がずれ（
合せ精度のずれによる）メモリの特性や、第１導体層１
と第２導体層２の間の耐圧、第１導体層１とソース・ド
レイン領域３間の耐圧、第２層導体層２とソース・ドレ
イン領域３間の耐圧に悪影響を及ぼし、耐圧を下げてい
た。First, the first conductor layer 1 and the second conductor layer 2 are formed in separate steps.
By forming these two layers, the relative positions of these two layers are shifted (
(due to deviations in alignment accuracy) and the characteristics of the first conductor layer 1.
This adversely affects the breakdown voltage between the first conductor layer 1 and the second conductor layer 2, the breakdown voltage between the first conductor layer 1 and the source/drain region 3, and the breakdown voltage between the second conductor layer 2 and the source/drain region 3, lowering the breakdown voltage. Ta.
第２に、第１導体層と第２導体層を別々の工程で作るこ
とにより、合せ精度の余裕、及び特に第１図タイプの場
合には、第２導体層を第１導体層がおおう形になるので
、自づからメモリセルの大きさが増大し、ＬＳＩを作る
上で、集積度がおちる結果となる。Second, by making the first conductor layer and the second conductor layer in separate processes, there is a margin for alignment accuracy, and especially in the case of the type shown in Figure 1, the shape of the second conductor layer covered by the first conductor layer is improved. Therefore, the size of the memory cell naturally increases, resulting in a decrease in the degree of integration when manufacturing an LSI.
第３に、この半導体メモリ素子は、第１．第２導体層に
、２０〜３０Ｖの電圧を印加して（Ｎチャンネルの場合
）第１導体層に、電子を注入することにより書き込みが
行なわれるが、その場合、第１導体層と第２導体層の間
の容量と第１導体層と基板間の容量の比が問題になり、
できるだけ低電圧で効率よく書き込みが行なわれるには
、前者（第１−第２導体層間）容量が後者（第１一基板
間）に較べて大きい方が書き込みに必要な電圧が下がる
。よって第２図のように第２導体層の幅ＷｏをＷより細
くすると、第１−第２導体層間の容量が小さくなるので
書き込み電圧が上がる結果になる。Thirdly, this semiconductor memory element has the following features: Writing is performed by applying a voltage of 20 to 30 V to the second conductor layer (in the case of N channel) and injecting electrons into the first conductor layer. The problem is the ratio of the capacitance between the layers and the capacitance between the first conductor layer and the substrate.
In order to perform writing efficiently with as low a voltage as possible, the voltage required for writing is lowered if the former (between the first and second conductor layers) has a larger capacitance than the latter (between the first and first substrates). Therefore, if the width Wo of the second conductor layer is made smaller than W as shown in FIG. 2, the capacitance between the first and second conductor layers becomes smaller, resulting in an increase in the write voltage.
第４に、この不揮発性メモリでは、第１導体層と第２導
体層間の絶縁膜のリークにより、書き込みによって注入
された電子も逃げてしまう現象が起こる。このリーク現
象は、主として第１導体層の端部から電子が逃げていく
ことが原因であるが、第１図に示す構造にすると、特に
このリーク現象が著しい。Fourth, in this nonvolatile memory, a phenomenon occurs in which electrons injected by writing also escape due to leakage of the insulating film between the first conductor layer and the second conductor layer. This leakage phenomenon is mainly caused by electrons escaping from the ends of the first conductor layer, but this leakage phenomenon is particularly significant when the structure shown in FIG. 1 is used.
尚１本発明と同様の半導体メモリを対象とする製法とし
て特開昭５１−５９．２８１号公報に記載された技術が
ある。There is a technique described in Japanese Unexamined Patent Publication No. 51-59.281 as a manufacturing method for a semiconductor memory similar to that of the present invention.
しかし、該技術は、上層をホ１へエッチした後、下層を
酸化することについては何ら開示していなＩＬ）。However, this technique does not disclose anything about oxidizing the lower layer after etching the upper layer to the hole (IL).
本発明は低電圧で効率よく書き込みが行え、耐圧特性が
極めて良好な半導体メモリを得ることを目的とする。An object of the present invention is to obtain a semiconductor memory that can be written efficiently at low voltage and has extremely good breakdown voltage characteristics.
発明の他の目的は、リーク現象の少ない半導体メモリを
得ることを目的とする。Another object of the invention is to obtain a semiconductor memory with less leakage phenomenon.
上記目的を達成する為に、本願発明では上層導体層等を
自己整合的にホトエッチ除去し、下層導体層は所望部分
を酸化することを特徴とする。In order to achieve the above object, the present invention is characterized in that the upper conductor layer and the like are removed by photoetching in a self-aligned manner, and desired portions of the lower conductor layer are oxidized.
本発明はこれらの欠点を無くすもので、以下実施例に基
づいて説明する。The present invention eliminates these drawbacks and will be explained below based on examples.
実施例１
単体１個のメモリ素子を作る場合と、大規模集積回路中
にメモリ素子を組み込む場合とでは、多少、製造プロセ
スが異なるが、ここでは大規模集積回路の場合について
第３図を用いて説明する。Example 1 The manufacturing process is slightly different between making a single memory element and incorporating a memory element into a large-scale integrated circuit, but here we will use Figure 3 for the case of a large-scale integrated circuit. I will explain.
第３図（ａ）は装置主要部の平面図、（ｂ）、 （ｃ、
）は各々、ソース・ドレイン方向に平行（Ａ−Ａ’ ）
、ソース・ドレイン方向に直角（Ｂ−Ｂ’）な断面図で
ある。Figure 3 (a) is a plan view of the main part of the device, (b), (c,
) are parallel to the source/drain direction (A-A')
, is a cross-sectional view (BB') perpendicular to the source/drain direction.
第３図（ｂ）、 （Ｃ）に示すように、シリコン基板７
（Ｎ型、Ｐ型どちらでも使えるがここでは、Ｎ型を例に
あげる）上に、第１絶縁膜６（例えばシリコン酸化膜）
及び、絶縁膜５（例えばシリコン酸化膜）をそれぞれ形
成する。その時の厚さは、それぞれ、１０００人、１．
２７ｚｒｎであった。（これから記す各値は１例であり
、この半導体装置の構造を束縛するものではない。もち
ろん、他の値も許される。）この絶縁膜５．６−ｈに、
第１導体層１ （例えば、リンがドープされた多結晶シ
リコン、もちろん多結晶シリコンを堆積して、その後で
リンを拡散してもよい。又、その他の半導体、・あるい
は半導体にかぎらず、金属でもよい。）を付ける。この
膜厚は３５００人であった。この第１導体層１をソース
・ドレイン方向に平行な二辺９だけをホトエツチングに
より切る。（このホトエツチングの工程は、単体１個の
メモリを作る時には、不必要であり、第２導体層２をホ
トエツチングする時に、自己整合法により、同時に形成
すればよい。）次に、第２絶縁膜４（例えば、多結晶シ
リコンの熱酸化膜、Ｃ’Ｖ Ｄ法による酸化膜）を１０
００人程度付ける。As shown in FIGS. 3(b) and (C), the silicon substrate 7
(N-type or P-type can be used, but N-type will be taken as an example here.) On the first insulating film 6 (for example, silicon oxide film)
Then, an insulating film 5 (for example, a silicon oxide film) is formed. The thickness at that time was 1000 people and 1.
It was 27zrn. (The values described below are just examples and do not limit the structure of this semiconductor device. Of course, other values are also allowed.) In this insulating film 5.6-h,
First conductor layer 1 (for example, polycrystalline silicon doped with phosphorus, of course polycrystalline silicon may be deposited and then phosphorus is diffused. Also, other semiconductors, or not only semiconductors, but also metals) ). The film thickness was 3,500 people. This first conductor layer 1 is cut by photoetching only two sides 9 parallel to the source/drain direction. (This photo-etching step is not necessary when making a single memory, and can be formed simultaneously by the self-alignment method when photo-etching the second conductor layer 2.) Next, the second insulating film is formed. 4 (for example, thermal oxide film of polycrystalline silicon, oxide film by C'V D method) to 10
Add about 00 people.
この絶縁膜４の上に、第２導体層（例えば、リンをドー
プした多結晶シリコン３５００人又は、多結晶シリコン
を堆積し、後のソース・ドレインを作る工程のときに、
いっしょにリン拡散してもよい。又金属でもよい。）を
付ける。次に、この第２導体層２をホトエツチングによ
り、ソース・ドレイン方向に直角に、第２導体層を切る
。このときの幅は５μｍであった。次に、レジスト膜を
残したまま自己整合法により第２導体層２．第２絶縁膜
４．第１導体層１．第１絶縁膜６を順にエツチングによ
り所定の大きさに形成すればよいが、周辺回路も第２導
体層をマスクにした自己整合法により形成しようとする
と第４図の様な工程をふむことが必要である。第４図に
主な工程の流れ図を示す。（ａ）、 （ｂ）はそれぞれ
、周辺回路のＭＣ）８トランジスターの主な製造工程、
導体２層構造を持つメモリの主な製造工程を示す。On this insulating film 4, a second conductor layer (for example, phosphorus-doped polycrystalline silicon or polycrystalline silicon is deposited, and in the later process of forming sources and drains,
You can also diffuse phosphorus together. It may also be made of metal. ). Next, the second conductor layer 2 is cut perpendicularly to the source/drain direction by photoetching. The width at this time was 5 μm. Next, the second conductor layer 2 is formed using a self-alignment method while leaving the resist film. Second insulating film 4. First conductor layer1. The first insulating film 6 may be formed to a predetermined size by sequential etching, but if the peripheral circuit is also formed by a self-alignment method using the second conductor layer as a mask, the process as shown in FIG. 4 may be required. is necessary. Figure 4 shows a flowchart of the main processes. (a) and (b) are the main manufacturing processes of the peripheral circuit MC)8 transistors, respectively;
This figure shows the main manufacturing process of a memory with a two-layer conductor structure.
上述したごとく第１導体層１．第２導体層２゜第１絶縁
膜６．第２絶縁膜４を形成し、次に、第２導体層２上に
付着したレジスト膜１１をマスクにして自己整合法によ
り、エツチングして第２導体層２．第２絶縁膜４．第１
導体層ｌを形成する。As described above, the first conductor layer 1. Second conductor layer 2゜first insulating film 6. A second insulating film 4 is formed, and then the second conductive layer 2 is etched by a self-alignment method using the resist film 11 deposited on the second conductive layer 2 as a mask. Second insulating film 4. 1st
A conductor layer l is formed.
次に、１度全レジスト膜を除去して、新に、メモリ部分
だけを全面レジスト膜でおおう。その状態で、周辺回路
の第２導体層（第４図（ａ））。次に、レジスト膜を除
去して、メモリ部分の第１絶縁膜６と周辺回路の第２絶
縁膜４．第１絶縁１肱６を一度にエツチングする。次に
、自己整合法により、拡散Ｎ３を形成する。Next, the entire resist film is removed once, and only the memory area is covered with a new resist film. In this state, the second conductor layer of the peripheral circuit (FIG. 4(a)). Next, the resist film is removed, and the first insulating film 6 of the memory portion and the second insulating film 4 of the peripheral circuit. One layer 6 of the first insulation is etched at a time. Next, diffusion N3 is formed by a self-alignment method.
以上の方法により、周辺回路、メモリ部分を同時に形成
することができた。次にこのメモリの主な特性を従来の
メモリと比較する。By the above method, the peripheral circuit and the memory portion could be formed simultaneously. Next, the main characteristics of this memory will be compared with conventional memory.
第１に、第１導体層１と第２導体層を自己整合法により
一度に作ることにより、相対的なずれもなく、メモリ特
性や耐圧特性が著しく良くなった。First, by forming the first conductor layer 1 and the second conductor layer at the same time by a self-alignment method, there was no relative deviation, and the memory characteristics and breakdown voltage characteristics were significantly improved.
第２に、自己整合法を用いたことにより、メモリの大き
さを従来のものに較べて約半分にすることができ、集積
度を著しく向上することができた。Second, by using the self-alignment method, the size of the memory can be reduced to approximately half that of the conventional method, and the degree of integration can be significantly improved.
第３に、第１導体［１と第２導体Ｍ２間のリーク現象も
著しく少なくなった。これは、第１図のような構造では
、第１導体層の端部から電子がリークするが、第３図の
ような構造にすると端部の影響があられれてこない。第
１図の構造の時には、リーク電流がＩ Ｏ’ Ａ／ｃｎ
！（第１導体Ｒりと第２導体層間の電圧は２０ｖ）であ
ったものが、この発明では１０ ’−’ Ａ／ＣＩ＃と
なり著しい向上を見た。Thirdly, the leakage phenomenon between the first conductor [1 and the second conductor M2 was also significantly reduced. This is because, in the structure shown in FIG. 1, electrons leak from the ends of the first conductor layer, but in the structure shown in FIG. 3, the influence of the ends is eliminated. In the structure shown in Fig. 1, the leakage current is I O' A/cn
! (The voltage between the first conductor layer and the second conductor layer was 20V), but in this invention, the voltage was 10'-'A/CI#, which was a remarkable improvement.
第４に、この発明のように、メモリ部及び周辺回路を自
己整合法により作らＪし、その工程も、複雑でないので
、多層構造を持つ半導体装置に利用される。Fourthly, as in the present invention, the memory section and peripheral circuits are manufactured by a self-alignment method, and the process is not complicated, so that it can be used in semiconductor devices having a multilayer structure.
実施例２
実施例１に示した、自己整合法による第１導体層１と第
２導体層２の形成は、ホトエツチングを用いたが、ここ
では、酸化法による自己整合法について説明する。まず
、第２導体層２の１．にシリコン窒化膜を付けそれをホ
トエツチングにより、所定の大きさに切る。さらに、第
２導体に１２．第２絶縁膜４もナイ］・ライドをマスク
にしてホトエツチングによって切る。その状態で、酸化
すると第１導体層ｌが、自己整合法により、形成され、
かつ、第１導体層は回りを酸化膜で自づからおおわれる
形となり、絶縁性がよく、各層間の耐圧も向上された。Example 2 Although photoetching was used to form the first conductor layer 1 and the second conductor layer 2 by the self-alignment method shown in Example 1, a self-alignment method using an oxidation method will be described here. First, 1. of the second conductor layer 2. A silicon nitride film is attached to the surface and cut into a predetermined size by photoetching. Furthermore, 12. The second insulating film 4 is also cut by photo-etching using a blank film as a mask. When oxidized in that state, the first conductor layer l is formed by a self-alignment method,
In addition, the first conductor layer was automatically covered with an oxide film, resulting in good insulation and improved breakdown voltage between each layer.
第１図は、従来からあるメモリ素子の構造を示し、（ａ
Ｌ （ｂ）、 （Ｃ）、そ汎ぞ九、平面図、ソース・ド
レインに直角方向の断面図、ソース・ドレインに平行８
方向の断面図である。
第２図は、従来からある別なタイプのメモリ素子の構造
を示し、（ａＬ （ｂ）はそＭ汎、平面図、ソース・ド
レイン方向に平行な断面図でＪ、′ｌる。
第３図は、本発明の半導体装置の構造を示し、（ａ）、
（ｂ）、 （ｃ）それぞれ、平面図、ソース・トレイ
ン方向に平行な断面図、ソース・ドレイン方向に直角な
断面図である。
第４図は、本発明の主な製造工程で、自己整合法により
、メモリ部分と周辺回路部分を作る工程を示している。
（ａ）、 （ｂ）は、それぞれ周辺回路のＭｏ５ｔ−ラ
ンジスタの主な’Ｍ ｉｆｆ Ｉ 程の断面図、メモリ
部分の主な製造工程の断面図である。
１・・・第１導体層２２・・・第２導体層、３・・・不
純物領域、４・・・絶縁膜、５・・・絶縁膜である。
第１図
第２図
（ａ−ン
第３ 図
（６） 〜２FIG. 1 shows the structure of a conventional memory element, (a
L (b), (C), dimensions 9, top view, cross-sectional view perpendicular to the source/drain, parallel to the source/drain 8
It is a sectional view of the direction. FIG. 2 shows the structure of another conventional type of memory element, where (aL (b) is a general view, a plan view, and a sectional view parallel to the source/drain direction. The figure shows the structure of a semiconductor device of the present invention, (a),
(b) and (c) are a plan view, a sectional view parallel to the source/train direction, and a sectional view perpendicular to the source/drain direction, respectively. FIG. 4 shows the main manufacturing process of the present invention, which is the process of creating a memory section and a peripheral circuit section by a self-alignment method. (a) and (b) are a cross-sectional view of the main M iff I of the Mo5t transistor of the peripheral circuit, and a cross-sectional view of the main manufacturing process of the memory part, respectively. 1... First conductor layer 22... Second conductor layer, 3... Impurity region, 4... Insulating film, 5... Insulating film. Figure 1 Figure 2 (a-n Figure 3 (6) ~2
Claims (1)
程。 該耐食性膜をマスクとして、第２の絶縁膜を食刻する工
程。 酸化雰囲気で、第１の導体層の所望部分及び第２の導体
層の端部を酸化する工程。 上記、第１の導体層の酸化膜の所望部分を除去する工程
。 上記、第１の絶縁膜の所望部分を除去する工程。 上記半導体基板中に、ソース及びドレイン領域を形成す
る工程。 から成ることを特徴とする半導体装置の製造方法。[Claims] 1. A step of forming a first insulating film on a semiconductor substrate. A step of forming a first conductor layer on the insulating film. forming a second insulating film on the first conductor layer; forming a second conductor layer on the second insulating film; forming a corrosion-resistant film on the second conductor layer; Etching the corrosion-resistant film into a desired shape. A step of etching the second conductor layer using the corrosion-resistant film as a mask. A step of etching the second insulating film using the corrosion-resistant film as a mask. oxidizing a desired portion of the first conductor layer and an end of the second conductor layer in an oxidizing atmosphere; the step of removing a desired portion of the oxide film of the first conductor layer; A step of removing a desired portion of the first insulating film. forming source and drain regions in the semiconductor substrate; A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59244428A JPS60149168A (en) | 1984-11-21 | 1984-11-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59244428A JPS60149168A (en) | 1984-11-21 | 1984-11-21 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12380976A Division JPS5349960A (en) | 1976-10-18 | 1976-10-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60149168A true JPS60149168A (en) | 1985-08-06 |
Family
ID=17118508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59244428A Pending JPS60149168A (en) | 1984-11-21 | 1984-11-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149168A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0396508A2 (en) * | 1989-04-07 | 1990-11-07 | STMicroelectronics S.r.l. | Process for fabricating an EPROM cell array |
-
1984
- 1984-11-21 JP JP59244428A patent/JPS60149168A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0396508A2 (en) * | 1989-04-07 | 1990-11-07 | STMicroelectronics S.r.l. | Process for fabricating an EPROM cell array |
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