JPS60143653A - Sealing and cooling mechanism of package - Google Patents

Sealing and cooling mechanism of package

Info

Publication number
JPS60143653A
JPS60143653A JP24765383A JP24765383A JPS60143653A JP S60143653 A JPS60143653 A JP S60143653A JP 24765383 A JP24765383 A JP 24765383A JP 24765383 A JP24765383 A JP 24765383A JP S60143653 A JPS60143653 A JP S60143653A
Authority
JP
Japan
Prior art keywords
cap
substrate
semiconductor devices
package
cooling mechanism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24765383A
Other languages
Japanese (ja)
Other versions
JPS6412098B2 (en
Inventor
Hideki Watanabe
秀樹 渡邊
Fumiyuki Kobayashi
小林　二三幸
Takahiro Oguro
崇弘 大黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24765383A priority Critical patent/JPS60143653A/en
Publication of JPS60143653A publication Critical patent/JPS60143653A/en
Publication of JPS6412098B2 publication Critical patent/JPS6412098B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To miniatuarize a part for sealing and impart a high cooling performance by sticking a cap comprising a thermal expansion coefficient which is equal to that of a substrate on which semiconductor devices are mounted or is almost accordant with that and consisting of a material of high heat conductivity to said substrate. CONSTITUTION:Plural semiconductor devices 13 are connected by solder to a surface of a substrate 11 consisting of a sintered multilayer mullite ceramic material by flip chips. A cap 12 made of silicon carbide is stuck to a substrate 11 in order to seal the semiconductor devices 13. The cap 12 is provided with a heat conduction means 14 for conducting the generated heat by the semiconductors 13 to the cap which exists between an internal surface of the cap 12 and the semiconductor devices 13 and a cooling jacket 15 as a cooling means for removing the heat collected in the cap 12. Thermal expansion coefficients of mullite ceramic and silicon carbide are 40X10<-7>/ deg.C and 35X10<-7>/ deg.C respectively and are almost equal so that there is no warpage produced in both of the substrate 11 and the cap 12 even when these are stuck.

Description

【発明の詳細な説明】 ［発明の利用分野〕 本発明は、複数個の半導体デバイスを実装したパッケー
ジを封止し冷却するパッケージの封止冷却機構に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a package sealing and cooling mechanism for sealing and cooling a package in which a plurality of semiconductor devices are mounted.

〔発明の背景〕[Background of the invention]

複数の半導体デバイスを実装したパッケージの従来の封
止冷却機構の一例として、第１図にその断面を示す。こ
の機構は、半導体デバイス３を搭載したセラミック基板
１と、該セラミック基板１にロー付けされ、かつ該セラ
ミック基板１の端部を越えて外方にのびた環状フランジ
２と、該フランジに係合するキャップ４と、該フランジ
２と該キャップ間の環状ガスケシトロと、該フランジ２
と該キャップ４の係合状態を維持するためのクランプ部
材５により封止体を形成する。上記半導体デバイス３か
ら熱を取り除くために上記キャップ４に冷却手段７が取
り付けられている。上記機構では、キャップ４とセラミ
ック基板１は別体をなしているから、キャップ４の熱膨
張係数をセラミック基板１の熱膨張係数に整合させなく
ても良い。As an example of a conventional sealing cooling mechanism for a package in which a plurality of semiconductor devices are mounted, a cross section thereof is shown in FIG. This mechanism includes a ceramic substrate 1 on which a semiconductor device 3 is mounted, an annular flange 2 that is soldered to the ceramic substrate 1 and extends outward beyond the end of the ceramic substrate 1, and engages with the flange. a cap 4, an annular gasket between the flange 2 and the cap, and the flange 2.
A sealing body is formed by a clamp member 5 for maintaining the engaged state of the cap 4. Cooling means 7 are attached to the cap 4 to remove heat from the semiconductor device 3. In the above mechanism, since the cap 4 and the ceramic substrate 1 are separate bodies, it is not necessary to match the thermal expansion coefficient of the cap 4 to that of the ceramic substrate 1.

そのためキャップ４の材料として、たとえばアルミニウ
ムのような高い熱伝導率を有する材料が使用できる。し
かし上記機構では熱膨張係数の異なる部材を互に強固に
固定するため、封止のためのフランジ２やキャップ４や
クランプ部材５の部分が上記セラミック基板１の外に突
き出て、パッケージの占有面積が大きくなる。このため
、パッケージ相互間の配線が長くなり、複数のパッケー
ジからなるシステム全体の信号遅延が増大するという欠
点があった。Therefore, as the material of the cap 4, a material having high thermal conductivity such as aluminum can be used. However, in the above mechanism, since members having different coefficients of thermal expansion are firmly fixed to each other, parts of the flange 2, cap 4, and clamp member 5 for sealing protrude outside the ceramic substrate 1, resulting in the occupying area of the package. becomes larger. For this reason, there is a drawback that the wiring between the packages becomes long and the signal delay of the entire system consisting of a plurality of packages increases.

また、他の従来の封止冷却機構として、半導体デバイス
を搭載したセラミック基板と、セラミック基板の半導体
デバイス搭載面を覆い、かつこの搭載面の端部にて基板
接合されたセラミック基板と同材質のセラミックで作っ
たキャップとで封止体を形成しているものが知られ按で
いる。半導体デバイスから熱を取り除くためにキャップ
に冷却手段が取り付けられている。上記機構では、セラ
ミック基板とキャップの熱膨張係数の不整合に基づく問
題はないが、セラミック材はあまり高い熱伝導率を持た
ないので、高い冷却性能を得にくいという欠点があった
。In addition, as another conventional sealed cooling mechanism, a ceramic substrate with a semiconductor device mounted thereon and a ceramic substrate made of the same material as the ceramic substrate that covers the semiconductor device mounting surface of the ceramic substrate and is bonded to the substrate at the edge of this mounting surface are used. It is known that a sealed body is formed with a cap made of ceramic. Cooling means are attached to the cap to remove heat from the semiconductor device. Although the above mechanism does not have problems due to mismatching of the coefficients of thermal expansion between the ceramic substrate and the cap, it has the disadvantage that it is difficult to obtain high cooling performance because the ceramic material does not have very high thermal conductivity.

〔発明の目的〕[Purpose of the invention]

本発明は上述の点にかんがみてなされたもので、封止め
ための部分を極小化し、かつ高い冷却性能を持つ半導体
デバイス用のパッケージ封止冷却機構を提供することを
目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a package sealing cooling mechanism for semiconductor devices that minimizes the sealing portion and has high cooling performance.

〔発明の概要〕[Summary of the invention]

本発明は、上述の目的を達成するため、半導体デバイス
が搭載される基板に、この基板の熱膨張３− 係数と等しいかほぼ整合する熱膨張係数を有し、かつ熱
伝導率の高い材料よりなるキャップを固着するよう構成
する。In order to achieve the above object, the present invention provides a substrate on which a semiconductor device is mounted using a material having a coefficient of thermal expansion equal to or almost matching the coefficient of thermal expansion of the substrate and having a high thermal conductivity. The cap is configured to be fixed.

〔発明の実施例〕[Embodiments of the invention]

・以下、本発明の実施例を図面に基づいて説明する。 - Hereinafter, embodiments of the present invention will be described based on the drawings.

第２図は本発明の一実施例をなすパッケージの封止冷却
機構を示す一部切断斜視図であり、第３図はその断面図
である。FIG. 2 is a partially cutaway perspective view showing a sealing cooling mechanism for a package according to an embodiment of the present invention, and FIG. 3 is a sectional view thereof.

複数個の半導体デバイス１３がフリップチップによって
、焼成された多層ムライトセラミック材からなる基板１
１の上表面に電気的、物理的にハンダ付けで接続される
。基板１１の基板裏表面にはパッケージが外部と電気的
に接続するためのＩ１０ピン１６がロー付けされている
。基板１１には半導体デバイス３とＩ１０ピン１６が電
気的に相互に接続されるための表面層および内層配線を
有している。半導体デバイス１３を封止するために炭化
シリコン（ＳｉＣ）を材料とするキャップ１２が基板１
に固着されている。キャップ１２４− には、キャップ１２の内面と半導体デバイス１３の間に
あって、半導体デバイス１３の発熱をキャップ１２に伝
えるための熱伝導手段１４と、キャップ１２に集められ
た熱を取り除くための冷却手段として水冷ジャケット１
５が取り付けられている。A substrate 1 made of a multilayer mullite ceramic material on which a plurality of semiconductor devices 13 are baked by flip-chip
It is electrically and physically connected to the upper surface of 1 by soldering. An I10 pin 16 is soldered to the back surface of the substrate 11 for electrically connecting the package to the outside. The substrate 11 has a surface layer and inner layer wiring for electrically interconnecting the semiconductor device 3 and the I10 pin 16. A cap 12 made of silicon carbide (SiC) is attached to the substrate 1 to seal the semiconductor device 13.
is fixed to. The cap 124 includes a heat conduction means 14 located between the inner surface of the cap 12 and the semiconductor device 13 for transmitting the heat generated by the semiconductor device 13 to the cap 12, and a cooling means for removing the heat collected in the cap 12. water cooling jacket 1
5 is attached.

１７と１８は各々水冷ジャケット１５の水の人出口であ
る。17 and 18 are water outlets of the water cooling jacket 15, respectively.

上記キャップ１２の材質は銅−炭素繊維複合材料（Ｃｕ
−ＣＦＲＭ　（以下単にＣｕ−ＣＦＲＭと記す）】でも
よく、その場合は基板１１の材料はアルミナセラミック
でもよい。The material of the cap 12 is a copper-carbon fiber composite material (Cu
-CFRM (hereinafter simply referred to as Cu-CFRM)], and in that case, the material of the substrate 11 may be alumina ceramic.

上記封止冷却機構において、半導体デバイス１３により
発生する熱は熱伝導手段１４を介してキャップ１２に集
められ、キャップ１２に集められた熱は水冷ジャケット
１５で熱交換され、外部に排出される。シリコン、ムラ
イトセラミック、アルミナセラミック、炭化シリコン、
Ｃｕ−ＣＦＲＭの熱膨張係数と伝導率は表１に示すよう
な関係になっている。In the sealed cooling mechanism, heat generated by the semiconductor device 13 is collected in the cap 12 via the heat conduction means 14, and the heat collected in the cap 12 is exchanged with the water cooling jacket 15 and discharged to the outside. silicon, mullite ceramic, alumina ceramic, silicon carbide,
The thermal expansion coefficient and conductivity of Cu-CFRM have a relationship as shown in Table 1.

表１ 基板１１にムライトセラミック材を用い、キャップ１２
に炭化シリコン材を用いた場合、ムライトセラミックと
炭化シリコン、その熱膨張係数はそほぼ等しいため基板
１１とキャップ１２を固着しても両者に歪を生ずること
はない。また、基板１１の材料にアルミナセラミックを
用い、キャップ１２の材料にＣｕ　−ＣＦ　ＲＭを用い
た場合も、アルミナセラミックとＣＣｕ−４０ＣＦＲの
その熱膨張係数はそれぞれ６５Ｘ１０　７℃、６５×１
０７℃と等しいから基板１１とキャップ１２を固着して
も両者に歪を生ずることはない。しかも、炭化シリコン
、Ｃｕ−ＣＦＲＭの熱伝導率はそれぞれ２７０．２５０
　ｗ　ｍ−１ｋ−１とアルミニウムの２４０　ｗ　ｍ−
１ｋ−１にほぼ等しいから、キャップ１２にこれらの材
料を用いることは、冷却性能をアルミニウムを用いる場
合と同様に高めることができる。Table 1 Mullite ceramic material is used for the substrate 11, cap 12
When a silicon carbide material is used, the coefficients of thermal expansion of mullite ceramic and silicon carbide are almost the same, so even if the substrate 11 and the cap 12 are fixed together, no distortion occurs in them. Furthermore, when alumina ceramic is used as the material for the substrate 11 and Cu-CF RM is used as the material for the cap 12, the thermal expansion coefficients of alumina ceramic and CCu-40CFR are 65×10 7°C and 65×1, respectively.
Since the temperature is equal to 0.7°C, even if the substrate 11 and the cap 12 are fixed together, no distortion will occur in both. Moreover, the thermal conductivity of silicon carbide and Cu-CFRM is 270.250, respectively.
w m-1k-1 and 240 w m- of aluminum
Since it is approximately equal to 1k-1, using these materials for the cap 12 can improve the cooling performance as well as using aluminum.

第４図は本発明の他の実施例をなすパッケージの封止冷
却機構の一部切断側面図である。FIG. 4 is a partially cutaway side view of a package sealing cooling mechanism according to another embodiment of the present invention.

ムライトセラミック材からなる基板２１の上表面に半導
体デバイス２３がフリップチップによって接続されてい
る。２９はその接続素子である。A semiconductor device 23 is connected to the upper surface of a substrate 21 made of mullite ceramic material by a flip chip. 29 is its connecting element.

半導体デバイス２３を封止するために炭化シリコンを材
料とするキャップ２２が基板２１に固着されている。キ
ャップ２２と半導体デバイス２３の間には、化学的に不
活性な熱伝導ペースト２４があり、また空冷フィン２５
がキャップ２２に取すウ 付けられている。こパッケージは外部とフラットリード
２６によって電気的に接続されている。A cap 22 made of silicon carbide is fixed to the substrate 21 to seal the semiconductor device 23 . Between the cap 22 and the semiconductor device 23 there is a chemically inert thermally conductive paste 24 and air cooling fins 25.
is attached to the cap 22. This package is electrically connected to the outside via a flat lead 26.

上記キャップ２２め材質は、Ｃｕ　−ＣＦ　ＲＭでもよ
く、その場合は基板２１の材料はアルミナセフ− ラミックでよい。The material of the cap 22 may be Cu-CF RM, and in that case, the material of the substrate 21 may be alumina cephramic.

上記のような構造にすることにより、基板２１の材料ム
ライトセラミックと、キャップ２２の材料炭化シリコン
とは熱膨張率が前述同様はぼ等しいから基板１１とキャ
ップ２２を固着しても両者に歪は生じない。また、キャ
ップ２２として炭化シリコンを用いることは、炭化シリ
コンが前述のようにアルミニウムと同様、高い熱伝導率
を有することから、冷却性能もすぐれたものとなる。基
板２１の材料にアルミナセラミック、キャップ２２の材
料にＣｕ　−ＣＦ　ＲＭを用いた場合も、同様に基板２
１とキャップ２２間の歪がなく、冷却性もすぐれたもの
となる。上記構造のバッツケージの封止冷却機構は、１
つのパッケージあたりの半導体デバイス２３の個数が比
較的少なく、かつ半導体デバイスの発熱量が比較的小さ
い場合に用いられる。With the above structure, the mullite ceramic material for the substrate 21 and the silicon carbide material for the cap 22 have approximately the same coefficient of thermal expansion as described above, so even if the substrate 11 and the cap 22 are fixed together, there is no distortion in both. Does not occur. Furthermore, using silicon carbide as the cap 22 provides excellent cooling performance since silicon carbide has high thermal conductivity like aluminum as described above. Similarly, when the substrate 21 is made of alumina ceramic and the cap 22 is made of Cu-CF RM, the substrate 2
There is no distortion between the cap 1 and the cap 22, and the cooling performance is excellent. The sealing cooling mechanism of the butt cage with the above structure is as follows:
This is used when the number of semiconductor devices 23 per package is relatively small and the amount of heat generated by the semiconductor devices is relatively small.

また、上記実施例において、熱伝導手段１４や熱伝導ペ
ースト２４のように、冷却用の部品の全てもしくは一部
をキャップ１２や２２と一体に形８− 成すれば、キャップ１２や２２とこれら冷却用部品の固
着による熱抵抗の増大を回避できて、冷却性能がよりよ
くなると共に１部品点数の減少によりパッケージの封止
冷却機構の組立性能が向上する。Further, in the above embodiment, if all or a part of the cooling parts, such as the heat conduction means 14 and the heat conduction paste 24, are formed integrally with the caps 12 and 22, the caps 12 and 22 and these parts can be integrated. It is possible to avoid an increase in thermal resistance due to the fixation of cooling parts, thereby improving cooling performance, and by reducing the number of parts, the assembly performance of the package sealing cooling mechanism is improved.

上記実施例によれば、基板１１．２１の上面にキャップ
１２．２２を直接固着できるので、パッケージの封止部
を小型にでき、パッケージ間の信号遅延が減少し、複数
のパッケージからなるシステムの性能向上が図れる。し
かも、キャップ１２．２２の材料としては、アルミニウ
ムと同程度あるいはそれ以上の炭化シリコンやＣｕ−Ｃ
ＦＲＭを使用するので冷却性能も向上する。According to the above embodiment, since the cap 12.22 can be directly fixed to the upper surface of the substrate 11.21, the sealing part of the package can be made smaller, the signal delay between packages can be reduced, and the system consisting of multiple packages can be reduced. Performance can be improved. Moreover, the material of the cap 12.22 is silicon carbide or Cu-C, which is equivalent to or higher than aluminum.
Since FRM is used, cooling performance is also improved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、複数個の半導体
デバイスを実装したパッケージに高い冷却性能を与える
ことが可能になり、かつパッケージ間の信号遅延が減少
し、複数のパッケージからなるシステムの性能向上が可
能となるという優れた効果が得られる。As explained above, according to the present invention, it is possible to provide high cooling performance to a package mounted with a plurality of semiconductor devices, reduce signal delay between packages, and improve the efficiency of a system consisting of a plurality of packages. An excellent effect is obtained in that performance can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のパッケージの封止冷却機構を示す断面図
、第２図、第３図は本発明の一実施例をなすパッケージ
の封止冷却機構を示す図で、第２図は一部切断斜視図、
第３図は断面図、第４図は本発明の他の実施例をなすパ
ッケージの封止冷却機構の断面図である。 １１、】２・・・基板、１２．２２・・・キャップ、１
３．２３・・・半導体デバイス、１４・・・熱伝導手段
、　２４・・・熱伝導ペースト、１５・・・水冷ジャケ
ット、１６．２６・・・Ｉ１０ピン。 １１− 第１図 第２図FIG. 1 is a sectional view showing a conventional package sealing cooling mechanism, and FIGS. 2 and 3 are diagrams showing a package sealing cooling mechanism according to an embodiment of the present invention. Cutaway perspective view,
FIG. 3 is a sectional view, and FIG. 4 is a sectional view of a package sealing cooling mechanism according to another embodiment of the present invention. 11, ]2... Substrate, 12.22... Cap, 1
3.23...Semiconductor device, 14...Heat conduction means, 24...Heat conduction paste, 15...Water cooling jacket, 16.26...I10 pin. 11- Figure 1 Figure 2

Claims (4)

【特許請求の範囲】[Claims] （１）複数の半導体デバイスが上面に登載されかつ該半
導体デバイスと熱膨張係数が等しいがあるいはほぼ整合
する材料からなる基板と、該基板の熱膨張係数に等しい
かあるいはほぼ整合する熱膨張係数を有しかつ熱伝導率
の高い材料がらなり前記基板上面に固着され前記半導体
デバイスを覆い封止するキャップと、前記半導体デバイ
スの発熱を前記キャップに伝えるために該半導体デバイ
ス上面と前記キャップ内面との間に設けられた熱伝導手
段と、前記キャップに集められた熱を取り除くため前記
キャップ外表面に取り付けられた冷却手段とから構成さ
れることを特徴とするパッケージの封止冷却機構。(1) A substrate on which a plurality of semiconductor devices are mounted and made of a material having a coefficient of thermal expansion equal to or almost matching that of the semiconductor devices, and a material having a coefficient of thermal expansion equal to or almost matching that of the semiconductor devices; a cap made of a material with high thermal conductivity and fixed to the upper surface of the substrate to cover and seal the semiconductor device; A package sealing cooling mechanism comprising: a heat conduction means provided between the caps, and a cooling means attached to the outer surface of the cap for removing heat collected in the cap. （２）前記基板材料としてムライトセラミックを用い、
前記キャップ材料として炭化シリコンを用いたことを特
徴とする特許請求の範囲第（１）項記載のパッケージの
封止冷却機構。(2) using mullite ceramic as the substrate material,
The package sealing cooling mechanism according to claim 1, characterized in that silicon carbide is used as the cap material. （３）前記キャップ材料として銅−炭素繊維複合材料を
用いたことを特徴とする特許請求の範囲第（１）項記載
のパッケージの封止冷却機構。(3) The package sealing cooling mechanism according to claim (1), wherein a copper-carbon fiber composite material is used as the cap material. （４）前記キャップに取り付けられる冷却手段および前
記熱伝導手段の部品の内、全てもしくは一部を前記キャ
ップと一体に形成したことを特徴とする特許請求の範囲
第（１）項記載のパッケージの封止冷却機構。(4) The package according to claim (1), wherein all or a part of the cooling means and the heat conduction means attached to the cap are formed integrally with the cap. Sealed cooling mechanism.
JP24765383A 1983-12-30 1983-12-30 Sealing and cooling mechanism of package Granted JPS60143653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24765383A JPS60143653A (en) 1983-12-30 1983-12-30 Sealing and cooling mechanism of package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24765383A JPS60143653A (en) 1983-12-30 1983-12-30 Sealing and cooling mechanism of package

Publications (2)

Publication Number Publication Date
JPS60143653A true JPS60143653A (en) 1985-07-29
JPS6412098B2 JPS6412098B2 (en) 1989-02-28

Family

ID=17166679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24765383A Granted JPS60143653A (en) 1983-12-30 1983-12-30 Sealing and cooling mechanism of package

Country Status (1)

Country Link
JP (1) JPS60143653A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0350593A2 (en) * 1988-07-13 1990-01-17 International Business Machines Corporation Electronic package with heat spreader member
US5109317A (en) * 1989-11-07 1992-04-28 Hitachi, Ltd. Mounting mechanism for mounting heat sink on multi-chip module
US5455457A (en) * 1990-11-27 1995-10-03 Nec Corporation Package for semiconductor elements having thermal dissipation means
US5880524A (en) * 1997-05-05 1999-03-09 Intel Corporation Heat pipe lid for electronic packages
US6528878B1 (en) * 1999-08-05 2003-03-04 Hitachi, Ltd. Device for sealing and cooling multi-chip modules
CN110010574A (en) * 2018-12-29 2019-07-12 杭州臻镭微波技术有限公司 A kind of radio-frequency structure and preparation method thereof that multiple-level stack type longitudinally interconnects

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196041A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Thermal conduction connecting device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58196041A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Thermal conduction connecting device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0350593A2 (en) * 1988-07-13 1990-01-17 International Business Machines Corporation Electronic package with heat spreader member
US5109317A (en) * 1989-11-07 1992-04-28 Hitachi, Ltd. Mounting mechanism for mounting heat sink on multi-chip module
US5455457A (en) * 1990-11-27 1995-10-03 Nec Corporation Package for semiconductor elements having thermal dissipation means
US5880524A (en) * 1997-05-05 1999-03-09 Intel Corporation Heat pipe lid for electronic packages
US6528878B1 (en) * 1999-08-05 2003-03-04 Hitachi, Ltd. Device for sealing and cooling multi-chip modules
US6890799B2 (en) * 1999-08-05 2005-05-10 Hitachi, Ltd. Device for sealing and cooling multi-chip modules
CN110010574A (en) * 2018-12-29 2019-07-12 杭州臻镭微波技术有限公司 A kind of radio-frequency structure and preparation method thereof that multiple-level stack type longitudinally interconnects
CN110010574B (en) * 2018-12-29 2021-02-09 浙江臻镭科技股份有限公司 Multilayer stacked longitudinally interconnected radio frequency structure and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6412098B2 (en) 1989-02-28

Similar Documents

Publication Publication Date Title
US5644163A (en) Semiconductor device
US6330158B1 (en) Semiconductor package having heat sinks and method of fabrication
EP0509825A2 (en) Package structure for semiconductor device
JPH07169882A (en) Molded integrated circuit package
KR960012647B1 (en) Semiconductor device and manufacture method
US4292647A (en) Semiconductor package and electronic array having improved heat dissipation
JPS60143653A (en) Sealing and cooling mechanism of package
JPS62249429A (en) Semiconductor device
JPH08264688A (en) Ceramic package for semiconductor
JPH09213847A (en) Semiconductor integrated circuit device, manufacture thereof, and electronic device equipped therewith
JPH05206320A (en) Multi-chip module
JPH0574985A (en) Semiconductor element mounting structure
JP2501279B2 (en) Semiconductor package
JPS63190363A (en) Power package
JPS62281453A (en) Chip carrier module
JPH05198708A (en) Semiconductor integrated circuit device
JPH03248449A (en) Semiconductor device with heat sink
JPS60226149A (en) Ceramic package with heat sink
JPH0878616A (en) Multi-chip module
JPH0290555A (en) Semiconductor device
JPH0797616B2 (en) Method for manufacturing semiconductor device
JPH05275578A (en) Semiconductor device
KR100264644B1 (en) Module package
JP3335657B2 (en) Semiconductor package
JPH04348061A (en) Package for semiconductor device

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term