JPS6014327A - Multiplying circuit for digital signal - Google Patents
Multiplying circuit for digital signalInfo
- Publication number
- JPS6014327A JPS6014327A JP12022683A JP12022683A JPS6014327A JP S6014327 A JPS6014327 A JP S6014327A JP 12022683 A JP12022683 A JP 12022683A JP 12022683 A JP12022683 A JP 12022683A JP S6014327 A JPS6014327 A JP S6014327A
- Authority
- JP
- Japan
- Prior art keywords
- multiplier
- signal
- maximum value
- digital signal
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49942—Significance control
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Picture Signal Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、デジタル・テレビジョン映像信号の利得制御
を行なうためのデジタル信号乗算回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal multiplication circuit for controlling the gain of a digital television video signal.
従来、デジタル化された映像信号の利得制御のために乗
算器が使用されているが、従来の乗算器は、乗算結果の
ビット数が多くなるため、乗算器の後段に続く回路の回
路数(ビット数等)が多くなるという欠点がある。また
、一般にこの種利得制御回路は、1つの装置の中で多段
に接続されることが多いため、後段になるほどビット数
の多い乗算器が必要となる。ビット数の増加を防ぐため
には、各乗算器ごとに丸め回路等が必要であり、回路が
複雑にならざるを得ない。Traditionally, multipliers have been used to control the gain of digitized video signals. The disadvantage is that the number of bits, etc.) increases. Furthermore, since this type of gain control circuit is generally connected in multiple stages within one device, multipliers with a larger number of bits are required in later stages. In order to prevent the number of bits from increasing, a rounding circuit or the like is required for each multiplier, which inevitably makes the circuit complicated.
本発明の目的は、」二連の従来の欠点を解決し、簡単な
回路で実用的に充分な乗算精度を有するデジタル信号乗
算回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve two conventional drawbacks and provide a digital signal multiplication circuit that is simple and has practically sufficient multiplication accuracy.
本発明の乗算回路は、デジタル信号と該デジタル信号の
利得を制御するための制御信号とを入力して上記2つの
入力信号を乗算する乗算器と、前記制御信号の最大値を
検出する検知回路と、該検知回路の出力信号によって前
記乗算器の出力信号の最下位ビットに最小単位II I
IIを加算する加算器とを備えて、前記制御信号が最
大値のときには、前記乗算器の出力信号に最小単位“°
l°°を加算して出力することを特徴とする。The multiplication circuit of the present invention includes a multiplier that inputs a digital signal and a control signal for controlling the gain of the digital signal and multiplies the two input signals, and a detection circuit that detects the maximum value of the control signal. and the least significant bit of the output signal of the multiplier by the output signal of the detection circuit.
and an adder for adding up the multiplier, and when the control signal is at the maximum value, the output signal of the multiplier has a minimum unit "°
It is characterized by adding l°° and outputting it.
次に、本発明について、図面を参照して詳細に説明する
。Next, the present invention will be explained in detail with reference to the drawings.
図は、本発明の一実施例を示すブロック図である。すな
わち、入力端子1からデジタル化されたテレビジョン映
像信号が入力し、入力端子2から」二股映像信号の利得
制御のための制御信号が入力する。乗算器3は、上記2
つの入力信号を乗算する乗算器であるが、出力信号のビ
ット数は、入力信号のビット数と同じである。検知回路
4は、前記入力端子2から入力した制御信号の最大値を
検出するとハイレベルを出力して切替器を切替え制御す
る。切替器7は、データ発生器9とデータ発生器8の出
力する最小単位の信号” 1 ”および0゛を入力し、
前記検知回路4からハイレベルが供給されたときは、“
1”を選択出力し、検知回路4の出力がローレベルのと
きは“0″を選択出力する。加算器5は、乗算器3の出
力する乗算結果6の最下位ビットに切替器7の出力信号
” o ”またはt ”を加算して、出力端子10に出
力する。The figure is a block diagram showing one embodiment of the present invention. That is, a digitized television video signal is input from input terminal 1, and a control signal for gain control of the bifurcated video signal is input from input terminal 2. Multiplier 3 is
Although this is a multiplier that multiplies two input signals, the number of bits of the output signal is the same as the number of bits of the input signal. When the detection circuit 4 detects the maximum value of the control signal input from the input terminal 2, it outputs a high level to control the switching device. The switch 7 inputs the minimum unit signals "1" and 0 " outputted by the data generator 9 and the data generator 8,
When a high level is supplied from the detection circuit 4, “
When the output of the detection circuit 4 is at a low level, it selects and outputs "0".The adder 5 selects and outputs "0" from the output of the switch 7 to the least significant bit of the multiplication result 6 output from the multiplier 3. The signal “o” or t” is added and outputted to the output terminal 10.
一例として、デジタル映像入力信号および制御信号が共
に8ビットであり、その値が、16進表示でそれぞれ、
FF 、FFである場合を考えると乗算結果は、FFX
FF=FEO1(16進表示)となる。すなわち、16
ビツトが必要である。乗算結果を、8ビツトとすると、
丸め等を行なわない時は、FEとなって01のエラーを
含むことになる。これをそのまま使用すると、乗算回路
が多段に接続されている場合は、上記エラーが累積され
ていくことになる。乗算ごとに丸めや切り」−げを行な
えばよいが、回路数が多く複雑となる。本実施例におい
ては、このとき、検知器4が制御信号が最大値(FF)
であることを検出して、切替器7にハイレベルを供給し
、切替器7は“l“を選択出力するから、加算器5は乗
算器3の乗算結果6(今、FEである)に“1 ”を加
算出力する。すなわち、FFを出力する。従って、この
ような回路が多段接続された場合であっても、制御入力
が最大値1である乗算回路についてのエラー加算はない
。制御信号が最大値1でなく、0〜1未満の乗算回路で
は、エラーを生じるが、このエラーは、最小単位“1°
°以下である。As an example, the digital video input signal and the control signal are both 8 bits, and their values are respectively expressed in hexadecimal.
Considering the case of FF and FF, the multiplication result is FFX
FF=FEO1 (displayed in hexadecimal). That is, 16
Bits are required. If the multiplication result is 8 bits, then
If rounding or the like is not performed, the result will be FE and will contain an error of 01. If this is used as is, the above-mentioned errors will accumulate if the multiplication circuits are connected in multiple stages. It would be possible to perform rounding or truncating for each multiplication, but this would require a large number of circuits and become complicated. In this embodiment, at this time, the detector 4 detects that the control signal is at the maximum value (FF).
is detected, and supplies a high level to the switch 7, and the switch 7 selects and outputs "l", so the adder 5 outputs the multiplication result 6 (currently FE) of the multiplier 3. Add “1” and output. That is, it outputs FF. Therefore, even if such circuits are connected in multiple stages, there will be no error addition for the multiplication circuit whose control input has a maximum value of 1. In a multiplication circuit where the control signal does not have a maximum value of 1, but is between 0 and less than 1, an error will occur, but this error will occur in the minimum unit of 1°.
° or less.
一般に乗算回路を2つのテレビジョン映像信号の混合器
として使用する場合は、2つの乗算回路を並列に接続し
、それぞれに供給する制御信号を0〜1の間で相互に補
数となるようにしている。そして、制御信号をO〜1に
変化させて、この間に2つの映像信号を切り替えるので
あるから、切り替え途中のものは1つだけであり、多段
に接続された乗算回路が同時に利得制御されることはな
い。従って、」二股エラーが累積されることはない。ま
た、画像切り替え途中の前記エラーは、視覚では感知さ
れ難く、問題とならない。問題は、多段に接続された乗
算回路のうち、制御信号の最大値1で制御されている多
数の乗算回路のエラーが累積することを防止することで
ある。本実施例では、各乗算回路は、制御入力が最大値
1のとき、乗算エラーとなる値が加算されてエラーが除
去されているから、複数の乗算回路を多段接続した場合
においても、正しい結果が得られるという効果がある。Generally, when a multiplier circuit is used as a mixer for two television video signals, the two multiplier circuits are connected in parallel, and the control signals supplied to each are set to be mutually complementary between 0 and 1. There is. Then, since the control signal is changed from O to 1 and two video signals are switched during this time, only one signal is being switched, and the multiplier circuits connected in multiple stages are gain-controlled at the same time. There isn't. Therefore, no two-way errors are accumulated. Furthermore, the error during image switching is difficult to detect visually and does not pose a problem. The problem is to prevent errors from accumulating in a large number of multiplier circuits that are controlled by the maximum value 1 of the control signal among multiplier circuits connected in multiple stages. In this embodiment, when the control input is the maximum value 1, each multiplier circuit adds the value that causes a multiplication error and removes the error. Therefore, even when multiple multiplier circuits are connected in multiple stages, the correct result is obtained. This has the effect of providing.
以上のように、本発明においては、制御入力の最大値を
検知すると乗算器の出力に最小単位゛1°′を加算して
出力するように構成したから、簡単な回路構成で乗算エ
ラーのない利得制御が可能となるという効果がある。As described above, in the present invention, when the maximum value of the control input is detected, the minimum unit ``1°'' is added to the output of the multiplier and output, so the circuit configuration is simple and there is no multiplication error. This has the effect of making gain control possible.
図は本発明の一実施例を示すブロック図である。
図において、1,2:入力端子、3:乗算器、4:検知
回路、5:加算器、6:乗算器3の乗算結果、7:切替
器、8,9:データ発生器、10:出力端子。
出願人 日本電気株式会社
代理人 弁理士 住田俊宗The figure is a block diagram showing one embodiment of the present invention. In the figure, 1, 2: input terminal, 3: multiplier, 4: detection circuit, 5: adder, 6: multiplication result of multiplier 3, 7: switch, 8, 9: data generator, 10: output terminal. Applicant: NEC Corporation Agent: Patent Attorney: Toshimune Sumita
Claims (1)
制御信号とを入力して上記2つの入力信号を乗算する乗
算器と、前記制御信号の最大値を検出する検知回路と、
該検知回路の出力信号によって前記乗算器の出力信号の
最下位ビットに最小単位゛1“を加算する加算器とを備
えて、前記制御信号が最大値のときには、前記乗算器の
出力信号に最小単位“1゛を加算して出力することを特
徴とするデジタル信号乗算回路。a multiplier that receives a digital signal and a control signal for controlling the gain of the digital signal and multiplies the two input signals; a detection circuit that detects the maximum value of the control signal;
an adder that adds a minimum unit of "1" to the least significant bit of the output signal of the multiplier according to the output signal of the detection circuit; A digital signal multiplication circuit characterized by adding and outputting the unit "1".
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12022683A JPS6014327A (en) | 1983-07-04 | 1983-07-04 | Multiplying circuit for digital signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12022683A JPS6014327A (en) | 1983-07-04 | 1983-07-04 | Multiplying circuit for digital signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6014327A true JPS6014327A (en) | 1985-01-24 |
Family
ID=14780990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12022683A Pending JPS6014327A (en) | 1983-07-04 | 1983-07-04 | Multiplying circuit for digital signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014327A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003097678A (en) * | 2001-09-21 | 2003-04-03 | Fuji Heavy Ind Ltd | Lubricating structure of automatic transmission |
-
1983
- 1983-07-04 JP JP12022683A patent/JPS6014327A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003097678A (en) * | 2001-09-21 | 2003-04-03 | Fuji Heavy Ind Ltd | Lubricating structure of automatic transmission |
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