JPS60142592A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS60142592A JPS60142592A JP24584283A JP24584283A JPS60142592A JP S60142592 A JPS60142592 A JP S60142592A JP 24584283 A JP24584283 A JP 24584283A JP 24584283 A JP24584283 A JP 24584283A JP S60142592 A JPS60142592 A JP S60142592A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- pattern
- nickel layer
- conductive foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はプリント回路板に関し、特には、高密度パター
ンを要求されるプリント回路板の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to printed circuit boards, and more particularly to a method for manufacturing printed circuit boards requiring high density patterns.
電気・電子機器の小型化、軽量化等の要望に応じてプリ
ント回路板は現今極めて広汎に利用され、その製造法に
ついても多方面において改善、研究がなされているが、
近時、前記の要望が厳しくなるに伴ない回路パターンは
微細化の一途をたどっている。このような回路基板の従
来の製造法としては、第１図に示す如く、硬質またはフ
レキシブルな絶縁性のベース材１上に例えば銅箔等の導
電箔２を被着させ、更にその表面にフォトレジスト層３
を同図（１）の如く形成し、次いで所要の回路パターン
に従ってフォトレジスト層３に露光、現像処理を施して
同図（２）のようにレジストパターン３Ａを形成した上
、導電箔２に対しエツチング処理を施すことによシ同図
（３）の如く回路パターン２Ａを形成し、最後にレジス
トパターン３Ａの剥離・除去を行なって同図（４）のプ
リント回路板を得ている。しかし、斯かる方法において
は、回路パターン２Ａを形成している導電箔２はエツチ
ング処理に伴なうサイド・エツチング現象によってその
両側面がえぐられて断面が凹状になシ、従って、回路パ
ターン２Ａが微細なものでは所要のパターン幅を確保で
きないという問題があった。Printed circuit boards are now widely used in response to demands for smaller, lighter electrical and electronic devices, and improvements and research are being made in many areas in their manufacturing methods.
In recent years, as the above-mentioned requirements have become stricter, circuit patterns have become increasingly finer. As shown in FIG. 1, the conventional manufacturing method for such a circuit board involves depositing a conductive foil 2, such as copper foil, on a hard or flexible insulating base material 1, and then coating the surface with a conductive foil 2. resist layer 3
The photoresist layer 3 is then exposed and developed according to the required circuit pattern to form a resist pattern 3A as shown in (2) of the same figure. By performing etching, a circuit pattern 2A is formed as shown in FIG. 3(3), and finally, the resist pattern 3A is peeled off and removed to obtain a printed circuit board as shown in FIG. 4(4). However, in such a method, both sides of the conductive foil 2 forming the circuit pattern 2A are hollowed out due to the side etching phenomenon accompanying the etching process, resulting in a concave cross section. There is a problem in that a required pattern width cannot be secured if the pattern is minute.
本発明は、前記問題を好適に解消するようにしたプリン
ト回路板の製造法を提供するものである。The present invention provides a method for manufacturing a printed circuit board that suitably solves the above problems.
本発明に係るプリント−回路板の製造法によれば、ベー
ス材上に被着させた導電箔の表面にニッケル層を形成し
た後にエツチング処理を施して回路パターンを得ること
によシ、回路パターンのサイドエツチング量を極小化し
ている。According to the method for manufacturing a printed circuit board according to the present invention, a nickel layer is formed on the surface of a conductive foil deposited on a base material, and then an etching process is performed to obtain a circuit pattern. The amount of side etching is minimized.
このようなニッケル層は、導電箔に無電解メッキ法、電
解メッキ法またはクラッド法等によって形成することが
できる。Such a nickel layer can be formed on the conductive foil by electroless plating, electrolytic plating, cladding, or the like.
以下、第２図に示す実施例を参照しながら本発明を更に
詳細に説明する。同図において、説明の便宜上、第１図
と同一の符号はそれらと同一の構成侠素な示している。Hereinafter, the present invention will be explained in more detail with reference to the embodiment shown in FIG. In this figure, for convenience of explanation, the same reference numerals as in FIG. 1 indicate the same elements.
工程に従って説明すると、第２図（１）ＶＣ示すように
、ベース材ＩＦｃ被着させた導電箔２の表面にニッケル
層４を積層形成する。その方法としては、導電箔２に、
ニッケルを無電解メッキ法、電解メッキ法またはクラッ
ド法等によって接合するもので、その場合、ニッケル層
４の厚さは、導電箔２との金言」厚さの５〜５０係とす
ることが望ましい。次いで、同図（２）に示すように、
ニッケル層４にフォトレジスト層３を形成せしめ、同図
（３１Ｖｃ示すように、フォトレジスト層３に対する露
光・現像処理を施すことによシレジストパターン３Ａを
形成し、しかる後、同図（４）に示すように、導電箔２
及びニッケル層４にエツチング処理を施すことによシ、
これら両者から成る回路パターン５を形成し、最後に、
同図（５）に示すように、レジストパターン３Ａの剥離
・除去を行なって、ベース材１上にニッケル導電部材と
からなる所要の回路パターン５を形成したプリント回路
板を得る。To explain the steps, as shown in FIG. 2 (1) VC, a nickel layer 4 is laminated on the surface of the conductive foil 2 on which the base material IFc is deposited. As a method, on the conductive foil 2,
Nickel is bonded by electroless plating, electrolytic plating, cladding, etc. In this case, the thickness of the nickel layer 4 is preferably 5 to 50 times the thickness of the conductive foil 2. . Next, as shown in (2) of the same figure,
A photoresist layer 3 is formed on the nickel layer 4, and a photoresist pattern 3A is formed by exposing and developing the photoresist layer 3 as shown in the same figure (31Vc). As shown in FIG.
And by etching the nickel layer 4,
A circuit pattern 5 consisting of these two is formed, and finally,
As shown in FIG. 5(5), the resist pattern 3A is peeled off and removed to obtain a printed circuit board in which a desired circuit pattern 5 made of a nickel conductive material is formed on the base material 1.
このような方法によれば、ニッケルのエツチング特性に
よって、エツチング時にニッケル層４の部分におけるサ
イド・エツチングが殆んど生ぜず、従って、レジストパ
ターン３Ａの厚みとの相乗効果によってエツチング時に
導電箔２とニッケル層４とから成る導電部分のサイドエ
ツチング量が全体的に大きく減少する。その結果、微細
な回路パターン５の寸法精度の向上を図ることができる
。また、例えばプリント・コイル等の如く導体抵抗をコ
ントロールする必要のある場合に、ニッケル層４の厚さ
を大きくすればエツチング時間に対するサイドエツチン
グ量を自由に設定し易くなるので、パターン精度を向上
させることができる他、前述したようなサイド・エツチ
ング量の減少効果によって形成すべきパターンの安定化
も計れる。According to this method, due to the etching properties of nickel, side etching hardly occurs in the nickel layer 4 during etching, and therefore, due to the synergistic effect with the thickness of the resist pattern 3A, the conductive foil 2 and The amount of side etching of the conductive portion consisting of the nickel layer 4 is greatly reduced overall. As a result, the dimensional accuracy of the fine circuit pattern 5 can be improved. Furthermore, when it is necessary to control the conductor resistance, such as in printed coils, for example, increasing the thickness of the nickel layer 4 makes it easier to freely set the amount of side etching relative to the etching time, improving pattern accuracy. In addition, the pattern to be formed can be stabilized by the effect of reducing the amount of side etching as described above.
上記のとおり、本発明に係るプリント回路板の製造法は
、回路パターンのサイド・エツチング量を極小化したも
のであるため、回路パターンの寸法精度を格段に向上さ
せることができるとともに、微細パターンでも十分な所
要幅が得られ、従って、回路パターンの高密度化への要
求に応えるものとして有用性が極めて高いものである。As mentioned above, the printed circuit board manufacturing method according to the present invention minimizes the amount of side etching of the circuit pattern, so it is possible to significantly improve the dimensional accuracy of the circuit pattern, and even with fine patterns. A sufficient required width can be obtained, and therefore, it is extremely useful as a device that meets the demand for higher density circuit patterns.
第１図（１）〜（４）は従来のプリント回路板の製造法
を概念的に示す工程説明図、第２図は本発明に係るプリ
ント回路板の製造法の一実施例を概念的に示す工程説明
図である。
１・・・ベース材、２・・・導？！［、４・・・ニッケ
ル層、５・・・回路パターン
出願人 日本メクトロン株式会社
第１図
（１）
（４）
第２図
（１）Figures 1 (1) to (4) are process explanatory diagrams conceptually showing a conventional printed circuit board manufacturing method, and Figure 2 conceptually shows an embodiment of the printed circuit board manufacturing method according to the present invention. FIG. 1... Base material, 2... Conductor? ! [, 4...Nickel layer, 5...Circuit pattern applicant Nippon Mektron Co., Ltd. Figure 1 (1) (4) Figure 2 (1)
Claims (1)
成した後、これら導電箔およびニッケル層にエツチング
処理を施して所要の回路パターンを形成することを特徴
とするプリント回路板の製造法。A method for manufacturing a printed circuit board, which comprises forming a nickel layer on the surface of a conductive foil deposited on a base material, and then etching the conductive foil and the nickel layer to form a desired circuit pattern. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24584283A JPS60142592A (en) | 1983-12-29 | 1983-12-29 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24584283A JPS60142592A (en) | 1983-12-29 | 1983-12-29 | Method of producing printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60142592A true JPS60142592A (en) | 1985-07-27 |
Family
ID=17139659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24584283A Pending JPS60142592A (en) | 1983-12-29 | 1983-12-29 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60142592A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331193A (en) * | 1986-07-24 | 1988-02-09 | 三井金属鉱業株式会社 | Method of forming conductor pattern of printed wiring board |
| JPH02220087A (en) * | 1989-02-21 | 1990-09-03 | Okamoto Ind Inc | Copying preventing sheet |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5118858A (en) * | 1974-07-30 | 1976-02-14 | Shin Kobe Electric Machinery | Insatsukairobanno seizoho |
-
1983
- 1983-12-29 JP JP24584283A patent/JPS60142592A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5118858A (en) * | 1974-07-30 | 1976-02-14 | Shin Kobe Electric Machinery | Insatsukairobanno seizoho |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331193A (en) * | 1986-07-24 | 1988-02-09 | 三井金属鉱業株式会社 | Method of forming conductor pattern of printed wiring board |
| JPH02220087A (en) * | 1989-02-21 | 1990-09-03 | Okamoto Ind Inc | Copying preventing sheet |
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