JPS60141129U - Terminal structure of leadless chip carrier - Google Patents

Terminal structure of leadless chip carrier

Info

Publication number
JPS60141129U
JPS60141129U JP2751584U JP2751584U JPS60141129U JP S60141129 U JPS60141129 U JP S60141129U JP 2751584 U JP2751584 U JP 2751584U JP 2751584 U JP2751584 U JP 2751584U JP S60141129 U JPS60141129 U JP S60141129U
Authority
JP
Japan
Prior art keywords
terminal structure
chip carrier
leadless chip
chip
leadless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2751584U
Other languages
Japanese (ja)
Inventor
小川　廣光
谷中　定雄
佐藤　憲雄
長沼　理市
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP2751584U priority Critical patent/JPS60141129U/en
Publication of JPS60141129U publication Critical patent/JPS60141129U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のリードレスチップキャリアを説明するた
めの図、第２図は本考案のリードレスチップキャリアの
端子構造を説明するための図、第３図は他の実施例を説
明するための図である。 図面において、１０はチップ、１１は端子、１２は基板
、１３はパッド、１４は半田をそれぞれ示す。 第２図 第３図Fig. 1 is a diagram for explaining a conventional leadless chip carrier, Fig. 2 is a diagram for explaining the terminal structure of the leadless chip carrier of the present invention, and Fig. 3 is a diagram for explaining another embodiment. This is a diagram. In the drawings, 10 is a chip, 11 is a terminal, 12 is a substrate, 13 is a pad, and 14 is solder. Figure 2 Figure 3

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チップの外周側面に多数の端子を有するリードレスチッ
プキャリアにおいて、その端子部がチップの上面から下
面に向って内側に傾斜していることを特徴とするリード
レスチップキャリアの端子構造。1. A terminal structure for a leadless chip carrier having a large number of terminals on the outer circumferential side surface of a chip, wherein the terminal portion is inclined inward from the top surface of the chip toward the bottom surface.
JP2751584U 1984-02-29 1984-02-29 Terminal structure of leadless chip carrier Pending JPS60141129U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2751584U JPS60141129U (en) 1984-02-29 1984-02-29 Terminal structure of leadless chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2751584U JPS60141129U (en) 1984-02-29 1984-02-29 Terminal structure of leadless chip carrier

Publications (1)

Publication Number Publication Date
JPS60141129U true JPS60141129U (en) 1985-09-18

Family

ID=30524540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2751584U Pending JPS60141129U (en) 1984-02-29 1984-02-29 Terminal structure of leadless chip carrier

Country Status (1)

Country Link
JP (1) JPS60141129U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01132120U (en) * 1988-03-01 1989-09-07
JP2004079642A (en) * 2002-08-12 2004-03-11 Kyocera Corp Wiring board
JP2016025239A (en) * 2014-07-22 2016-02-08 京セラ株式会社 Wiring board, electronic device and mounting structure of electronic device
JP2018163908A (en) * 2017-03-24 2018-10-18 旭化成エレクトロニクス株式会社 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01132120U (en) * 1988-03-01 1989-09-07
JP2004079642A (en) * 2002-08-12 2004-03-11 Kyocera Corp Wiring board
JP2016025239A (en) * 2014-07-22 2016-02-08 京セラ株式会社 Wiring board, electronic device and mounting structure of electronic device
JP2018163908A (en) * 2017-03-24 2018-10-18 旭化成エレクトロニクス株式会社 Semiconductor device

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