JPS60136338A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60136338A JPS60136338A JP58243995A JP24399583A JPS60136338A JP S60136338 A JPS60136338 A JP S60136338A JP 58243995 A JP58243995 A JP 58243995A JP 24399583 A JP24399583 A JP 24399583A JP S60136338 A JPS60136338 A JP S60136338A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- wiring
- base film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特にフリップチップ方式の
フェイスダウンボンディング用電極構造を有する半導体
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an electrode structure for flip-chip type face-down bonding.
所要の拡散工程や配線工程を経て完成された半導体装置
（半導体素子チップ）は１次にプラスチックやセラミッ
クのパッケージ内に封止されるが、このときチップの電
極とパッケージの外部導出端子（リード）とを電気的に
接続する必要がある。The completed semiconductor device (semiconductor element chip) is first sealed in a plastic or ceramic package after going through the necessary diffusion and wiring processes, but at this time the chip's electrodes and the package's external terminals (leads) are sealed. It is necessary to electrically connect the
この電気接続には通常チップ電極とリードとを極細線で
接続するワイヤボンディング構造が知られている。ワイ
ヤを使用しないでチップ電極を直接リードに接続するフ
リップチップ方式のフェイスダウンボンディングの利用
が増大する傾向にある。For this electrical connection, a wire bonding structure is generally known in which a chip electrode and a lead are connected using a very thin wire. There is an increasing trend in the use of flip-chip face-down bonding, which connects chip electrodes directly to leads without using wires.
この構造は、チップ表面に形成したチップ電極上にバン
プと通称される半田ポールを予め形成しておき、その表
面を下側に向けてチップをリード上に載置した上でチッ
プをリードに対して加熱押圧することＫより、バンプを
リードに溶着させ、チップ電極とリードとの接続を行な
うことができる。In this structure, solder poles, commonly called bumps, are formed in advance on the chip electrodes formed on the chip surface, and the chip is placed on the leads with the surface facing downward, and then the chip is placed against the leads. By heating and pressing the bumps, the bumps can be welded to the leads and the chip electrodes can be connected to the leads.
この種のバンプ電極は第１図に示す構成とされている。This type of bump electrode has a configuration shown in FIG.
つまり、チップ１の表面絶縁膜（Ｂｔｏｔ膜やＰＳＧ膜
等）２上に形成したＡ２配線３上のパッシベーション膜
４の電極相当箇所にコンタクトホール５を形成し、この
コンタクトホール５内および周囲にわたってＣｒ、Ｃｕ
、Ａｕの多層構造の下地膜６を形成した後、下地膜６上
に半球状の半田バンプ７を形成した構成である（工業調
査会発行ｒＩＣ化実装技術」Ｐ８１など）。That is, a contact hole 5 is formed at a location corresponding to the electrode of the passivation film 4 on the A2 wiring 3 formed on the surface insulating film (Btot film, PSG film, etc.) 2 of the chip 1, and Cr is formed in and around the contact hole 5. , Cu
, after forming a base film 6 with a multilayer structure of Au, hemispherical solder bumps 7 are formed on the base film 6 (for example, p. 81 of ``RIC Mounting Technology'' published by the Industrial Research Institute).
しかしながら、この構造では、その製造方法に関係され
る次のような問題が生じることが本発明者により明らか
にされた。即ち、パッシベーション膜４を構成する５ｉ
０ｚ膜にコンタクトホール５を形成する方法は％Ｓｉｎ
、膜４上に形成したホトレジスト８をマスクにしてウェ
ットエツチングによりスパッタＳｉｎ、膜４にホール５
形成する方法がとられている。このため、ホール５のエ
ツチング断面形状は、スパッタＳ１０．膜４とホトレジ
スト８の接着性が良好であることも相俟つて、同図のよ
うにホール５開口周縁が比較的忙急峻な形状とされる。However, the inventors have found that this structure causes the following problems related to its manufacturing method. That is, 5i constituting the passivation film 4
The method for forming the contact hole 5 in the 0z film is %Sin.
Using the photoresist 8 formed on the film 4 as a mask, wet etching is performed to form a hole 5 in the film 4 by sputtering Sin.
A method of forming is being used. Therefore, the etched cross-sectional shape of the hole 5 is the same as that of the sputter S10. Coupled with the good adhesion between the film 4 and the photoresist 8, the opening periphery of the hole 5 has a relatively steep shape as shown in the figure.
このため１次工程で下地膜６を蒸着法により形成したと
きには所謂セル７シヤドウイングによってホール開口周
縁内側への下地膜６の付着が不良となり、下地膜６が開
口周縁直下の領域９で断線状態となってＡＡ配線３との
接続不良が生じ、更に下地膜６上に形成した半田バンプ
７とＡ２配線３との接続不良が生じてチップ電極接続の
信頼性を低下させる。また、断線状態に至らないまでも
下地膜６のホール開口周縁内側（略領域９０部分）にク
ラックが生じることがある。後工程における下地膜６の
エツチングマスク用のホトレジスト（図示せず）の剥離
液がこのクラックを通して下層のＣｕ、Ｃｒ層を浸蝕し
、上層のＡｕ層の膜剥れを生起させる。これＫより、良
好な半田バンプ７の形成が阻害され或いは前述のように
接続の信頼性が低下されるという問題が生じる。For this reason, when the base film 6 is formed by vapor deposition in the first step, the adhesion of the base film 6 to the inner side of the hole opening periphery becomes poor due to so-called cell 7 shadowing, and the base film 6 becomes disconnected in the region 9 immediately below the opening periphery. As a result, a connection failure with the AA wiring 3 occurs, and a connection failure also occurs between the solder bump 7 formed on the base film 6 and the A2 wiring 3, reducing the reliability of the chip electrode connection. Further, even if the wire does not become disconnected, cracks may occur inside the hole opening periphery of the base film 6 (approximately in the area 90). A stripping solution for the photoresist (not shown) for the etching mask of the base film 6 in the subsequent process corrodes the lower Cu and Cr layers through this crack, causing film peeling of the upper Au layer. This K causes a problem that the formation of good solder bumps 7 is inhibited or the reliability of the connection is reduced as described above.
本発明の目的は半田バンプの下地膜における断線やクラ
ック発生等を防止し、これにより良好な半田バンプの形
成を可能としかつチップ電極における接続の信頼性の向
上を達成することのできるＣＣＢ構造を備えた半導体装
置を提供するととＫある。The purpose of the present invention is to create a CCB structure that can prevent wire breakage and crack generation in the base film of solder bumps, thereby making it possible to form good solder bumps and improving the reliability of connections at chip electrodes. It is possible to provide a semiconductor device equipped with the following.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、電極箇所の絶縁膜に形成するコンタクトホー
ルの断面形状を、ホール開口周縁部において比較的緩や
かな傾斜のテーパ形状に形成することにより、下地膜の
形成に際しての所謂セル７シヤドウイング現象を防止し
、これにより下地膜の断線やクラックの発生防止を図っ
て良好な半田バンプの形成を可能としかつ電極における
接続の信ｉ性の向上を達成するものである。That is, by forming the cross-sectional shape of the contact hole formed in the insulating film at the electrode location into a tapered shape with a relatively gentle slope at the periphery of the hole opening, the so-called cell 7 shadowing phenomenon when forming the base film can be prevented. This makes it possible to form good solder bumps by preventing disconnections and cracks in the base film, and improves the reliability of connections at the electrodes.
第２図は本発明の半導体装置の要部の断面図を示す。図
において、１１は所定の拡散工程や配線工程を経てその
主面に種々の素子を形成した半導体チップであり、その
最上層のスパッタにより形成したＳｉｎ、（以下スパッ
タｓｉｏ、という）或はＰＳＧ等の絶縁膜１２上にＡ！
配線１３を所定のパターン形状忙形成して℃・る。この
Ａ−ｇｆｉｉＪ１１３上Ｋ ハスバッタ５ｉｏｔかもな
る最終パッシベーション［１４ヲ形成し、このパッシベ
ーション膜１４の電極形成位置にはコンタクトホール１
５を形成して前記ＡＡ配線１３の一部を露呈させている
。FIG. 2 shows a sectional view of essential parts of the semiconductor device of the present invention. In the figure, 11 is a semiconductor chip on which various elements are formed on its main surface through a predetermined diffusion process and wiring process, and its top layer is formed by sputtering such as Sin, (hereinafter referred to as sputter SIO), PSG, etc. A! on the insulating film 12 of
The wiring 13 is formed into a predetermined pattern shape. A final passivation [14] is formed on this A-gfiiJ113, and a contact hole 1 is formed at the electrode formation position of this passivation film 14.
5 to expose a part of the AA wiring 13.
この場合、コンタクトホール１５はその開口周縁部１５
ａを比較的緩やかな傾余）のテーパ形状とした断面形状
に構成している。その上で＊ Ｃｒ ＋ ＣｕＡｕの多
層構造の下地膜１６をＢＬＭ（ボール・リミテッド・メ
タライゼーション）電極としてコンタクトホール１５内
面、１配線１３上面ないしコンタクトホール１５の周囲
部分圧わたって形成し、この下地膜１６上忙半球状の半
田バンプ１７を形成してＣＣＢ構造を構成している。In this case, the contact hole 15 has an opening periphery 15
It has a tapered cross-sectional shape with a relatively gentle inclination. On top of that, a base film 16 with a multilayer structure of Cr + CuAu is formed as a BLM (ball limited metallization) electrode over the inner surface of the contact hole 15, the upper surface of one wiring 13, and the partial pressure around the contact hole 15. A hemispherical solder bump 17 is formed on the earth's membrane 16 to constitute a CCB structure.
以上の構成のＣＣＢｔｆｆ造の製造方法を説明する。A method of manufacturing the CCBtff structure having the above configuration will be explained.
先ず、第３同国のように、半導体チップ１１上に形成し
たＡ−４ｉｔ配線１３およびバッジベージ日ン膜（スパ
ッタ５ｔｏｔ ＞ ｉ ４上圧プラズマＣＶＤ法により
形成した５ｉＮ（以下プラズマＳｉＮという）膜１８を
形成する。次いで、その上にホトレジスト膜を塗布した
後、同図（刊のように電極形成相当位置のみ開口される
ようにホトリソグラフィ技術によりホトレジスト膜１９
をマスクとして前記プラズマＳｉＮ膜１８をドライエツ
チングする。First, as in the third country, A-4it wiring 13 formed on a semiconductor chip 11 and a 5iN (hereinafter referred to as plasma SiN) film 18 formed by a badge-base solar film (sputter 5tot>i4 high pressure plasma CVD method) are Next, after applying a photoresist film thereon, the photoresist film 19 is formed using photolithography technology so that only the positions corresponding to electrode formation are opened, as shown in the same figure (published in 2013).
Using this as a mask, the plasma SiN film 18 is dry etched.
次に、前記ホトレジスト膜１９およびプラズマＳｉＮ膜
１８をマスクとし又、前記パッシベーション膜１４をフ
ッ酸系のエツチング液を用いてウェットエツチングする
。これにより、同図（Ｃ）Ｋ示す断面形状のコンタクト
ホール１５が形成され、ＡＡ配配線３の一部が露呈され
る。このとき、パッシベーション膜１４とし又のスパッ
タ５ｌｏｔはプラズマ５ｔＮｉｓとの接着性が余り良好
ではないことから、エツチングの進行に伴なってエツチ
ング液はパッシベーション膜１４とプラズマＳｉＮ膜１
８との間に進入し外方へ向かってのエツチングを促進さ
せる。このとき、プラズマＳｌＮ膜１８も同時にエツチ
ングされ、これにより、形成されたコンタクトホール１
５は、開口周縁部１５ａが外方に大きくエツチングされ
たことにより比較的緩やかな傾斜角度のテーバ形状に形
成される。Next, using the photoresist film 19 and the plasma SiN film 18 as masks, the passivation film 14 is wet-etched using a hydrofluoric acid-based etching solution. As a result, a contact hole 15 having a cross-sectional shape shown in FIG. At this time, since the adhesion between the passivation film 14 and the sputtered 5lot with the plasma 5tNis is not very good, as the etching progresses, the etching solution is applied to the passivation film 14 and the plasma SiN film 1.
8 and promotes etching outward. At this time, the plasma SlN film 18 is also etched at the same time, thereby forming the contact hole 1.
5 is formed into a tapered shape with a relatively gentle inclination angle by greatly etching the opening peripheral edge 15a outward.
次いで、同図■のようにホトレジスト膜１９とプラズマ
ＳｉＮ膜１８をＣＦ、のプラズマエツチング等により除
去した後、全面に下地膜１６を形成する。この下地膜１
６は下からＣｒ、Ｃｕ、Ａｕの多層構造とされ、蒸着法
により℃形成される。Next, as shown in (2) in the figure, the photoresist film 19 and plasma SiN film 18 are removed by CF plasma etching or the like, and then a base film 16 is formed on the entire surface. This base film 1
6 has a multilayer structure of Cr, Cu, and Au from the bottom, and is formed by vapor deposition at .degree.
このとき、コンタクトホール１５は開口周縁部１５ａが
緩やかな傾斜のテーパ状に形成されているので従来のよ
うなセルフシャドウィング現象が生じることはなく、し
たがって断線やクラックのない均一かつ良質の下地膜１
６が形成できる。At this time, since the opening peripheral edge 15a of the contact hole 15 is formed in a tapered shape with a gentle slope, the self-shadowing phenomenon unlike in the conventional case does not occur. 1
6 can be formed.
その上で、同図（ト）のようにホトレジスト膜２０を積
層してこれを電極形状にパターニングし、かつこれをマ
スクにして前記下地膜１６をエツチングする。エツチン
グ後、ホトレジスト膜２０をエツチング除去する。この
とき、下地膜１６にはクラック等は殆んど発生していな
いため、ホトレジスト膜２０のエツチング除去液、つま
り剥離液による下地膜１６のダメージは生じない。下地
膜１６はＢＬＭ電極として構成される。Thereafter, a photoresist film 20 is laminated and patterned into an electrode shape as shown in FIG. After etching, the photoresist film 20 is removed by etching. At this time, since almost no cracks or the like are generated in the base film 16, the base film 16 is not damaged by the etching removal solution for the photoresist film 20, that is, by the stripping solution. The base film 16 is configured as a BLM electrode.
次いで、同図いのようにチップ１１上にマスク２１をセ
ットし、半田敏着を施すことＫより下地膜１６上に半田
厚膜１７Ａを形成し、その後この半田厚膜ｉ７Ａを加熱
溶融すれば半田は表面張力により半球状のバンプｉ７と
なり、第２図に示したＣＣＢ措造が完成されることにな
る。Next, as shown in the same figure, a mask 21 is set on the chip 11 and solder is applied to form a thick solder film 17A on the base film 16, and then this thick solder film i7A is heated and melted. The solder becomes a hemispherical bump i7 due to surface tension, completing the CCB structure shown in FIG.
一方、第４図に示す製造方法も考えられる。On the other hand, a manufacturing method shown in FIG. 4 is also considered.
即ち、第４図（４）のように、スパッタＳｉ０！からな
るパッシベーション藤１４にホトレジスト膜８をマスク
として従来と同様にウェットエツチングによりコンタク
トホール１５を形成する。この状態ではコンタクトホー
ル１５の開口周縁部は急峻な形状にあることは前述の通
りである。次いで。That is, as shown in FIG. 4 (4), sputtered Si0! A contact hole 15 is formed in the passivation layer 14 by wet etching as in the conventional method using the photoresist film 8 as a mask. As described above, in this state, the opening periphery of the contact hole 15 has a steep shape. Next.
同図（Ｂｌのようにホトレジストや５ＯＧ（スピンオン
グラス）等のレジスト２２を上面に薄く塗布し、その後
このレジスト２２とスパッタＳｉ０＊の選択比が＝１．
０の条件でドライエツチングを行なう。As shown in the same figure (Bl), a resist 22 such as photoresist or 5OG (spin-on glass) is applied thinly to the upper surface, and then the selectivity ratio between this resist 22 and sputtered Si0* is set to 1.
Dry etching is performed under the condition of 0.
これにより、エツチングの初期はレジスト２２のみがエ
ツチングされ、その後同図（Ｂ）のようにコンタクトホ
ール１５の開口周縁部１５ａであるパッシベーション膜
１４の一部が露呈された後はレジスト２２とパッシベー
ション膜１４が同時にエツチングされる。そして５通常
ではコンタクトホー／Ｌ４５（’）開口周縁部が最先に
露呈されるためにここのエツチングが進行される。As a result, at the initial stage of etching, only the resist 22 is etched, and after that, as shown in FIG. 14 are etched at the same time. 5. Normally, the peripheral edge of the contact hole/L45(') opening is exposed first, so that etching proceeds there.
したがって、適宜のエツチングでこれを停止してレジス
ト２２を除去すれば、同図（ｃｌのように開口周縁部１
５ａがエツチングされて緩やがな傾斜とされた断面形状
のコンタクトホール１５が形成される。以下、第２図月
以下と同じ工程によりバンプ電極構造を完成することが
できる。この場合にも、コンタクトホール１５の前述の
形状によって断線やクラックのない下地膜１６を形成で
き。Therefore, if this is stopped by appropriate etching and the resist 22 is removed, the opening periphery 1 can be etched as shown in the same figure (cl).
5a is etched to form a contact hole 15 having a gently sloped cross section. Hereinafter, the bump electrode structure can be completed by the same steps as those shown in Figure 2 and below. In this case as well, the above-described shape of the contact hole 15 makes it possible to form the base film 16 without disconnections or cracks.
良質のバンプを形成できる。Can form high quality bumps.
（１）パッシベーション膜に形成したコンタクトホ−ル
の開口周縁部を比較的緩やかな傾斜のテーバ状に形成し
ているので、ホール内部ないしその周囲に形成する下地
膜のセルフシャドウィング現象を防止して断線、クラッ
クのない下地膜を形成することができ、これにより良好
なバンプを形成して＠極接続の信頼性を向上することが
できる。(1) The opening edge of the contact hole formed in the passivation film is formed in a tapered shape with a relatively gentle slope, which prevents the self-shadowing phenomenon of the base film formed inside or around the hole. Therefore, it is possible to form a base film free from wire breaks and cracks, thereby forming good bumps and improving the reliability of the @-pole connection.
（２）パッシベーション膜上にプラズマ５ｉＮＬＱを形
成した上でコンタクトホールのエツチングを行なえば開
口周縁部の傾斜を緩やかなものにしたホール形状を形成
できるので、従来工程に数工程を付加するだけでバンブ
電極構造の信頼性を格段に向上することができる。(2) By forming plasma 5iNLQ on the passivation film and then etching the contact hole, it is possible to form a hole shape with a gentle slope at the opening periphery. The reliability of the electrode structure can be significantly improved.
（３）従来と同様に形成したコンタクトホールにレジス
ト塗布およびそのエツチング工程を付加するだけで開口
周縁部の傾斜が緩やかなホール形状を形成できるので、
前記（２）の効果と同様にバンブ電極構造の信頼性を向
上できる。(3) By simply adding a resist coating and etching process to a contact hole formed in the same way as before, a hole shape with a gentle slope at the opening periphery can be formed.
Similar to the effect (2) above, the reliability of the bump electrode structure can be improved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、コンタクト
ホールを形成する絶縁膜としてのパッシベーション膜は
スパッタｓｉｏ。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a passivation film as an insulating film for forming contact holes is sputtered.
に限られるものではなく他の材質であってもよい。The material is not limited to , and may be made of other materials.
但し、他の材質を使用したときにはエツチング液を変更
する場合があり、またプラズマＳｉＮ膜に代えた他の膜
を使用する必要が生じることもある。However, when other materials are used, the etching solution may need to be changed, and it may also be necessary to use another film in place of the plasma SiN film.
また、レジストを使用する場合圧も、パッシベーション
膜の材質に応じてレジスト材質やエツチング条件を適宜
変化させる必要がある。なお、下地膜の構造や半田バン
プの形成方法は穏々の変形例が考えられる。Furthermore, when using a resist, it is necessary to appropriately change the pressure, resist material, and etching conditions depending on the material of the passivation film. Incidentally, the structure of the base film and the method of forming the solder bumps may be moderately modified.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体チップの電極
構造に適用した場合について説明したが、それに限定さ
れるものではなく、半導体モジュールを構成する各穏半
導体部品でＣＣＢ構造を備えるもの全てに適用すること
ができる。In the above explanation, the invention made by the present inventor is mainly applied to the electrode structure of a semiconductor chip, which is the background field of application. It can be applied to all moderate semiconductor components having a CCB structure.
第１図は従来構造の断面図、
第２図は本発明のＣＣＢ構造を有する半導体装置の断面
図、
第３図（５）〜（Ｆ′ｌは製造方法を工程順に示す断面
図、第４図（５）〜（０は他の製造方法の工程断面図で
ある。
１１・・・半導体チップ、１３・・・ＡＡ配線、１４・
・・パッシベーション［，１５・・・コンタクトホール
。
１５ａ・・・開口周縁部、１６・・・下地膜、１７・・
・半田バンプ、１８・・・プラズマＳｉＮ、１９・・・
ホトレジスト膜、２０・・・ホトレジスト、２１・・・
マスク、２２・・・レジスト。
第 １ 図
第 ２ 図
第 ３ 図FIG. 1 is a sectional view of a conventional structure, FIG. 2 is a sectional view of a semiconductor device having a CCB structure according to the present invention, FIGS. Figures (5) to (0 are process cross-sectional views of other manufacturing methods. 11... Semiconductor chip, 13... AA wiring, 14...
... Passivation [,15... Contact hole. 15a... Opening periphery, 16... Base film, 17...
・Solder bump, 18...Plasma SiN, 19...
Photoresist film, 20... Photoresist, 21...
Mask, 22...Resist. Figure 1 Figure 2 Figure 3
Claims (1)
した上に半田バンプを形成してなる電極構造を備える半
導体装置であって、前記コンタクトホールはその開口周
縁部を緩やかな傾斜角度のテーパ形状に形成したことを
特徴とする半導体装置。 ２、Ａ、６配線上のバッジベージリン膜としての絶縁膜
にコンタクトホールを形成し、Ｃｒ、Ｃｕ＋Ａｕの多層
構造の下地膜を蒸着形成してなる特許請求の範囲第１項
記載の半導体装置。 ３、バックペーション膜にスパッタＳ ｉ Ｏｔヲ使用
し、その上にこれと接着性の低いプラズマＳｉＮ膜を形
成しかつこれをマスクとしてコンタクトホールをエツチ
ング形成してなる特許請求の範囲第１項又は第２項記載
の半導体装置。[Claims] 1. Forming a contact hole in an insulating film on a wiring. A semiconductor device includes an electrode structure in which a base film is formed inside or around the contact hole and a solder bump is formed on the base film, and the contact hole has an opening periphery formed in a tapered shape with a gentle inclination angle. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein a contact hole is formed in an insulating film as a badge phosphorus film on the wirings 2, A, and 6, and a base film having a multilayer structure of Cr, Cu+Au is formed by vapor deposition. 3. Sputter SiOt is used for the backpation film, a plasma SiN film with low adhesion is formed thereon, and a contact hole is etched using this as a mask. 2. The semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243995A JPS60136338A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58243995A JPS60136338A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60136338A true JPS60136338A (en) | 1985-07-19 |
Family
ID=17112146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58243995A Pending JPS60136338A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136338A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196146A (en) * | 1988-02-01 | 1989-08-07 | Matsushita Electron Corp | Semiconductor device |
| US4950623A (en) * | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
| JPH04229627A (en) * | 1990-04-27 | 1992-08-19 | Hughes Aircraft Co | Electric relay section structure and formation method |
| US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
| EP0717441A3 (en) * | 1994-12-13 | 1997-05-02 | At & T Corp | Method of solder bonding a body, e.g. a silicon chip, to another body |
| JP2011512679A (en) * | 2008-02-15 | 2011-04-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Solder interconnection pad structure and manufacturing method thereof |
-
1983
- 1983-12-26 JP JP58243995A patent/JPS60136338A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01196146A (en) * | 1988-02-01 | 1989-08-07 | Matsushita Electron Corp | Semiconductor device |
| US4950623A (en) * | 1988-08-02 | 1990-08-21 | Microelectronics Center Of North Carolina | Method of building solder bumps |
| JPH04229627A (en) * | 1990-04-27 | 1992-08-19 | Hughes Aircraft Co | Electric relay section structure and formation method |
| US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
| US5374893A (en) * | 1992-03-04 | 1994-12-20 | Mcnc | Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon |
| US5381946A (en) * | 1992-03-04 | 1995-01-17 | Mcnc | Method of forming differing volume solder bumps |
| EP0717441A3 (en) * | 1994-12-13 | 1997-05-02 | At & T Corp | Method of solder bonding a body, e.g. a silicon chip, to another body |
| JP2011512679A (en) * | 2008-02-15 | 2011-04-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Solder interconnection pad structure and manufacturing method thereof |
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