JPS60133794A - Method of producing multilayer printed board - Google Patents
Method of producing multilayer printed boardInfo
- Publication number
- JPS60133794A JPS60133794A JP24131083A JP24131083A JPS60133794A JP S60133794 A JPS60133794 A JP S60133794A JP 24131083 A JP24131083 A JP 24131083A JP 24131083 A JP24131083 A JP 24131083A JP S60133794 A JPS60133794 A JP S60133794A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- multilayer printed
- cupric oxide
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は多層プリント基板を構成する中間層の導体パタ
ーンの表面処理方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for surface treatment of a conductor pattern in an intermediate layer constituting a multilayer printed circuit board.
(2)技術の背景
複数枚の中間1−としてのプリント基板に所望の導体パ
ターンを形成し、プリブレーグを介在せしめて積層して
多層プリント基板となす時、それぞれのプリント基板と
プリブレーグとの接着力な確保するためにプリント基板
の導体パターンの表面を粗化して接着面積乞増加する手
法が用いられる。(2) Background of the technology When forming a desired conductor pattern on a plurality of intermediate printed circuit boards and laminating them with a prebrag interposed to form a multilayer printed circuit board, the adhesive strength between each printed circuit board and the prebrag In order to ensure this, a method is used to increase the bonding area by roughening the surface of the conductor pattern on the printed circuit board.
(3)従来技術と問題点
第1図は多層プリント基板の断面図を示し、第2図はス
ルーホール透孔の断面図ン示す0図に於いて1は多層プ
リント基板、2は中間層プリント基板、3は導体パター
ン、4はプリプレ一層、5は表面層プリント基板、6は
スルーホール透孔、7はランド、8はパターンをそれぞ
れ示す0
第1図に示j如く、多層プリント基板lは両面の表面層
のプリント基板5と、複数枚の中間層のプリント基板2
と、それぞれのプリント基板を接合するプリブレーグ層
4とで構成され、それぞれのプリント基板2及び5との
接合は、プリブレーグ層4を介して接合され、それぞれ
のプリント基板2及び50表面とプリブレーグ層4との
接合状態によりて、プリント基板2及び5の接合強度が
左右される。(3) Prior art and problems Figure 1 shows a cross-sectional view of a multilayer printed circuit board, and Figure 2 shows a cross-sectional view of a through hole. The board, 3 is a conductor pattern, 4 is a pre-prepared layer, 5 is a surface layer printed board, 6 is a through hole, 7 is a land, and 8 is a pattern. As shown in Figure 1, the multilayer printed board l is A double-sided surface layer printed circuit board 5 and a plurality of intermediate layer printed circuit boards 2
and a prebrag layer 4 for bonding the respective printed circuit boards.The respective printed circuit boards 2 and 5 are bonded via the prebrag layer 4, and the surfaces of the respective printed circuit boards 2 and 50 and the prebrag layer 4 are bonded to each other. The bonding strength between the printed circuit boards 2 and 5 is influenced by the bonding state between the printed circuit boards 2 and 5.
従がってそれぞれのプリント基板2及び5の接合力を増
加せしめるために、プリブレーグ層4と接するプリント
基板2及び5に形成する導体パターン3の表面を粗化し
て、プリプレーグ4との接合する表面積を増加し又接合
部の投錨効果による方法が一般的である。Therefore, in order to increase the bonding strength between the respective printed circuit boards 2 and 5, the surfaces of the conductor patterns 3 formed on the printed circuit boards 2 and 5 that are in contact with the prepreg layer 4 are roughened to increase the surface area of the conductor patterns 3 that are bonded to the prepreg layer 4. A common method is to increase the anchoring effect of the joint.
このため導体パターン30表面を粗化するのlこ、次亜
塩素酸ソーダと苛性ソーダを主剤とする溶液で黒化処理
し、酸化第二銅の直径1〜2μm1長さ2μ露程度の針
状態ヲ密生して形成せしめて、導体パターン30単位面
積当りの有効表面積を増加せしめると共に、プリブレー
グ層4のエポキシ樹脂との投錨効果を期待して積層成形
し、第2図に示j如く所望ケ所のスルーホールすべき部
分を穿孔して得たスルーホール透孔6を無電解メッキす
る。For this reason, the surface of the conductor pattern 30 is roughened by blackening with a solution containing sodium hypochlorite and caustic soda as main ingredients, and the needles of cupric oxide with a diameter of 1 to 2 μm and a length of 2 μm are formed. The conductor pattern 30 is formed in a dense manner to increase the effective surface area per unit area of the conductor pattern 30, and is laminated to form an anchoring effect with the epoxy resin of the prebrag layer 4. A through-hole 6 obtained by drilling a hole-to-be-hole portion is electrolessly plated.
この時、中間層プリント基板2の接続すべきランド7は
、スルーホール透孔6の内壁薔こ露呈する。At this time, the land 7 to be connected on the intermediate layer printed circuit board 2 exposes the inner wall of the through hole 6.
スルーホール透孔6に無電解メッキを成す前処理として
10チ@度の稀塩酸浴を成″′1″が、2の稀塩酸によ
ってスルーホール透孔6の内壁に露呈する部分より、ラ
ンド70表面の酸化第二銅が容易に還元されて、内壁面
より内部方向の針状の酸化第二銅が除去されて空洞化し
てハローイング状態となり、この空洞内Eこ′屯解買の
液体が浸透し、残留したまま無電解メッキと電解メッキ
とがなされ多層プリント基板lとなり、部品を搭載して
電子機器を構成するパッケージとして使用中に、ランド
7とパターン8との電位差によりマイグレーシロンを生
じ、その間の絶縁抵抗が常態の100万分の1根度に劣
化し、パッケージとしての機能を失することがある。As a pretreatment for performing electroless plating on the through-hole holes 6, a dilute hydrochloric acid bath of 10 degrees Celsius is applied. The cupric oxide on the surface is easily reduced, and the acicular cupric oxide inward from the inner wall surface is removed, forming a cavity and forming a haloing state. After penetrating and remaining, it is subjected to electroless plating and electrolytic plating to form a multilayer printed circuit board l, and when it is used as a package to mount components and configure electronic equipment, migration occurs due to the potential difference between land 7 and pattern 8. , the insulation resistance between them may deteriorate to 1/1,000,000 times less than normal, and the package may lose its function.
従来ランド7とパターン8との最小間隔が500μm以
上である時は、絶縁抵抗の値が尚くかつ劣化時間が艮か
ったために実用的に大なる支障がなかったが、最近の如
くパターンの密度が稠密となりランド7と隣接するパタ
ーン8との最小間隔が100μrrL程度となる時の絶
縁抵抗値は低く、劣化時間が短かくなるため、回路間の
19r要の絶縁抵抗を保持し得なくなっている。Conventionally, when the minimum distance between the land 7 and the pattern 8 was 500 μm or more, there was no practical problem because the insulation resistance value was high and the deterioration time was short, but recently the pattern density has increased. becomes dense and the minimum distance between the land 7 and the adjacent pattern 8 is about 100μrrL, the insulation resistance value is low and the deterioration time becomes short, so it is no longer possible to maintain the insulation resistance of 19r between the circuits. .
(4)発明の目的
本発明は上記従来の欠点にm^、プリント基板(1)接
合面の導体パターンのランドが、スルーホー−3=
ル透孔に露呈したる状態で、透孔内の無電解メッキのた
めの前処地によって、ハローイングを生じないランドを
形成する、多層プリント基板の製造方法の提供を目的と
するものである。(4) Purpose of the Invention The present invention solves the above-mentioned drawbacks of the conventional art, and the land of the conductor pattern on the bonding surface of the printed circuit board (1) is exposed to the through hole. The object of the present invention is to provide a method for manufacturing a multilayer printed circuit board in which a land that does not cause haloing is formed using a pre-surface for electrolytic plating.
(5) 発明の構成
そしてこの目的は本発明によれば、接合すべきプリント
基板の導体パターンを黒化処理して得られた酸化第二@
を予め還元して酸化第−銅又は銅となし、たる後、積層
成形することを特徴とする多層プリント基板の製造方法
を提供することによって達成される。(5) Structure and object of the invention According to the present invention, the second oxide @ obtained by blackening the conductor pattern of the printed circuit board to be bonded.
This is achieved by providing a method for manufacturing a multilayer printed circuit board, which is characterized in that it is reduced in advance to form cupric oxide or copper oxide, which is then laminated and molded.
(6)発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第3図は導体パターンの表面の酸化第二銅による針状態
の模式図で、第4図は第3図の酸化第二銅の還元を示す
模式図である。FIG. 3 is a schematic diagram of the needle state caused by cupric oxide on the surface of the conductive pattern, and FIG. 4 is a schematic diagram showing the reduction of the cupric oxide in FIG. 3.
図に於いて9は銅箔、lOは酸化第二銅、11は第−酸
化鋼、12は還元d、13はイミダゾール被模をそれぞ
れ示す。In the figure, 9 represents copper foil, IO represents cupric oxide, 11 represents secondary oxide steel, 12 represents reduced d, and 13 represents imidazole coating.
多層プリント基板lを構成する中間層のプリン4−
卜基板2と表面層のプリント基板5の積層面の導体パタ
ーン30表面の模式的拡大断面図は、第3図iこ示す如
く、導体パターン3の銅箔9の表面が黒化処理されて酸
化第二銅10が形成され、直径1〜2μ・長さ2μ−程
度の突起が密生する。A schematic enlarged sectional view of the surface of the conductor pattern 30 on the laminated surface of the intermediate layer printed circuit board 4 and the surface layer printed circuit board 5 constituting the multilayer printed circuit board l is shown in FIG. The surface of the copper foil 9 is blackened to form cupric oxide 10, and protrusions with a diameter of 1 to 2 μm and a length of about 2 μm grow densely.
本発明は第3図に示す酸化第二銅10を積層に先立って
稀塩酸等の強酸で容易に還元されにくい酸化第一銅11
又は還元銅12に変換し、積層後所望の位置にスルーホ
ールメッキのための透孔6を穿孔して得た内壁に、導体
パターン30ランド7が露呈した部分ζこ、スルーホー
ル透孔6の内壁を無電解メッキする前処理としての稀塩
酸浴をした時、透孔6に露呈するランド7の表面に、容
易に還元される酸化第二銅10が酸化第一銅11と還元
銅12とに変換されており、ハローイングを生ぜず銅箔
9とプリブレーグ層4との接着部に空洞を生ぜず、電解
質の浴液の浸透を生ぜざるため、隣接するパターン8間
でマイグレーシロンを生ずる拳はない。In the present invention, prior to laminating cupric oxide 10 shown in FIG. 3, cuprous oxide 11 which is not easily reduced with a strong acid such as dilute hydrochloric acid
Alternatively, convert it into reduced copper 12, and after laminating, drill holes 6 for through-hole plating at desired positions on the inner wall, where the conductor pattern 30 land 7 is exposed, the part ζ of the through-hole hole 6. When the inner wall is subjected to a dilute hydrochloric acid bath as a pretreatment for electroless plating, the easily reduced cupric oxide 10 is mixed with cuprous oxide 11 and reduced copper 12 on the surface of the land 7 exposed in the through hole 6. Since no haloing occurs, no cavities are formed at the bond between the copper foil 9 and the prebrag layer 4, and no penetration of the electrolyte bath solution occurs, migration between adjacent patterns 8 is avoided. There isn't.
この酸化第二銅10を酸化第一銅11と還元銅l2に変
換するには、還元作用が緩擬なイミダソール糸のペンソ
トリャゾールを用い、第4図に示す如く酸化第二銅10
を酸化第1@t lと、還元@12にとなし、咽化第−
@llの表面を1μm厚程腿のイミダゾール13の防錆
被模を形成せしめると共にプリプレーグ4のレジンとの
密着性を高める。In order to convert this cupric oxide 10 into cuprous oxide 11 and reduced copper 12, pensotriazole of imidasol yarn, which has a slow reducing action, is used, and as shown in Fig. 4, cupric oxide 10
The oxidation #1@tl and the reduction@12 are the pharyngeal #1 and the reduction @12.
A rust-preventing imidazole 13 on the thigh is formed on the surface of @ll to a thickness of about 1 μm, and the adhesion to the resin of the prepreg 4 is increased.
(7)発明の効果
上記の説明で明らかな如く、本発明の多層プリント基板
の製造方法によれは、スルーホールの内壁と接するラン
ドと隣接するパターン間にマイグレーシヨンを生ずる挙
がないため、稠密なパターンでランドとパターン間の間
隔が極めて狭小なプリント基板1こあっても、絶縁抵抗
の劣化がないため信頼性の高いパッケージを形成し得る
。(7) Effects of the Invention As is clear from the above explanation, the method for manufacturing a multilayer printed circuit board of the present invention prevents migration between the land in contact with the inner wall of the through-hole and the adjacent pattern. Even if there is a single printed circuit board with a similar pattern and extremely narrow spacing between lands and patterns, a highly reliable package can be formed because there is no deterioration in insulation resistance.
第1図は多層プリント基板の断面図を示し、第2図はス
ルーホール透孔の断面図を示し、第3図は導体パターン
の表面の酸化第2銅による針状態の模式図を示し、第4
図は第3図の酸化第二銅還元を示す模式図である。Fig. 1 shows a cross-sectional view of a multilayer printed circuit board, Fig. 2 shows a cross-sectional view of a through hole, Fig. 3 shows a schematic diagram of a needle state caused by cupric oxide on the surface of a conductor pattern, and Fig. 4
The figure is a schematic diagram showing the cupric oxide reduction of FIG. 3.
Claims (1)
基板の接合面の導体パターンの表面を、ソ゛′ 黒化処理して得た酸化第二銅を、イミダゾール形の溶成
で還元した後積層することを%似とする多層プリント基
板の製造方法。[Claims] Cupric oxide obtained by solubilizing the surface of the conductor pattern on the joint surface of the surface layer and intermediate layer printed circuit board constituting the multilayer printed circuit board is melted in imidazole form. A method for manufacturing multilayer printed circuit boards that is similar to that of % reduction and then lamination.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24131083A JPS60133794A (en) | 1983-12-21 | 1983-12-21 | Method of producing multilayer printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24131083A JPS60133794A (en) | 1983-12-21 | 1983-12-21 | Method of producing multilayer printed board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60133794A true JPS60133794A (en) | 1985-07-16 |
JPH0141276B2 JPH0141276B2 (en) | 1989-09-04 |
Family
ID=17072381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24131083A Granted JPS60133794A (en) | 1983-12-21 | 1983-12-21 | Method of producing multilayer printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60133794A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6126292A (en) * | 1984-07-17 | 1986-02-05 | 松下電器産業株式会社 | Ceramic multilayer circuit board and method of producing same |
JPH0187678U (en) * | 1987-12-02 | 1989-06-09 | ||
US4981560A (en) * | 1988-03-25 | 1991-01-01 | Fukuda Metal Foil & Powder Industrial Co., Ltd. | Method of surface treatment of copper foil or a copper clad laminate for internal layer |
WO1995027808A1 (en) * | 1994-04-11 | 1995-10-19 | Electrochemicals, Inc. | Method for treating an oxidized copper film |
-
1983
- 1983-12-21 JP JP24131083A patent/JPS60133794A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6126292A (en) * | 1984-07-17 | 1986-02-05 | 松下電器産業株式会社 | Ceramic multilayer circuit board and method of producing same |
JPH0348676B2 (en) * | 1984-07-17 | 1991-07-25 | Matsushita Electric Ind Co Ltd | |
JPH0187678U (en) * | 1987-12-02 | 1989-06-09 | ||
US4981560A (en) * | 1988-03-25 | 1991-01-01 | Fukuda Metal Foil & Powder Industrial Co., Ltd. | Method of surface treatment of copper foil or a copper clad laminate for internal layer |
WO1995027808A1 (en) * | 1994-04-11 | 1995-10-19 | Electrochemicals, Inc. | Method for treating an oxidized copper film |
Also Published As
Publication number | Publication date |
---|---|
JPH0141276B2 (en) | 1989-09-04 |
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