JPS60133645U - モ−ルド型トランジスタの端子構造 - Google Patents

モ−ルド型トランジスタの端子構造

Info

Publication number
JPS60133645U
JPS60133645U JP2033484U JP2033484U JPS60133645U JP S60133645 U JPS60133645 U JP S60133645U JP 2033484 U JP2033484 U JP 2033484U JP 2033484 U JP2033484 U JP 2033484U JP S60133645 U JPS60133645 U JP S60133645U
Authority
JP
Japan
Prior art keywords
terminal structure
molded transistor
molded
transistor
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2033484U
Other languages
English (en)
Inventor
健治 松田
Original Assignee
株式会社ピ−エフユ−
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ピ−エフユ− filed Critical 株式会社ピ−エフユ−
Priority to JP2033484U priority Critical patent/JPS60133645U/ja
Publication of JPS60133645U publication Critical patent/JPS60133645U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図および第２図は従来例を示す図であり、第１図は
モールド型トランジスタの内部構造を示す斜視図、第２
図ろ第１図のモールド型トランジスタをプリント基板に
搭載した状態を示す斜視図、第３図および第４図は本考
案の１実施例を５ス図であり、第３図はモールド型トラ
ンジスタの内部構造を示す斜視図、第４図は第３図のモ
ールド型トランジスタをプリント基板に搭載した状態を
示す斜視図マある。

Claims (1)

    【実用新案登録請求の範囲】
  1. 平型で複数本の端子を有するモールド型トランジスタに
    おいて、２すくなくとも一本の端子が放熱板面に対して
    立設されたことを特徴とするモールド型トランジスタの
    端子構造。
JP2033484U 1984-02-14 1984-02-14 モ−ルド型トランジスタの端子構造 Pending JPS60133645U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2033484U JPS60133645U (ja) 1984-02-14 1984-02-14 モ−ルド型トランジスタの端子構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2033484U JPS60133645U (ja) 1984-02-14 1984-02-14 モ−ルド型トランジスタの端子構造

Publications (1)

Publication Number Publication Date
JPS60133645U true JPS60133645U (ja) 1985-09-06

Family

ID=30510720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2033484U Pending JPS60133645U (ja) 1984-02-14 1984-02-14 モ−ルド型トランジスタの端子構造

Country Status (1)

Country Link
JP (1) JPS60133645U (ja)

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