JPS60132358A - Complementary mos integrated circuit device - Google Patents
Complementary mos integrated circuit deviceInfo
- Publication number
- JPS60132358A JPS60132358A JP58240303A JP24030383A JPS60132358A JP S60132358 A JPS60132358 A JP S60132358A JP 58240303 A JP58240303 A JP 58240303A JP 24030383 A JP24030383 A JP 24030383A JP S60132358 A JPS60132358 A JP S60132358A
- Authority
- JP
- Japan
- Prior art keywords
- type
- substrate
- well
- epitaxial layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims description 12
- 241000270708 Testudinidae Species 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000003321 amplification Effects 0.000 abstract description 6
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000010354 integration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 241000219094 Vitaceae Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 235000021021 grapes Nutrition 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 （技術分野） 本発明は相補型Ｍ（ＪＳ集積回路装置に関する。[Detailed description of the invention] (Technical field) The present invention relates to a complementary M (JS) integrated circuit device.
（在米技術）
相補型ＭＯ８集積回路装置には、その構造上、ＰＮＰ’
、！：ＮＰＮ の２種の寄生バイポーラトランジスタが
形成さＡ、この二つの寄生ノくイボーラトランジスタに
より寄生サイリスタが構成さ扛、入出力端子に過大な゛
匡正や磁流が印加さ几た時オン状態となバいわゆるラツ
テアッグ現象を生ずるという問題がおる。(U.S.-based technology) Complementary MO8 integrated circuit devices have PNP's due to their structure.
,! : Two types of parasitic bipolar transistors of NPN are formed A, and these two parasitic Ibora transistors constitute a parasitic thyristor, which turns on when an excessive voltage or magnetic current is applied to the input/output terminal. There is a problem in that the so-called Ratteag phenomenon occurs.
第１図は従来の相補型Ｍ（ＪＳ集槓回路装置の一例の−
）Ｔ面図で必る。Figure 1 shows an example of a conventional complementary M (JS integrated circuit device).
) Required for T-view.
Ｎ型半導体基板ｌにＰウェル２忙設け、Ｐウェル内にＮ
型のソース拳ドレイン領域３．４とＰ＋領域５七作り、
ソース・ドレイン明域間の上にゲ−）Ｇτ設けてへチャ
ンネルＦ Ｅ Ｔで作る。基板領域ｖｃＰ型のソース・
ドレイン＝Ａ域６．７とＮ十槌域８とｔ作り、ソース・
ドレイン埃域間にゲートＧτ設けてＰチャンネルＦＥＴ
で作る。この構造において、Ｐウェル２ｉ１’Ｉ：形成
されたＦＥＴのソース３をエミッタ、Ｐウェル２をベー
ス％基板１ｔコレクタとする吾生ＮＰＮ縦型トランジス
タと、基板領域に形成されたＦＥＴのソース６をエミッ
タ、基板１？ベース、Ｐウェル２ｔコレクタとする寄生
ＰＮＰ横型卜２ンジスタが存在する。導電型ｔすべて逆
にすると通導ＩＫｍ、の寄生バイボークトランジスタが
形成される。この２桓の寄生トランジスタとＰウェルの
等測的抵抗Ｒｗｅｌｌ 及びサブストレートの等価的な
抵抗Ｒｓｕｂより寄生ブイリスクが構成される。この寄
生サイリスクは、入出力端子に過大な外米雑音電圧や電
流が印加され間に過大電流が流れてデバイスの破壊める
いは劣化ｋｌｊＡすことが知られている。Two P-wells are provided on an N-type semiconductor substrate l, and an N well is formed in the P-well.
Make source fist drain region 3.4 and P+ region 57 of type,
Gτ is provided above the source-drain bright region, and a channel FET is formed. Substrate area vcP type source
Drain = A area 6.7 and N Jutsuchi area 8 and t made, source
P-channel FET with gate Gτ provided between drain dust region
Make it with In this structure, P well 2i1'I: a vertical NPN transistor with the source 3 of the formed FET as the emitter, the P well 2 as the base and the collector as the substrate 1t, and the source 6 of the FET formed in the substrate region as the emitter. , board 1? There is a parasitic PNP horizontal type transistor with a base and a P well 2t collector. If all the conductivity types t are reversed, a parasitic biboke transistor of conducting IKm is formed. A parasitic builisk is constituted by these two parasitic transistors, the isometric resistance Rwell of the P well, and the equivalent resistance Rsub of the substrate. It is known that this parasitic noise risk occurs when an excessive external noise voltage or current is applied to the input/output terminals, and an excessive current flows between them, resulting in destruction or deterioration of the device.
従来、相補型ＭＯ８集積回路装置において、ラッチアッ
プ現象を防止するため、−ケイリスタを構成するを生縦
１ＮＰＮ）９ンジスタと寄生横型ＰへＰトランジスタの
電流増幅率會下げる手段がとられている。丁なわち寄生
縦型ＮＰＮ）ランジスタＱ１の電流増幅犀τ′下げ／）
ため、第１図に示すように、ベース幅に相当する距離（
１１に大さくと９．寄生横型Ｐ Ｎ Ｐ トランジスタ
の′１流増幅率全下げるため、ベース幅に相当する距離
ｄ２ ｋ大きくとっている。しかしｄ、−ｚ大きくとる
ことば不純物拡散によるウェルの横方向の広が９も大き
くなることを意味し、またｄ２ 葡大きくとることはＮ
チャンネル、Ｐチャンネルの各ＦＥＴ間距離が大きくな
るため高集積化が困難となる。Conventionally, in a complementary MO8 integrated circuit device, in order to prevent the latch-up phenomenon, measures have been taken to reduce the current amplification factor of the P transistor constituting the transistor to a parasitic horizontal P transistor and a vertical P transistor. In other words, the current amplification of the parasitic vertical NPN transistor Q1 is lowered by τ'.
Therefore, as shown in Figure 1, the distance corresponding to the base width (
11 and 9. In order to completely reduce the '1 current amplification factor of the parasitic lateral PNP transistor, a distance d2k corresponding to the base width is set large. However, setting d, -z large means that the lateral spread of the well due to impurity diffusion9 also becomes large, and setting d2 large means that N
Since the distance between the channel and P-channel FETs becomes large, high integration becomes difficult.
第２図は従来の相補１１ＭＯ８集幀回路装置の他の例の
断面図である。FIG. 2 is a sectional view of another example of a conventional complementary 11MO8 integrated circuit device.
との相補型ＭＯＢ集積回路装置では、ラッテアップを防
止する一手段としてＮ型半導体基板１にＰ十埋込層９を
設け、八−皺エビタキシアルＭ１゜を成長せしめ、その
後にＰウェル２をイオン注入や熱拡散等の手段で形成し
埋込層９と接触させるＰウェル形成方法がとられている
。この方法τコ凶用して作成し文相桶型ＭＯ８構造では
、Ｐウェルの抵抗Ｒｗｅｌｌに相当するウェルの等価的
な抵抗を低減させることができ、また寄生縦型ＮＰＮ
ｌ−ランジスタのベース改変を上げることに相当するた
め、電流増幅率も低下し２クチアツプは起シにくくなる
。In a complementary MOB integrated circuit device, a P well 2 is formed by forming an 8-wrinkle epitaxial layer M1° on an N-type semiconductor substrate 1 by forming an 8-wrinkle epitaxial layer M1° as a means of preventing ratt-up. A P-well formation method is used in which the P-well is formed by means such as injection or thermal diffusion and brought into contact with the buried layer 9. In the Bunsooke type MO8 structure created using this method, the equivalent resistance of the well corresponding to the resistance Rwell of the P well can be reduced, and the parasitic vertical NPN
Since this corresponds to increasing the base modification of the L-transistor, the current amplification factor also decreases, making it difficult for double-up to occur.
し〃）シ、この方法では、埋込層形成のだめのフォトワ
ーク工程と不純物導入工程、Ｐウェル形成の定めのフォ
トワーク工程と不純ｇｌＪ４人工程とを要し工程が複雑
になる欠点がある。(ii) This method has the drawback that it requires a photowork process for forming the buried layer, an impurity introduction process, a photowork process for forming the P well, and a 4-person process for impurity GLJ, making the process complicated.
（発明の目的）
不発明の目的は、上記欠点全除去し、製造工程ＦＣｓ−
けるフォトワーク回数７増さず、また集積密度全低下き
せることなく、２ツチアツグ現象の発生を抑えた相補ｍ
Ｍｏ５集積回路装置を提供することにある。(Objective of the invention) The object of the invention is to eliminate all the above defects and improve the manufacturing process FCs-
Complementary m that suppresses the occurrence of the two-shot lag phenomenon without increasing the number of photoworks or reducing the total integration density.
An object of the present invention is to provide an Mo5 integrated circuit device.
（発明の構成）
不発明の相補型ＭＯ８集積回路装置は、−導電型基板と
、該半導体基板の上に設けられ該半導体基板よりも高い
不純？ｌ濃朋を有する一導電型エビタキシアル層と、該
エピタキシアル層内面がらぽエピタキシアル層全通って
前記半導体基板に達゛するように設けられた反対導電型
ウェルと、該つエル内であってかつ前記エピタキシアル
層内に設けられた二つの一導電型領域ｔソース・ドレイ
ンとして構成さ几るｌ−導電型チャンネルのＭＯＳＦＥ
Ｔと、前記ワエル以外の前記エビタキンアル層に設けら
ｎた二つの反対導電型領域ンソース・ドレインとして構
成される反対導電型チャ／ネルのＭＯＳＦＥＴ とｔ含
んで構成烙詐る。(Structure of the Invention) The uninvented complementary MO8 integrated circuit device includes a -conductivity type substrate and an impurity higher than that of the semiconductor substrate provided on the semiconductor substrate. an epitaxial layer of one conductivity type having a conductivity of one conductivity, and a well of an opposite conductivity type provided such that the inner surface of the epitaxial layer reaches the semiconductor substrate through the entirety of the epitaxial layer; and an L-conductivity type channel MOSFE configured as two one-conductivity type regions provided in the epitaxial layer as a T source and a drain.
and a MOSFET of an opposite conductivity type channel configured as a source and a drain, and two opposite conductivity type regions provided in the Evitaquin Al layer other than the above-mentioned wafer.
（冥施例）
次に、不発明の芙施例について図面を用いて説明する７
゜
第３図（ａ）〜（Ｃ）は本発明の一実施例の製造方法を
説明するための工程順に示した断面図である。(Next example) Next, we will explain the non-inventive example using drawings 7
3(a) to 3(C) are sectional views shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
まず、第３図（ａ）Ｋ示すように、Ｎ型半導体１１の上
に基板と同導電温で基板よりも不純物＃度の大きいＮｆ
ｉエビタヤシアル層１２紮成長させる。First, as shown in FIG. 3(a)K, Nf, which has the same conductivity temperature as the substrate and a higher degree of impurity than the substrate, is placed on the N-type semiconductor 11.
i. Grow 12 strands of Evitata palm layer.
エビタキンアル層１２の厚さは後に形成するソース・ド
レイン層の深さより深く、かつＰウェルよシ浅くなるよ
うに設定する。また、エピタキシャル層１２の不純物傭
度は％後で形成するＰウェル形成後の表面濃度全考慮し
て設定する。Ｐ７ｚル形成予定領域以外を酸化膜等のマ
スク層１３で覆い、イオン注入法、拡散等によｆ）Ｐウ
ェル１４を形成する。このとき、Ｐ型不純物の拡散係数
に対してＮ型不純物の拡散係数が十分小さいことが望ま
しい。なお、Ｐウェル１４の不純物濃度は、図に破線で
示したエピタキシアル層１２と、Ｍｉｌｌとの界面を境
界にして不純物濃度が急激に変化している。The thickness of the Evitaquin Al layer 12 is set to be deeper than the depth of the source/drain layer to be formed later and shallower than the P well. Further, the impurity concentration of the epitaxial layer 12 is set by taking into account the total surface concentration after the P well is formed. The area other than the region where the P7z well is to be formed is covered with a mask layer 13 such as an oxide film, and f) a P well 14 is formed by ion implantation, diffusion, or the like. At this time, it is desirable that the diffusion coefficient of the N-type impurity is sufficiently smaller than the diffusion coefficient of the P-type impurity. Note that the impurity concentration of the P well 14 changes rapidly at the interface between the epitaxial layer 12 and the Mill, which is indicated by a broken line in the figure.
次に、第３図（ｂ）に示すように、通常の方法により素
子間分離用のフィールド酸化１１１１５．ゲート酸化膜
１６を形成する。ここで必要に応じて基板全面ｉｃＰ型
不純９ＩＪｆ低エネルギー、吐ト゛−ズ量でイオン注入
し、ＰチャンネルＭＯ８ＦＥＴ金作製する領域のエピタ
キシアル層１２の表面の不純物濃度？下げるとともに、
Ｐウェル領域の表面不純物濃度の最適化ケ行っても良い
。Next, as shown in FIG. 3(b), field oxidation 11115. A gate oxide film 16 is formed. Here, if necessary, ions are implanted all over the substrate with IC P-type impurity 9IJf at low energy and discharged dose to determine the impurity concentration on the surface of the epitaxial layer 12 in the region where P-channel MO8FET gold is to be fabricated. Along with lowering
The surface impurity concentration of the P-well region may be optimized.
次に％第３図（Ｃ）に示すように１通常の方法に従って
ゲート１７．１８Ｎ型ンース・ドレイン４１１９゜２０
Ｐ＋憤域２１．Ｐ型ソース・ドレイン領域２２゜２３、
Ｎ＋領域２４葡形成し、保穫膜形成後窓あけして電極２
５．２６．２７ で形成する。これにより本発明の一実
施例の相補型ＭＯ８集積回路装置が製作される。Next, as shown in Figure 3(C), according to the usual method, the gate 17.18N type drain 4119°20
P+ rage area 21. P-type source/drain regions 22°23,
After forming the N+ region 24 and forming the protective film, a window is opened and electrode 2 is formed.
5.26.27 Formed. In this way, a complementary MO8 integrated circuit device according to an embodiment of the present invention is manufactured.
第４図は第３図（ａ）に示したＰウェル部分の深さ方向
の不純物濃度？示す濃度分布図である。Is the impurity concentration in the depth direction of the P well part shown in FIG. 3(a) shown in FIG. 4? FIG.
第４図において、縦軸は不純物閾度、横軸はエピタキシ
アル層１２の表面からの深さｔ示し、実線２１は不純物
の総和、破線２２＆よＰ型不純物、一点鎖線２３はＮ型
不純物の濃度葡それぞ扛円く丁。In FIG. 4, the vertical axis represents the impurity threshold, the horizontal axis represents the depth t from the surface of the epitaxial layer 12, the solid line 21 represents the total impurity, the broken line 22 represents the P-type impurity, and the dashed line 23 represents the N-type impurity. The concentration of grapes is exactly the same.
ｔｘｋ ｄｅｐｉ はエピタキシアル層１２の浮式ン下
す。txk depi floats down the epitaxial layer 12.
実線２１で示すように、不純物の総オ■濃度は、エピタ
キシアル層１２で低く、エピタキシアル層よ４］ｔｌＶ
−Ｘ基板領域で最大値をとるように形成されている。こ
のような不純物濃度分布にすることによジ、寄生縦型Ｎ
ＰＮ）７ンジスタのベース製置を上げ、従って市原増幅
率τ下げることができると共に、Ｐウェルの等測的な抵
抗７１氏下させ、２ツチアツプ現象の発生荀抑えること
ができる。このことが本発明の車要なポイントである。As shown by the solid line 21, the total O concentration of impurities is low in the epitaxial layer 12, and is lower than the epitaxial layer 4]tlV.
It is formed to have a maximum value in the −X substrate region. By creating such an impurity concentration distribution, the parasitic vertical N
It is possible to increase the base configuration of the PN)7 transistor, thereby lowering the Ichihara amplification factor τ, and also to lower the isometric resistance of the P well by 71 degrees, thereby suppressing the occurrence of the double-up phenomenon. This is the essential point of the present invention.
に丁れば同様に行うことができることは明らかである。It is clear that the same thing can be done if
（発明の効果）
以上詳細に説明したように、本発明によれば、製造工程
にａ−けるフォトワーク回数ｆ増さず、また集積密度を
低下させることなく、ランチアップ現象の発生を抑えた
相補型ＭＯ８集積（ロ）路装置ン得ることができる。(Effects of the Invention) As explained in detail above, according to the present invention, the occurrence of the launch-up phenomenon can be suppressed without increasing the number of photoworks in the manufacturing process or reducing the integration density. A complementary MO8 integrated circuit device can be obtained.
第１図は従来の相補型ＭＯ８集積回路装置の一例の断面
図、第２図は従来の相補型Ｍ Ｏ８集積回路装置の他の
例のり［曲回、第３図（ａ）〜（Ｃ）は不発明の一実施
例の製造方法τ説明するための工程順に示した断凹図、
第４図は第３図（ａ）にボしたＰウェル部分の深さ方向
の不純物濃度分布す濃度分布図である。
ｌ・・・・・・Ｎ型半導体基板、２・・・・・・ＰＬ７
エル、３゜４・・・・・・Ｎｕン−ス・ドレイン領域、
５・・・・・・Ｐ＋領域、６，７・・・・・・Ｐ型ソー
ス・ドレイン領域、８・・・・・・Ｎ十領域、９・・・
・・・Ｐ十埋込層、１０・・・・・・Ｎ−型エビタキン
アルＩ！１，１１・・・−・・Ｎｍ半導体基板％ １２
９．・０．・Ｎ型エピタキシアル層、１３・・・・・・
マスク、１４・・・・・・Ｐウェル、１５・・・・・・
フィールドＷ化膜、ｌ ６・・・・・・ゲート酸化膜、
１７．１８・・・・・・ゲート、１９゜２０・・・・・
・Ｎ型ソース・ドレイン領域、２１・・・・・・Ｐ＋領
域、２２．２３・・・・・・Ｐ′！ｉンースソーレイン
領域、２４・・・・・・へ十領域、２５，２６．２７・
・・・・・１扛極。
」ｉ −
代理人 弁理士 内 原 口、。FIG. 1 is a sectional view of an example of a conventional complementary MO8 integrated circuit device, and FIG. 2 is a cross-sectional view of another example of a conventional complementary MO8 integrated circuit device. is a cutaway diagram showing the order of steps for explaining the manufacturing method τ of an embodiment of the invention,
FIG. 4 is a concentration distribution diagram showing the impurity concentration distribution in the depth direction of the P well portion shown in FIG. 3(a). l...N-type semiconductor substrate, 2...PL7
L, 3゜4... Nuance drain region,
5...P+ region, 6,7...P type source/drain region, 8...N+ region, 9...
...P ten buried layers, 10...N-type Evitaquin Al I! 1,11...--Nm semiconductor substrate% 12
9.・0.・N-type epitaxial layer, 13...
Mask, 14...P well, 15...
Field W oxide film, l 6...Gate oxide film,
17.18...Gate, 19°20...
・N-type source/drain region, 21...P+ region, 22.23...P'! i so rain area, 24...... ten area, 25, 26.27.
...1 stroke. ” i - Agent Patent Attorney Uchiharaguchi.
Claims (1)
半導体基板よりも高い不純物濃度を有する一導電型エビ
タキシアル層と、該エビクキ／アル層表面から該エピタ
キシアル層を通って＠１］記半導体基板に達するように
設けらｆ′Ｌ、た反対導電型ウヱルと、該フェル内であ
ってかつ前記エピタキシアル層内に設けられた二つの一
導電型領域をソース・ドレインとして構成される一導電
型チヤンネルのＭＯＳＦＥＴとｂ ＭｉＪ記ウェル以外
の前記エピタキシアル層に設けられた二つの反対導′亀
型領域全ソース・ドレインとして構成さｎる反対導′屯
型チャ／ネルのＭＯＳＦＥＴとｆｚｃ＠むことτ％徴と
する相補型Ｍ（Ｊ８集積回路装置。a semiconductor substrate of one conductivity type; an epitaxial layer of one conductivity type provided on the semiconductor substrate and having an impurity concentration higher than that of the semiconductor substrate; A well of opposite conductivity type f′L is provided to reach the semiconductor substrate, and a well of one conductivity type provided within the well and within the epitaxial layer is used as a source and drain. MOSFET of conductivity type channel and b MOSFET of opposite conductivity type channel/channel configured with two opposite conductivity tortoise type regions provided in the epitaxial layer other than the MiJ well as all sources and drains and fzc@ Complementary type M (J8 integrated circuit device) with τ% characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58240303A JPS60132358A (en) | 1983-12-20 | 1983-12-20 | Complementary mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58240303A JPS60132358A (en) | 1983-12-20 | 1983-12-20 | Complementary mos integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60132358A true JPS60132358A (en) | 1985-07-15 |
Family
ID=17057449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58240303A Pending JPS60132358A (en) | 1983-12-20 | 1983-12-20 | Complementary mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132358A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0696062A3 (en) * | 1994-07-28 | 1996-12-11 | Hitachi Ltd | CMOS semiconductor device and manufacturing method thereof |
| JP2015023177A (en) * | 2013-07-19 | 2015-02-02 | 富士通セミコンダクター株式会社 | Semiconductor device |
-
1983
- 1983-12-20 JP JP58240303A patent/JPS60132358A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100377649B1 (en) * | 1994-07-25 | 2003-06-02 | 가부시끼가이샤 히다치 세이사꾸쇼 | Method of manufacturing semiconductor wafer, Method of manufacturing semiconductor wafer, Semiconductor integrated circuit device and Semiconductor integrated circuit device |
| EP0696062A3 (en) * | 1994-07-28 | 1996-12-11 | Hitachi Ltd | CMOS semiconductor device and manufacturing method thereof |
| US6368905B1 (en) | 1994-07-28 | 2002-04-09 | Hitachi, Ltd. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
| US6630375B2 (en) | 1994-07-28 | 2003-10-07 | Hitachi, Ltd. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
| US6806130B2 (en) | 1994-07-28 | 2004-10-19 | Renesas Technology Corp. | Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
| JP2015023177A (en) * | 2013-07-19 | 2015-02-02 | 富士通セミコンダクター株式会社 | Semiconductor device |
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