JPS60132017U - Double balanced mixer circuit - Google Patents
Double balanced mixer circuitInfo
- Publication number
- JPS60132017U JPS60132017U JP1998684U JP1998684U JPS60132017U JP S60132017 U JPS60132017 U JP S60132017U JP 1998684 U JP1998684 U JP 1998684U JP 1998684 U JP1998684 U JP 1998684U JP S60132017 U JPS60132017 U JP S60132017U
- Authority
- JP
- Japan
- Prior art keywords
- vertex
- balanced mixer
- mixer circuit
- double balanced
- opposing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のダブル・バランスド・ミクサ回路を示す
回路図、第２図は第１図に示す従来例の動作を説明する
ための等価回路図、第３図は本考案による実施例を示す
回路図、第４図は第３図に示す実施例の動作を説明する
ための等価回路図である。
１．１９・・・受信信号源、２，２０・・・入カドラン
ス、３，２１・・・局部発振部、４〜７，２２〜２５・
・・ダイオード、８． ９． ２６・・・同調用コイル
、１０．１１，２７・・・同調用コンデンサ、１２．２
８・・・バイパス用コンデンサ、１３．２９・・・バイ
アス用抵抗、１４．３０・・・出カドランス、１５〜１
８．３１〜３４・・・直流阻止コンデンサ、３５．３６
・・・中間周波信号。Fig. 1 is a circuit diagram showing a conventional double balanced mixer circuit, Fig. 2 is an equivalent circuit diagram for explaining the operation of the conventional example shown in Fig. 1, and Fig. 3 is an example of an embodiment according to the present invention. The circuit diagram shown in FIG. 4 is an equivalent circuit diagram for explaining the operation of the embodiment shown in FIG. 1.19... Reception signal source, 2, 20... Input cadence, 3, 21... Local oscillation unit, 4-7, 22-25.
...Diode, 8. 9. 26... Tuning coil, 10.11, 27... Tuning capacitor, 12.2
8... Bypass capacitor, 13.29... Bias resistor, 14.30... Output transformer, 15-1
8.31-34...DC blocking capacitor, 35.36
...Intermediate frequency signal.
Claims (1)
１の頂点から受信信号および局部発振信号を印加し、こ
れにより生成する周波数変換された中間周波信号を他方
の対向する第２の頂点から取り出すと共に、該第２の頂
点に互に磁界を打ち消す方向に密結合させたコイルとコ
ンデンサとから成る該中間周波信号に同調した並列共振
回路を接続したことを特徴とするダブル・バランスドパ
ミクサ回路。Diodes are connected in a bridge configuration, a received signal and a local oscillation signal are applied from one opposing first vertex, and the resulting frequency-converted intermediate frequency signal is extracted from the other opposing second vertex. , a double balanced mixer circuit characterized in that a parallel resonant circuit tuned to the intermediate frequency signal, which is composed of a coil and a capacitor tightly coupled in a direction that cancels out magnetic fields, is connected to the second vertex.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1998684U JPS60132017U (en) | 1984-02-15 | 1984-02-15 | Double balanced mixer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1998684U JPS60132017U (en) | 1984-02-15 | 1984-02-15 | Double balanced mixer circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60132017U true JPS60132017U (en) | 1985-09-04 |
| JPH0212736Y2 JPH0212736Y2 (en) | 1990-04-10 |
Family
ID=30510060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1998684U Granted JPS60132017U (en) | 1984-02-15 | 1984-02-15 | Double balanced mixer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132017U (en) |
-
1984
- 1984-02-15 JP JP1998684U patent/JPS60132017U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0212736Y2 (en) | 1990-04-10 |
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