JPS60130920A - Semiconductor integrated logical circuit - Google Patents
Semiconductor integrated logical circuitInfo
- Publication number
- JPS60130920A JPS60130920A JP24031483A JP24031483A JPS60130920A JP S60130920 A JPS60130920 A JP S60130920A JP 24031483 A JP24031483 A JP 24031483A JP 24031483 A JP24031483 A JP 24031483A JP S60130920 A JPS60130920 A JP S60130920A
- Authority
- JP
- Japan
- Prior art keywords
- capacitors
- output
- circuit
- capacitor
- semiconductor integrated
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
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Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は半導体集積論理回路に関し、特に同時に動作す
る複数の出力回路を有する半導体集積論理回路に関する
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated logic circuit, and more particularly to a semiconductor integrated logic circuit having a plurality of output circuits that operate simultaneously.
（従来技術）
一般に、集積回路の出力段にはバス線路等の重い負荷を
駆動するためにバッファ回路が設置されるが、近年、集
積回路の設計、製造技術の進歩に伴ない１チツプに搭載
される論理回路は飛躍的に大規模化しており、出力バッ
ファ回路の数も必然的に増加する傾向にある。しかるに
、多ビットの出力バッファ部２有する大規模集積論理回
路ではこれらのバッファは論理信号又は制御信号によっ
て同時に動作する頻度が高く、負荷容量の充放電時にデ
バイスに対して流入、流出する過渡電流が増大するとい
う問題を生ずる。(Prior art) Generally, a buffer circuit is installed in the output stage of an integrated circuit to drive a heavy load such as a bus line, but in recent years, with advances in integrated circuit design and manufacturing technology, a buffer circuit has been installed on a single chip. The scale of the logic circuits used is increasing dramatically, and the number of output buffer circuits is also inevitably increasing. However, in a large-scale integrated logic circuit having a multi-bit output buffer section 2, these buffers are frequently operated simultaneously by logic signals or control signals, and transient currents flowing into and out of the device when charging and discharging the load capacitance are This results in the problem of increased growth.
第１図は従来の出力バッファの一例の回路図である。FIG. 1 is a circuit diagram of an example of a conventional output buffer.
この回路において、制御信号ａは、はぼ同じ遅延時間を
有するインバータＡ１〜Ａｎを介してほぼ同時に３−ス
テート出力バッファＢ１〜Ｂｎに伝達される。このため
３ステート出力バッファＢ、〜Ｂｎは同時に動作を開始
し、外部負荷としてそれぞれの出力につながる容量Ｃ８
〜Ｃｎの充電又は放電のため過渡電流ｉ１〜ｉｎが各出
力バッ７アの電源線路を通過する。例えば、３ステート
出カバ。In this circuit, control signal a is transmitted almost simultaneously to three-state output buffers B1-Bn via inverters A1-An having approximately the same delay time. Therefore, the 3-state output buffers B and ~Bn start operating at the same time, and the capacitor C8 connected to each output as an external load
For charging or discharging ~Cn, a transient current i1~in passes through the power supply line of each output buffer 7. For example, 3-state output cover.
ファＢ１〜Ｂｎは、“制御信号ＣＴ１〜ＣＴｎが高レベ
ルで出力アクティブとすると、データ信号ｂ８〜ｂｎが
低レベルの場合、制御信号ａが高レベルか低レベルに変
動するとき、出カバソファの出力部０、〜０ｎｌｄはば
同時に高インピーダンス状態から低インピーダンス状態
に変化する。この時、抵抗Ｒ８〜Ｒｎの一端が電源Ｖｃ
ｃに接続されていると想定すると、各容量は動作前にＶ
ｅｃレベルまでチャージアップされており、この容量か
らの放１１！電流を主とする過渡電流ｉ、〜ｉｎが一挙
に接地線路のｇ部に流れ込む。 ゛
を哄扇違電直はチップ内の抵抗Ｒ２，、ボンデインク線
及びケースのリードのインダクタンスＬｇ□を部接地端
子ＧＮＤに対して過渡的に上昇しチップ上の他の回路の
雑音余裕を著しく減少させる。また、外部負荷容量が大
きくかつ動作周波数が高い場合、出力部Ｏ１〜０ｎの平
均的々電流密度が増大し、この部分の信頼性を保証する
ために配置１！幅を大きくする等の対策が必要となる。The outputs of the output buffer sofas B1 to Bn are as follows: "If the control signals CT1 to CTn are at high level and the output is active, when the data signals b8 to bn are at low level, and when the control signal a changes to high or low level, the output of the output Parts 0 and 0nld simultaneously change from a high impedance state to a low impedance state.At this time, one end of the resistors R8 to Rn is connected to the power supply Vc.
c, each capacitor is connected to V before operation.
It is charged up to EC level, and the release from this capacity is 11! Transient currents i, .about.in, which are mainly currents, flow into the g section of the ground line all at once.゛When the fan is disconnected, the resistance R2 inside the chip, the inductance Lg of the bond wire and the case lead rise transiently with respect to the ground terminal GND, and the noise margin of other circuits on the chip is significantly reduced. let Further, when the external load capacity is large and the operating frequency is high, the average current density of the output parts O1 to 0n increases, and in order to guarantee the reliability of this part, the arrangement 1! Measures such as increasing the width are required.
炉に、データ信号す、〜ｂｎが高レベルで、制御信号ａ
が高レベルの時、出力部０１〜ｏｎは高インピーダンス
と欧るが、この時抵抗も〜Ｒｎの一端が接地ねに接続さ
れた状態を想定すると、出力部０、〜０ｎのレベルは接
地レベルにある。この状態から制御信号ａを高レベルか
ら低レベルに変化させると出力バッファＢ、〜Ｂｎは同
時にアクティブ状態への動作を一如し、出力部０．〜０
ｎを介して充電電流が流れる。この充１！電流はチップ
内の共通Ｖｃ、ｃ線路を流れるが、これの電り、は晶の
ことながらチップ内配線の抵抗へ、□、ボンディング線
及びケースのリードのインダクタンスＬｕ、を介して供
給されるため、Ｕ部の〜１位は過渡的に降下し本チップ
の他の回路部の雑音余裕を著しく減少させる。又、容量
Ｃ０〜Ｃｎが大きく、出力バッファＢ、〜Ｂｎの動作周
波数が高い場合、出力部０．〜０ｎの平均電流密度が増
大するため信頼性を確保するのにこの部分の配線幅を大
きめに設計する等の対策が必要となる。In the furnace, the data signals S,~bn are at high level and the control signal a
When is at a high level, output parts 01~on are considered to have high impedance, but at this time, assuming that one end of the resistor ~Rn is connected to the ground, the level of output parts 0 and ~0n is the ground level. It is in. When the control signal a is changed from a high level to a low level from this state, the output buffers B, -Bn simultaneously operate to the active state, and the output sections 0. ~0
A charging current flows through n. This full 1! Current flows through the common Vc and c lines within the chip, but this electricity is supplied to the resistance of the internal wiring of the chip via □, the inductance Lu of the bonding wire and the case lead. , the ~1st position of the U section drops transiently, significantly reducing the noise margin of other circuit sections of this chip. Further, when the capacitances C0 to Cn are large and the operating frequencies of the output buffers B and -Bn are high, the output section 0. Since the average current density of ~0n increases, it is necessary to take measures such as designing the wiring width in this portion to be larger in order to ensure reliability.
第２図は第１図の回路の同時動作時に流れる過渡電流の
波形図である。FIG. 2 is a waveform diagram of a transient current flowing during simultaneous operation of the circuit of FIG. 1.
第２図は過渡電流ｉ、〜１．及びｉ、１．ｉ、□の過渡
変動分を時間を横軸として表わしたものである。FIG. 2 shows the transient current i, ~1. and i, 1. The transient fluctuations of i and □ are expressed with time as the horizontal axis.
ｉｇ□及び’ｕｓ ｔ；ｊそれぞれｉ、〜ｉｎの変動分
の和となり極めて太き力過波変化を示す。ここで、外部
接地線路のｇ部の電位変動分ΔＵｇＶｉで表わされるも
ので１ ｇ １の変動が急激であればあるはとｇ部の変
動が大きくなることが理解さり、よう。同時にＵ部の電
位変動分ΔＵｕも
で表わされる。ig□ and 'us t;j are the sum of the fluctuations of i and ~in, respectively, and show extremely thick force overwave changes. Here, it is understood that the potential fluctuation of the g section of the external grounding line is represented by ΔUgVi, and if the fluctuation of 1 g 1 is rapid, the fluctuation of the g section becomes large. At the same time, the potential variation ΔUu of the U portion is also expressed as ΔUu.
以上説明したように、複数の出カバソファを同時に動作
させる同時動作出力バッファ回路を含む従来の半導体集
積論理回路においては、半導体チ、ブ上の電源配線の抵
抗やボンデインク線を含む電源線路のインダクタンスに
起因する過渡的な電位変動が増大し、雑音余裕度を著し
く低下させるという欠点があり、また、この過渡的な大
電流によって半導体チップ内配線の電流密度が増大し、
デバイスの寿命に係わる信頼度を低下させるという欠点
ｌがあった。As explained above, in conventional semiconductor integrated logic circuits that include a simultaneous output buffer circuit that operates multiple output buffers simultaneously, the resistance of the power supply wiring on the semiconductor chip and the inductance of the power supply line including the bonded ink line This has the disadvantage that the resulting transient potential fluctuations increase, significantly reducing the noise margin, and this transient large current increases the current density of the wiring within the semiconductor chip.
There is a drawback that reliability regarding the life of the device is reduced.
（発明の目的）
本発明の目的は、上記欠点を除去し、同時動作時に電源
線路を流れる過渡電流を制御し、雑音余裕度の低下と信
頼性の低下とを防いだ半導体集積論理回路を提供するこ
とにある。(Object of the Invention) An object of the present invention is to provide a semiconductor integrated logic circuit which eliminates the above drawbacks, controls the transient current flowing through the power supply line during simultaneous operation, and prevents a reduction in noise margin and reliability. It's about doing.
（発明の構成）
本発明の半導体集積論理回路は、同一の入力信号を入力
する複数個の論理ゲートと、前記複数個の論理ゲートの
うちの２個以上の論理ゲートの出力端にそれぞれ１個あ
て接続される容量体であってかつ該２個以上の容量体の
うち少くとも１個は残りの他の容量体とは異なる容量値
を有している複数個の容量体とを含んで構成される。(Structure of the Invention) The semiconductor integrated logic circuit of the present invention includes a plurality of logic gates to which the same input signal is input, and one logic gate at each output end of two or more logic gates among the plurality of logic gates. a plurality of capacitors to be connected in parallel and at least one of the two or more capacitors has a capacitance value different from that of the remaining capacitors; be done.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第３図は本発明の一実施例と該−実施例に接続した出力
バッファの回路図である。FIG. 3 is a circuit diagram of an embodiment of the present invention and an output buffer connected to the embodiment.
この実施例は、同一の入力信号ｄを入力する複数個の論
理ゲ−）Ａ、ｌ−Ａ、、と、これらの複数個の論理ゲー
トのうちの２個以上の論理ゲートの出力端にそれぞれ１
個あて接続される容量体であってかつ２個以上の容量体
のうち少くとも１個は残りの他の容量体とは異なる容量
値を有している複数個の容量体Ｄ１〜Ｄｎとを含んで構
成される。In this embodiment, a plurality of logic gates (A, 1A, . 1
A plurality of capacitors D1 to Dn are individually connected and at least one of the two or more capacitors has a capacitance value different from that of the remaining capacitors. It consists of:
即ち、容量体り、〜Ｄｎのうち少くとも一つは他の容量
体と容量値が異っている。このことが重要である。That is, at least one of the capacitors ~Dn has a capacitance value different from that of the other capacitors. This is important.
この実施例の使用例を示すために、第３図においては、
論理ゲートＡ、１〜Ａ、ｎの出力端に出カバ、ファＢ、
１〜Ｂｐｎを接続した。To illustrate the use of this embodiment, in FIG.
Output terminals of logic gates A, 1 to A, n, F, B,
1 to Bpn were connected.
第４図は第３図に示す容量体の一構成例を示す結線図で
ある。FIG. 4 is a wiring diagram showing an example of the structure of the capacitor shown in FIG. 3.
第４図は第３図に示す容量体り、〜Ｄｎのうちのｉ番目
の容量体ＤＩの一例を示したものである。FIG. 4 shows an example of the i-th capacitor DI of the capacitors ~Dn shown in FIG.
トランジスタＴ１〜Ｔｊはエミッタとコレクタとが短絡
されてダイオードを形成している。従って、トランジス
タＴ、〜Ｔｊをダイオードで置かれても良いし、逆にダ
イオードをトランジスタで置換えても良い。ダイオード
またはエミッタ・プレフタ短絡トランジスタの数を変え
ることにより容量体ＤＪの容量を変えることができる。The emitters and collectors of the transistors T1 to Tj are short-circuited to form diodes. Therefore, the transistors T, -Tj may be replaced with diodes, or conversely, the diodes may be replaced with transistors. The capacitance of the capacitor DJ can be changed by changing the number of diodes or emitter-prefter shorting transistors.
この例は、マスタースライス方式で論理回路を構成する
ときに余っているダイオードやトランジスタを利用する
ことで容量体を作ることができることを示したものであ
るが、コンデンサを新しく作って容量体としても良いこ
とはもちろんである。This example shows that it is possible to create a capacitor by using leftover diodes and transistors when configuring a logic circuit using the master slice method, but it is also possible to create a capacitor by creating a new capacitor. Of course it's a good thing.
次に、第３図に示す実施例の動作について説明する。Next, the operation of the embodiment shown in FIG. 3 will be explained.
制御信号ｄの入力によって、論理グー）Ａｐｒｓ人、２
．・・・・・・Ａ、ｎは同時に動作を開始する。論理ゲ
−） Ａ、１．Ａ卯、・・・・・・Ａ、ｎの出力端には
容量体へ。By inputting the control signal d, the logic group) Aprs person, 2
．． ...A and n start operating at the same time. Logic game) A, 1. A,...The output terminals of A and n are connected to a capacitor.
Ｄ、・・・・・・Ｄｎが接続されているから、出力バッ
ファＢｐ□ｔＢｐ２ｙ・・・・・・Ｂｐｎに入力される
論理ゲートＡ、□。Since D,...Dn are connected, the logic gates A,□ are input to the output buffers Bp□tBp2y...Bpn.
Ａｐ ２ ＠・・・・・・大ｐｍの出力は容量体り、、
Ｄ、”＝Ｄｎの容量値に応じた遅れを生じる。そのた
め、出カバ、ファＢ、、、Ｂｐ□、・・・・・・Ｂ、ｎ
の同時動作を回避することができる。Ap 2 @...The output of large pm is the capacitance.
A delay occurs depending on the capacitance value of D,"=Dn. Therefore, the output, F, B,..., Bp□,...B,n
simultaneous operations can be avoided.
例えば、容量体り、、Ｄ、、・・・・・・Ｄｎの各容量
値をｘ、、ｘ、、・・・・・・ｘｎとして、この間にｘ
ｔ＜ｘｔ ＜・・・・・・〈ｘｎの関係があるとすれば
、出カバソファの動作タイミングはＢ、□Ｉ Ｂｐ２
ｅ ”” ”” ＢｐＨの順番になり過渡電流ｉｐ１ｇ
’ｐｕ＞・・・・・・ｌｐｎの同時重畳の機会が回避
され＊ ’ｇ２ｅ ’ｕ２のピーク値は従来回路のそれ
に比してはるかに小さく抑えられる。今、容量体り、、
Ｄ、、・・・・・・Ｄｎの容量値と論理ゲートＡｐ ２
、 Ａｐ、、・・・・・・Ａｐｎの出力インピーダン
スとで決まる各信号ｌ、から１ｎの信号１１に対する動
作タイミングの差分をｔ’ｓ ｔｔｓ・・・・・・とす
るとｉｐｌ。For example, if each capacitance value of the capacitance bodies, , D, , . . . Dn is x, , x, , . . .
If there is a relationship of t<xt<...<xn, the operation timing of the output sofa is B, □I Bp2
e ”” ”” BpH order and transient current ip1g
The chance of simultaneous superposition of 'pu>...lpn is avoided, and the peak value of *'g2e'u2 is suppressed to be much smaller than that of the conventional circuit. Now, the capacity is increasing...
D, ...... Capacitance value of Dn and logic gate Ap 2
, Ap, . . . If the difference in the operation timing for the signal 11 from each signal 1 to 1n determined by the output impedance of Apn is t's tts . . . ipl.
Ｉｐ□、・・・・・・１ｐ１１と４□、ｉｕ、は横軸を
時刻として第５図の様に表わされる。Ip□, . . . 1p11 and 4□, iu are expressed as shown in FIG. 5, with the horizontal axis representing time.
ここで、第２図と第５図を比較すれば、チップの共通電
源線を流れる過渡電流の、特に時間に関する微分値が顕
著に異匁ることが理解されよう。If FIG. 2 is compared with FIG. 5, it will be understood that the transient current flowing through the common power supply line of the chip, especially the differential value with respect to time, is significantly different.
このことは電源線路のインダクタンス及び抵抗弁による
電位変動分が、本発明の回路では、従来方式よりはるか
に小さく抑えられることを意味しており本発明の有効性
を示すものである。又、本発明の回路ではすでに解るよ
うに過渡電流のピーク値が低く抑えられるため、配線の
寿命に関わる信頼性も向上する。This means that in the circuit of the present invention, potential fluctuations due to the inductance of the power supply line and the resistance valve can be suppressed to a much smaller value than in the conventional system, which shows the effectiveness of the present invention. Furthermore, as already understood, in the circuit of the present invention, since the peak value of the transient current can be suppressed to a low level, the reliability regarding the life of the wiring is also improved.
上記芙施例は、論理ゲートの次段の回路として出力バッ
ファを接続しであるが、出力バッファに限定されず他の
回路であっても良い。In the above embodiment, an output buffer is connected as the circuit next to the logic gate, but the circuit is not limited to the output buffer and may be any other circuit.
（発明の効果）
以上詳細に説明したように、本発明は、同時動作する論
理ゲートの出力端に容量体を接続することにより次段の
回路の入力タイミングを異ならしめ、次段の回路の同時
出力を回避させることにより電源線路を流れる過渡電流
を制御し、雑音余裕度の低下と信頼性の低下とを防いだ
牛導体集積論理回路が得られるという効果を有する。(Effects of the Invention) As explained in detail above, the present invention connects a capacitor to the output terminals of logic gates that operate simultaneously, thereby making the input timing of the next stage circuit different, and simultaneously operating the logic gates of the next stage. By avoiding the output, it is possible to control the transient current flowing through the power supply line, and to obtain a conductor integrated logic circuit which prevents a reduction in noise margin and reliability.
第１図は従来の出カバ、ファの一例の回路図、第２図は
第１図の回路の同時動作時に流れる過渡電流の波形図、
第３図は本発明の一実施例と該−実施一例に接続した出
−カバラン７の回路図、第４図は第３図に示す容量体の
一構成例を示す結線図、第５図は第３図ｔこ示す回路に
流れる過渡電流の波形図である。
ａ・・・・・・制御信号、Ａ、〜Ａｎ・・・・・・イン
バータ、Ａｐ１〜Ａｐｎ・・・・・・論理ゲ−）、ｂｌ
〜ｂｎ ・・・・・・データ信号、Ｂ、〜Ｂｎ、Ｂ、、
〜Ｂｐｎ・・・・・・出力バッファ、Ｃ１〜Ｃｎ・・・
・・・容量、ＣＴ、〜ＣＴｎ・・・・・・制御信号、ｄ
・・・・・・制御信号、Ｄ・・・・・・ダイオード、Ｄ
ｌＤｎ・・・・・・容量体、１１〜ｉ ｎ＠ ｓ ｐ
１〜し。・・・・・・過渡電流、！１〜Ｉｎ００１＋＋
信号ｓ Ｌｇｌ ＃ Ｌｇ２ ｔ Ｌｕｌ ＃”ｕ２
”’ ”°インダクタンス、０．〜０ｎ・・・・・・出
力部、ＲＩ−Ｒｎ、Ｒｇユ。
Ｒｇ□、へ、□、Ｒ１ｕ２・・・・・・抵抗、Ｔ、〜Ｔ
ｊ・・・・・・トランジスタ。
乃ｆ閏
も？国Fig. 1 is a circuit diagram of an example of a conventional output cover, and Fig. 2 is a waveform diagram of a transient current flowing when the circuit of Fig. 1 is operated simultaneously.
FIG. 3 is a circuit diagram of an embodiment of the present invention and an output coverlan 7 connected to the embodiment, FIG. 4 is a wiring diagram showing an example of the configuration of the capacitor shown in FIG. 3, and FIG. FIG. 3 is a waveform diagram of a transient current flowing through the circuit shown in FIG. a...Control signal, A, ~An...Inverter, Ap1~Apn...Logic game), bl
~bn...Data signal, B, ~Bn, B,...
~Bpn...Output buffer, C1~Cn...
...Capacitance, CT, ~CTn...Control signal, d
...Control signal, D...Diode, D
IDn...Capacitor, 11~in@sp
1~shi. ...Transient current! 1~In001++
Signal s Lgl # Lg2 t Lul #”u2
”' ”°Inductance, 0. ~0n...Output section, RI-Rn, Rgyu. Rg□, to, □, R1u2...Resistance, T, ~T
j...Transistor. Nori also? Country
Claims (1)
複数個の論理ゲートのうちの２個以上の論理ゲートの出
力端にそれぞれ１個あて接続される容量体であってかつ
該２個以上の容量体のうち少くとも１個は残りの他の容
量体とは異外る容量値を有している複数個の容量体とを
含むことを特徴とする半導体集積論理ゲート回路。A plurality of logic gates that input the same input signal, and one capacitor connected to each of the output terminals of two or more logic gates among the plurality of logic gates, and the two or more capacitors A semiconductor integrated logic gate circuit comprising a plurality of capacitors, at least one of which has a capacitance value different from that of the remaining capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24031483A JPS60130920A (en) | 1983-12-20 | 1983-12-20 | Semiconductor integrated logical circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24031483A JPS60130920A (en) | 1983-12-20 | 1983-12-20 | Semiconductor integrated logical circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60130920A true JPS60130920A (en) | 1985-07-12 |
Family
ID=17057616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24031483A Pending JPS60130920A (en) | 1983-12-20 | 1983-12-20 | Semiconductor integrated logical circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60130920A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857765A (en) * | 1987-11-17 | 1989-08-15 | International Business Machines Corporation | Noise control in an integrated circuit chip |
| US5194764A (en) * | 1989-12-14 | 1993-03-16 | Kabushiki Kaisha Toshiba | Data output buffer circuit for semiconductor integrated circuit having output buffers with different delays |
| US5285117A (en) * | 1991-10-09 | 1994-02-08 | Mitsubishi Denki Kabushiki Kaisha | Output circuit with output enabling inputs |
| US5378950A (en) * | 1992-02-03 | 1995-01-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit for producing activation signals at different cycle times |
| US5974259A (en) * | 1996-09-18 | 1999-10-26 | International Business Machines Corporation | Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels |
-
1983
- 1983-12-20 JP JP24031483A patent/JPS60130920A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857765A (en) * | 1987-11-17 | 1989-08-15 | International Business Machines Corporation | Noise control in an integrated circuit chip |
| US5194764A (en) * | 1989-12-14 | 1993-03-16 | Kabushiki Kaisha Toshiba | Data output buffer circuit for semiconductor integrated circuit having output buffers with different delays |
| US5285117A (en) * | 1991-10-09 | 1994-02-08 | Mitsubishi Denki Kabushiki Kaisha | Output circuit with output enabling inputs |
| US5378950A (en) * | 1992-02-03 | 1995-01-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit for producing activation signals at different cycle times |
| US5974259A (en) * | 1996-09-18 | 1999-10-26 | International Business Machines Corporation | Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels |
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