JPS60120591A - Method of forming ultrafine copper conductor - Google Patents

Method of forming ultrafine copper conductor

Info

Publication number
JPS60120591A
JPS60120591A JP22844483A JP22844483A JPS60120591A JP S60120591 A JPS60120591 A JP S60120591A JP 22844483 A JP22844483 A JP 22844483A JP 22844483 A JP22844483 A JP 22844483A JP S60120591 A JPS60120591 A JP S60120591A
Authority
JP
Japan
Prior art keywords
copper
copper conductor
plating
pattern
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22844483A
Other languages
Japanese (ja)
Inventor
鈴木 芳博
和嶋 元世
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22844483A priority Critical patent/JPS60120591A/en
Publication of JPS60120591A publication Critical patent/JPS60120591A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はスルーホールを有する絶縁基板上に銅導体配線
を形成する方法に係り、特に微細な銅導体配線を精度よ
く形成するのに好適なパターン化学めっき法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of forming copper conductor wiring on an insulating substrate having through holes, and particularly a pattern suitable for forming fine copper conductor wiring with high precision. Regarding chemical plating methods.

〔発明の背景〕[Background of the invention]

従来はプリント基板上への半導体の実装密度が低く、そ
のためプリント基板上の銅導体配線パターンもそれほど
微細なものは要求されておらず。
Conventionally, the packaging density of semiconductors on printed circuit boards has been low, and therefore the copper conductor wiring patterns on printed circuit boards have not been required to be very fine.

スルーホールの孔径も比較的大きなものであった。The diameter of the through hole was also relatively large.

しかし、年々半導体の実装密度の高いものが要求される
ようになってきており、それに伴ない、上記した銅導体
パターンおよびスルーホール径ト異なり、銅導体パター
ンに関しては微細化が、またスルーホール径については
孔径の小さいものがめられるようになってきた。しかし
、現在用いられているフォトエツチング法によるパター
ン形成法では微細パターンを精度よく形成することは不
可能である。
However, as the demand for semiconductors with higher packaging density increases year by year, copper conductor patterns and through-hole diameters are becoming smaller and smaller. For this purpose, smaller pore diameters are becoming popular. However, it is impossible to form fine patterns with high precision using the currently used pattern forming method using photoetching.

〔発明の目的〕[Purpose of the invention]

本発明の目的は高精度の微細パターンを有する絶縁基板
を提供することにある。
An object of the present invention is to provide an insulating substrate having a highly accurate fine pattern.

〔発明の概要〕[Summary of the invention]

スルーホ−ルを有する絶縁板上にドライフィルムを用い
て・化学めっきにより微細な銅導体配線を形成しようと
する場合、1つの方法として(イ)フルアディティブ法
が考えられる。しかし、この方式は(1)ドライフィル
ムによるめっき液の劣化、(2)ドライフィルムを厚お
することにより、レジストのパターン精度が低下すると
いう問題がある。このためめっき液汚染の恐れのない・
いわゆる(口)全面化学めっき法、すなわちスルーホー
ルを含めて。
When attempting to form fine copper conductor wiring by chemical plating using a dry film on an insulating plate having through holes, (a) full additive method can be considered as one method. However, this method has problems in that (1) the plating solution deteriorates due to the dry film, and (2) the pattern accuracy of the resist decreases due to the thick dry film. Therefore, there is no risk of plating solution contamination.
This is the so-called full surface chemical plating method, including through-holes.

基板全面に化学めっきを厚づけし、その後フォトエツチ
ングにより微細パターンを形成する方法が考えられる。
One possible method is to apply thick chemical plating to the entire surface of the substrate and then form a fine pattern by photoetching.

しかし、この方法では銅導体が厚く、かつ導体パターン
が微細になると、エツチング時のアンダーカットによる
問題を無視することができなくなり、しかも化学めっき
を全面に厚くめっきすると、もともと絶縁板に対するめ
っき膜の密着性が不十分なために、めっき膜にふくれが
生じ、めっき膜が下地からはく離するといった問題が生
ずる。
However, with this method, if the copper conductor is thick and the conductor pattern becomes fine, it becomes impossible to ignore the problem of undercutting during etching.Moreover, if the entire surface is coated with a thick chemical plating, the plating film on the insulating board may Insufficient adhesion causes problems such as blistering of the plating film and peeling of the plating film from the base.

本発明ではこれらの問題を解消するためK・1)ドライ
フィルムとしては膜厚いものを使用することにより・レ
ジストのパターン精度を高くし・2)アディティブ法と
フォトエツチング法とを併用するに至った。すなわち、
触媒を付与した絶縁基板上にドライフィルムによりレジ
ストパターンを形成し、その後回路上に化学銅めっきに
より・スルーl一層および銅箔上に・エツチング(D際
、77ダーカツトによる影響をほとんど無視できる程度
の厚さにまで化学めっきする。次に、フォトエツチング
により精度の高い銅導体パターン金形成した後、レジス
トフィルムを除去後、化学めっきにより厚づけし、所望
の超高精細導体パターン全形成する。なお、絶縁膜に対
する化学銅めっき膜導体の密着性は十分であるとは言え
ないが・プリプレグを用いて多層化接着することにより
、化学銅めっき膜導体は絶縁板およびプリプレグに対し
て固定されるようになるため、絶縁膜およびプリプレグ
に対して、化学銅めっき膜がはがれるといった問題は心
配ない。
In the present invention, in order to solve these problems, we have: 1) used a thick dry film to increase the precision of the resist pattern; and 2) combined use of an additive method and a photoetching method. . That is,
A resist pattern is formed using a dry film on an insulating substrate to which a catalyst has been applied, and then chemical copper plating is applied to the circuit by chemical copper plating and etching on the copper foil. Chemical plating is applied to the desired thickness.Next, a highly accurate copper conductor pattern is formed by photoetching, the resist film is removed, and the thickness is increased by chemical plating to form the entire desired ultra-high definition conductor pattern. However, the adhesion of the chemical copper-plated film conductor to the insulating film cannot be said to be sufficient. By using prepreg to bond the chemical copper-plated film conductor in multiple layers, the chemical copper-plated film conductor can be fixed to the insulating board and the prepreg. Therefore, there is no need to worry about the problem of the chemical copper plating film peeling off from the insulating film and prepreg.

〔発明の実施例〕[Embodiments of the invention]

実施例1 ガラス−エポキシ系のスルーホールを設けた絶縁基板上
に化学めっきにより5μmの厚さに全面めっきする。次
に、膜厚18μmのドライフィルムにより、レジストパ
ターンを形成する。次に、エツチングにより不要部の銅
を溶解除去する。その後・塩化メチレンによりレジスト
を溶解除去し。
Example 1 An insulating substrate provided with glass-epoxy through holes is entirely plated to a thickness of 5 μm by chemical plating. Next, a resist pattern is formed using a dry film having a thickness of 18 μm. Next, unnecessary copper is dissolved and removed by etching. Afterwards, dissolve and remove the resist using methylene chloride.

回路部上に残った銅導体上に化学銅めっきにより35μ
m厚づけする。鷺の結果、絶縁基板上に銅導体パターン
として、導体幅/導体間隔が50μm、159μmのも
のを精度よく形成できた。
35μ chemical copper plating on the copper conductor remaining on the circuit part
Make it thicker by m. As a result, a copper conductor pattern with conductor width/conductor spacing of 50 μm and 159 μm could be formed with high accuracy on an insulating substrate.

比較例1 スルーホールを形成したガラスエポキシ系の絶縁板上に
化学めっきにより、スルーホール内および基板平面部に
銅を40μmめっきする。その後、膜厚18μIT+の
ドライフィルムを用いて・レジストパターンを形成し、
フォトエツチングにより・回路上に銅の導体を形成する
。その結果、フォトエツチングの際の銅のアンダーカッ
トがはげしく・絶縁基板上の銅導体パターンとしては1
25μm/125μmよりも微細なパターンを形成する
ことが困難であった。
Comparative Example 1 On a glass epoxy insulating plate in which through holes were formed, copper was plated to a thickness of 40 μm inside the through holes and on the flat surface of the substrate by chemical plating. After that, a resist pattern was formed using a dry film with a film thickness of 18μIT+,
- Form copper conductors on the circuit by photo-etching. As a result, the copper undercut during photoetching is severe, and the copper conductor pattern on the insulating substrate is
It was difficult to form a pattern finer than 25 μm/125 μm.

〔発明の効果〕〔Effect of the invention〕

本発明によれば絶縁基板上にパターン精度にすぐれた微
細銅導体を形成できる。
According to the present invention, a fine copper conductor with excellent pattern accuracy can be formed on an insulating substrate.

代理人 弁理士 高橋明夫Agent: Patent Attorney Akio Takahashi

Claims (1)

【特許請求の範囲】[Claims] 1、絶縁基板にスルーホールを形成し、ついで基板全面
に化学めっきにより銅を薄づけし、次にフォトエツチン
グにより、銅導体回路を形成し、レジストを除去した後
、化学めっきにより、銅を厚づけし、銅導体パターンを
形成することを特徴とする微細銅導体の形成法。
1. Form a through hole in the insulating substrate, then thin the copper on the entire surface of the board by chemical plating, then form a copper conductor circuit by photoetching, remove the resist, and thin the copper by chemical plating. 1. A method for forming a fine copper conductor, characterized by forming a copper conductor pattern.
JP22844483A 1983-12-05 1983-12-05 Method of forming ultrafine copper conductor Pending JPS60120591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22844483A JPS60120591A (en) 1983-12-05 1983-12-05 Method of forming ultrafine copper conductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22844483A JPS60120591A (en) 1983-12-05 1983-12-05 Method of forming ultrafine copper conductor

Publications (1)

Publication Number Publication Date
JPS60120591A true JPS60120591A (en) 1985-06-28

Family

ID=16876587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22844483A Pending JPS60120591A (en) 1983-12-05 1983-12-05 Method of forming ultrafine copper conductor

Country Status (1)

Country Link
JP (1) JPS60120591A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500472A (en) * 1986-08-06 1989-02-16 マクダーミッド,インコーポレーテッド Printed circuit board manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01500472A (en) * 1986-08-06 1989-02-16 マクダーミッド,インコーポレーテッド Printed circuit board manufacturing method
JPH0455553B2 (en) * 1986-08-06 1992-09-03 Macdermid Inc

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