JPS60119724A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60119724A
JPS60119724A JP58227160A JP22716083A JPS60119724A JP S60119724 A JPS60119724 A JP S60119724A JP 58227160 A JP58227160 A JP 58227160A JP 22716083 A JP22716083 A JP 22716083A JP S60119724 A JPS60119724 A JP S60119724A
Authority
JP
Japan
Prior art keywords
pattern
semiconductor device
metal
pad
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58227160A
Other languages
Japanese (ja)
Other versions
JPH0129053B2 (en
Inventor
Takeshi Suzuki
毅 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58227160A priority Critical patent/JPS60119724A/en
Publication of JPS60119724A publication Critical patent/JPS60119724A/en
Publication of JPH0129053B2 publication Critical patent/JPH0129053B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To increase the degree of freedom of element design as well as to improve the degree of integration of the titled semiconductor device by a method wherein the semiconductor device is composed of an element forming region to be formed on a semiconductor substrate, a positioning pattern provided outside the element forming region, a metal pad and a metal wiring which are formed on the positioning pattern. CONSTITUTION:An element forming region 2 is provided on a semiconductor sub strate 1, a positioning pattern 10 is formed outside the region 2, and a metal pad 4 and a metal wiring 3 are formed in such a manner that they will be positioned within said positioning pattern 10. Accordingly, as the function to be performed by the pattern 10 finishes at this point, the space occupied by the pattern 10 can be used for other prupose. Especially, as the pad 4 and the wiring 3 are formed in the mask-matching process which will be performed finally, other parts can be provided on the position excluding the pad 4 and the wiring 3 as occasion demands, thereby enabling to increase the degree of freedom in design.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a semiconductor device.

〔従来技術〕[Prior art]

一般に半導体装置をウェハ上に形成する場合、複数のマ
スク合せ工程があるが、各工程において使用するマスク
の位置を合せるため最初の製造工程でチップ上に位置合
せ用のパターンが形成される。すなわち、製造工程で使
用するマスクの数よ＃）１個少ない位置合せ用パターン
が、例えばエツチング法によシチップ上の素子形成領域
外に形成される。Generally, when forming a semiconductor device on a wafer, there are a plurality of mask alignment processes, and in order to align the positions of the masks used in each process, an alignment pattern is formed on the chip in the first manufacturing process. That is, alignment patterns one less than the number of masks used in the manufacturing process are formed outside the element forming area on the chip by, for example, an etching method.

第１図及び第２図は位置合せ用パターンを形成した従来
の半導体チップの上面図である。FIGS. 1 and 2 are top views of conventional semiconductor chips on which alignment patterns are formed.

第１図に示すように、半導体基板１上には素子形成領域
２、金属配線３、金属バッド４及び位置合せ用パターン
５が形成されている。位置合せ用パターン５は半導体基
板１上のチップ内に一定のスペ；スを有して形成されて
いるため、素子等の設計の自由度を制限すると共に、半
導体装置の集積度の向上を阻害する欠点がある。As shown in FIG. 1, an element formation region 2, metal wiring 3, metal pads 4, and alignment patterns 5 are formed on a semiconductor substrate 1. Since the alignment pattern 5 is formed with a certain amount of space within the chip on the semiconductor substrate 1, it limits the degree of freedom in designing elements, etc., and impedes the improvement of the degree of integration of semiconductor devices. There are drawbacks to doing so.

第２図においては、スクライブ線６の一部が拡大され、
その上に位置合せ用パターン５′が形成されている。こ
のように位置合せ用パターン５′がチップの外部に形成
される場合は素子等の設計の自由度は確保されるが、ス
クライブ線が広くなるため集積度の向上した半導体装置
が得られない欠点がある。In FIG. 2, a part of the scribe line 6 is enlarged,
An alignment pattern 5' is formed thereon. When the alignment pattern 5' is formed outside the chip in this way, flexibility in designing elements etc. is ensured, but the drawback is that a semiconductor device with an improved degree of integration cannot be obtained because the scribe lines become wider. There is.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、素子等の設計が自
由にできしかも集積度の向上した半導体装置を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a semiconductor device in which elements can be designed freely and the degree of integration is improved.

〔発明の構成〕[Structure of the invention]

本発明の半導体チップ、半導体基板上に形成された素子
形成領域と、該素子形成領域の外部に形成された位置合
せ用パターンと、該位置合せ用パターン上に形成された
金属パッド及び又は金、輿配線とを含んで構成される。A semiconductor chip of the present invention, an element formation area formed on a semiconductor substrate, an alignment pattern formed outside the element formation area, a metal pad and/or gold formed on the alignment pattern, It consists of a palanquin wiring.

〔実施例の説明〕[Explanation of Examples]

次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第３図は本発明の一実施例の上面図である。FIG. 3 is a top view of one embodiment of the present invention.

半導体基板１上には素子形成領域２と素子形成領域２の
外部に位置合せ用パターン１０が形成されている。そし
てこの位置合せ用パターン１０上には金属パッド４及び
金属配線３が形成されている。すなわち、位置合せ用パ
ターン１０は、各製造工程においてマスクとの位置合せ
が完了すればその使命は終了する。従ってそのスペース
を他に転用することが可能である。On the semiconductor substrate 1, an element formation region 2 and an alignment pattern 10 are formed outside the element formation region 2. Metal pads 4 and metal wiring 3 are formed on this alignment pattern 10. That is, the mission of the alignment pattern 10 ends when alignment with the mask is completed in each manufacturing process. Therefore, the space can be used for other purposes.

特に金属パッドや金属配線は最終のマスク合せ工程で形
成されるため位置合せ用パターンｌ。In particular, since metal pads and metal wiring are formed in the final mask alignment process, the alignment pattern l.

上に都合よく形成することができる。この場合、金属バ
ッド４や金属配線３を形成する際に用いるマスクの位置
合せ用パターンを除いた他の位置合せ用パターン１０上
には、必要に応じて酸化膜等を形成して平坦化し金跣バ
ッド４や金属配線３が形成しゃすい状態にしておくこと
ができる。can be conveniently formed on top. In this case, if necessary, an oxide film or the like is formed on the alignment pattern 10 other than the alignment pattern of the mask used when forming the metal pad 4 and the metal wiring 3 to flatten the metal pad 4 and the metal wiring 3. The leg pad 4 and the metal wiring 3 can be easily formed.

このように構成された本発明の半導体装置においては、
位置合せ用パターンのスペースが金属パッドや金属配線
の形成に利用することができるため位置合せ用パターン
のスペースは、素子形成領域外、すなわち金属パッドや
金属配線を形成する領域内の任意の場所に確保すること
ができる。従って素子や金属パッド等のレイアウトも位
置合せ用パターンを気にすることなく自由に行なえるた
め設計工数が削減される。、、更に、位置合せ用パター
ン専用のスペースや広いスクライブ線を設ける必要がな
いため集積度が向上する。In the semiconductor device of the present invention configured as described above,
Since the space of the alignment pattern can be used for forming metal pads and metal wiring, the space of the alignment pattern can be placed anywhere outside the element formation area, that is, within the area where metal pads and metal wiring are formed. can be secured. Therefore, the layout of elements, metal pads, etc. can be freely performed without worrying about alignment patterns, reducing the number of design steps. Furthermore, since there is no need to provide a dedicated space for alignment patterns or wide scribe lines, the degree of integration is improved.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、位置合せ
用パターンの存在を気にすることなく素子や金属パッド
等の設計が自由にできしかも位置合せ用パターンのスペ
ースを削減できるため集積度の向上した半導体装置が得
られるのでその効果は太きい。As explained in detail above, according to the present invention, elements, metal pads, etc. can be designed freely without worrying about the existence of alignment patterns, and the space for alignment patterns can be reduced, resulting in higher integration density. The effect is significant because a semiconductor device with improved properties can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は位置合せ用パターンを形成した従来
の半導体チップの上面図、第３図は本発明の一実施例の
上面図である。 １・・・・・・半導体基板、２・・・・・・素子形成領
域、３・・・・・・金属配線、４・・・・・・金員バッ
ド、５．５’、　１０　・・・・・・位置合せ用パター
ン。 第１図 第２図 肇３図1 and 2 are top views of a conventional semiconductor chip on which alignment patterns are formed, and FIG. 3 is a top view of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Element formation region, 3...Metal wiring, 4...Metal pad, 5.5', 10... ...Positioning pattern. Figure 1 Figure 2 Hajime 3

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成された素子形成領域と、該素子形成
領域の外部に形成された位置合せ用パターンと、該位置
合せ用パターン上に形成された金属バッド及び又は金属
配線とを含むことを特徴とする半導体装置。It is characterized by including an element formation area formed on a semiconductor substrate, an alignment pattern formed outside the element formation area, and a metal pad and/or metal wiring formed on the alignment pattern. semiconductor device.
JP58227160A 1983-12-01 1983-12-01 Semiconductor device Granted JPS60119724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58227160A JPS60119724A (en) 1983-12-01 1983-12-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58227160A JPS60119724A (en) 1983-12-01 1983-12-01 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60119724A true JPS60119724A (en) 1985-06-27
JPH0129053B2 JPH0129053B2 (en) 1989-06-07

Family

ID=16856430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58227160A Granted JPS60119724A (en) 1983-12-01 1983-12-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60119724A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051807A (en) * 1987-04-07 1991-09-24 Seiko Epson Corporation Integrated semiconductor structure with incorporated alignment markings

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152130A (en) * 1981-03-16 1982-09-20 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57152130A (en) * 1981-03-16 1982-09-20 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051807A (en) * 1987-04-07 1991-09-24 Seiko Epson Corporation Integrated semiconductor structure with incorporated alignment markings

Also Published As

Publication number Publication date
JPH0129053B2 (en) 1989-06-07

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