JPS60111498A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS60111498A JPS60111498A JP21914383A JP21914383A JPS60111498A JP S60111498 A JPS60111498 A JP S60111498A JP 21914383 A JP21914383 A JP 21914383A JP 21914383 A JP21914383 A JP 21914383A JP S60111498 A JPS60111498 A JP S60111498A
- Authority
- JP
- Japan
- Prior art keywords
- heat transfer
- heat
- substrate
- conductive layer
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は電子部品の放熱性の向上を図ったプリント配線
基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a printed wiring board that improves the heat dissipation of electronic components.
プリント配線基板は、従来一般に、基板表面に所定のパ
ターンで導電層を形成し、この導電層上にランドを残し
てソルダレジスト層を設けて構成されており、ランドに
形成されたリード線挿通孔に電子部品のリード線を挿通
した状態で例えば溶融半田槽に基板下面を浸すことによ
りリード線をランドに半田付けするようにしている。而
して、プリント基板に装清される電子部品の放熱を図る
には、該電子部品に放熱板を取付けたり、或いは基板自
体を放熱性に優れる金属製としたりするようにしていた
。Conventionally, printed wiring boards are generally constructed by forming a conductive layer in a predetermined pattern on the surface of the board, and providing a solder resist layer on this conductive layer with lands left behind, and lead wire insertion holes formed in the lands. The lead wires are soldered to the lands by, for example, dipping the bottom surface of the board into a molten solder bath with the lead wires of the electronic components inserted therein. In order to dissipate heat from the electronic components mounted on the printed circuit board, a heat dissipation plate is attached to the electronic components, or the board itself is made of metal, which has excellent heat dissipation properties.
しかしながら、電子部品に逐一放熱板を取付ける方式で
は取付作業が頗る面倒で組立コストが嵩み、また基板自
体を金属製とする方式では材料費が甑めて高価になると
いう欠点がある。However, the method of attaching heat sinks to electronic components one by one has the disadvantage that the installation work is extremely troublesome and the assembly cost increases, and the method of making the board itself from metal increases the material cost and becomes expensive.
本発明の目的は、電子部品の放熱性に優れ且つ安価に製
造できるプリント配線基板を提供するにある。An object of the present invention is to provide a printed wiring board that has excellent heat dissipation properties for electronic components and can be manufactured at low cost.
本発明は、基板表面に導電層によりランドに連続して伝
熱部全形成すると共に、該伝熱部上に設けられるソルダ
レジスト層を伝熱部の−Ｓを露出させて半田付Ｎを可能
ならしめる複数の抜き部を有するように形成する構成と
なすことにより、ソルダレジスト層の抜き部において露
出する伝熱部に付着する半田から電子部品の熱を放散さ
せ得るようにするところに特徴を有する。In the present invention, a conductive layer is used to form all the heat transfer parts on the surface of the substrate in a continuous manner with the lands, and the solder resist layer provided on the heat transfer parts exposes the -S of the heat transfer parts to enable soldering N. The feature is that the heat of the electronic component can be dissipated from the solder that adheres to the heat transfer part exposed in the solder resist layer's punched parts by forming the solder resist layer with a plurality of punched parts. have
以下本発明の一実施例につき図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.
まず、第１図乃至第３図において、１は絶縁材製の基板
、２はこの基板ＩＫ影形成た多数のり−Ｆ線線通通孔あ
る。５は基板１の一方の面（”ｌ”’面）ＶＣ例えば銅
箔のエッチ゛ングによる周知のプリント配線手段により
設けた導電層で、これはリード線挿通孔２０周縁部に位
置するランド４を含んで所定の配線パターンを描くよう
形成されている。５は導電層３により形成された伝熱部
で、これは所定のランド４の周縁に連続して比較的広い
面積をもって略矩形状を成すよう形成されている。６は
ソルダレジスト層で、これは周知の如く不要部分に半田
が付着することを防止すべく設けられるものであって、
導電層３のうちランド４部分を残すように基板１の略全
域に設けられると共に、上記伝熱部５上に設けられるソ
ルダレジスト層乙にはスリット状の多数の抜き部７が形
成されていて該抜き部７において伝熱部５の一部が露出
されるようにしている。First, in FIGS. 1 to 3, reference numeral 1 indicates a substrate made of an insulating material, and reference numeral 2 indicates a large number of glue-F line through holes formed in the substrate IK. Reference numeral 5 denotes a conductive layer provided on one surface ("l" surface) of the substrate 1 by a well-known printed wiring method such as etching of copper foil, and this includes the land 4 located at the periphery of the lead wire insertion hole 20. It is formed to draw a predetermined wiring pattern. Reference numeral 5 denotes a heat transfer portion formed by the conductive layer 3, which is formed so as to be continuous with the periphery of a predetermined land 4 and to have a relatively wide area and a substantially rectangular shape. 6 is a solder resist layer, which is provided to prevent solder from adhering to unnecessary parts, as is well known.
The conductive layer 3 is provided over almost the entire area of the substrate 1 so as to leave the land 4 portion, and a large number of slit-like cutout portions 7 are formed in the solder resist layer B provided on the heat transfer portion 5. A part of the heat transfer part 5 is exposed in the cutout part 7.
一方、第４図は上記構成のプリンｌ−ｖ１ｍ基板に電子
部品を半田付けしたものを示し、この萬４図において、
８は電子部品たるトランジスタで、これのコレクタのリ
ード線８ａはリード線挿通孔２を通して伝熱部５ａ一連
続して有するランド４に半田付けされ、エミッタ及びベ
ースの各リード線８ｂ及び８Ｃは夫々側のリード線挿通
孔２全通して他のランド４．４に半田付けされている。On the other hand, FIG. 4 shows a printer l-v1m board having the above configuration with electronic components soldered to it.
Reference numeral 8 denotes a transistor which is an electronic component, the collector lead wire 8a of which is soldered to the land 4 which is continuous with the heat transfer part 5a through the lead wire insertion hole 2, and the emitter and base lead wires 8b and 8C are respectively connected. The lead wire insertion hole 2 on the side is completely passed through and soldered to another land 4.4.
この半田付けは、トランジスタ８の各リード線８ａ乃至
８Ｃを基板１の各リード線挿通孔２に上方から挿通した
状態で、基板１の導電層３側の面を溶融半田槽に浸して
行ったものである。さて、９は伝熱ｓ５に付所形成され
たビーＦ状をなす多数の放熱半田部で、これは上述の半
田付は時にソルダレジスト層６の抜き部７において露出
する伝熱部５に付着・固化して形成されている。This soldering was performed by immersing the surface of the conductive layer 3 side of the substrate 1 in a molten solder bath while the lead wires 8a to 8C of the transistor 8 were inserted into the lead wire insertion holes 2 of the substrate 1 from above. It is something. Now, reference numeral 9 denotes a large number of heat dissipating solder parts in the shape of a bead formed in the heat transfer s5.・It is solidified and formed.
次に、１記構成の作用？説明する。トランジスタ８が発
熱すると、その熱は主として発熱源たる半導体ペレット
にＬＴ接板接続れているコレクタのリード線８ａＴｈ伝
わって基板１側に流れ、リード線８ａが接続されている
ランド４から更に伝熱部５に伝えられる。そして、この
熱は、伝熱部５から艶に多数の放熱半田部９に伝えられ
、この放熱半田部９が広い表面積をもって空気に晒され
た形態となっていることから、該放熱半田部９から周囲
に放散される。これにより、トランジスタ８からの熱が
効果的に発散されるので、トランジスタ８の放熱を図る
ことができる。Next, what is the effect of configuration 1? explain. When the transistor 8 generates heat, the heat is mainly transmitted to the semiconductor pellet as the heat source through the lead wire 8aTh of the collector connected to the LT contact plate, flows to the substrate 1 side, and further heat is transferred from the land 4 to which the lead wire 8a is connected. This will be communicated to Department 5. This heat is smoothly transmitted from the heat transfer part 5 to a large number of heat dissipating solder parts 9, and since the heat dissipating solder parts 9 have a large surface area and are exposed to the air, the heat dissipating solder parts 9 is dissipated into the surrounding area. As a result, heat from the transistor 8 is effectively dissipated, so that heat dissipation from the transistor 8 can be achieved.
上記した木実流側によれば、トランジスタ８を単に基板
１に半田付けするのみでその放熱を図り得るので、トラ
ンジスタ８に逐−放熱板等を取付けｆｃｖせずとも済ん
でプリント配線基板への電子部品の組付作業が頗る簡単
になる。しかも、基板（ζ ）
１表面に木来設けられる導電層５によって伝熱部５を形
成すると共に、導電Ｍ３上にやはり本来的ＶＣ設けられ
るソルダレジスト層乙のうち伝熱部５上に位置する部分
に複数の抜き部７を形成するという構成であるから、基
板１を高価な金属製のものとしたすせずとも従前の材料
や製法のままで製造することができて製造コストを安価
に済ませ得る。According to the above-mentioned method, heat radiation can be achieved by simply soldering the transistor 8 to the board 1, so there is no need to attach a heat sink etc. to the transistor 8 and perform FCV. Assembling electronic parts becomes much easier. Moreover, the heat transfer part 5 is formed by the conductive layer 5 provided on the surface of the substrate (ζ) 1, and the solder resist layer B, which is originally provided on the conductive M3, is located on the heat transfer part 5. Since the structure is such that a plurality of cutouts 7 are formed in the part, the substrate 1 can be manufactured using conventional materials and manufacturing methods without having to make the substrate 1 made of expensive metal, reducing manufacturing costs. It can be done.
尚、本発明は上記し且つ図面に示す夾流側のみに限定さ
れるものではなく、例えば抜きＳを放射状や同心円状を
成すように形成したり、トランジスタに限らず抵抗・コ
イル等を半田付けするランドに連続して伝熱部を形成す
るようにしたりする等適宜変更して賽施し得るものであ
る。It should be noted that the present invention is not limited to the above-mentioned flow side shown in the drawings. For example, the holes S may be formed in a radial or concentric shape, or not only transistors but also resistors, coils, etc. may be soldered. It can be applied by making appropriate changes, such as forming a heat transfer part continuously on the land.
以上述べたよう四、本発明は、基板表面に導電層により
ランドに連続して伝熱部を形成すると共に、該伝熱部上
に設けられるソルダレジスト層ヲ、伝熱部の一部全露出
させる抜き部を有するようにｉ成−ｔ−るところに特徴
を有し、この結果、抜き部において露出する伝熱部に付
層する半田により伝熱部ひいてはそのランドに半田付け
された電子部品の放熱を効果的に図ることができるので
、放熱性に優れ九プリント配線基板を安価に製造し得る
という効果を奏する。As described above, 4. the present invention forms a heat transfer part continuous to the land with a conductive layer on the surface of the substrate, and at the same time, the solder resist layer provided on the heat transfer part is partially or completely exposed. As a result, the electronic component is soldered to the heat transfer area and the land thereof by the solder layered on the heat transfer area exposed in the cutout. Since heat dissipation can be effectively achieved, it is possible to produce a printed wiring board with excellent heat dissipation properties at low cost.
図面は本発明の一実施例を示し、第１図はプリント配線
基板の断面図、第２図はソルダレジスト層の形成器の状
態を示す同底面図、第３図はソルダレジスト層の形成後
の状態を示す同底面図、第４図は半田付は後の状態で示
すプリント配線基板の断面図である。
図中、１は基板、５は導電層、４はランド、５は伝熱部
、６はソルダレジスト層、７は抜＠部、８はトランジス
タ（電子部品ン、８ａ乃至８ｃはリード線、９は放熱半
田部である。
（７）
第１Ｍ
第２０
第４ 口The drawings show one embodiment of the present invention, in which Fig. 1 is a cross-sectional view of a printed wiring board, Fig. 2 is a bottom view of the same showing the state of the solder resist layer forming device, and Fig. 3 is a view after the solder resist layer is formed. FIG. 4 is a cross-sectional view of the printed wiring board shown after soldering. In the figure, 1 is a substrate, 5 is a conductive layer, 4 is a land, 5 is a heat transfer part, 6 is a solder resist layer, 7 is an open part, 8 is a transistor (electronic component), 8a to 8c are lead wires, 9 is the heat dissipation solder part. (7) 1st M 20th 4th port
Claims (1)
の導電層上に電子部品のリード線が半田付けされるラン
ドを残してソルダレジスト層を設けるものであって、前
記基板表面に前記導電層により前記ランドに連続して伝
熱ｌｆＢを形成すると共に、該伝熱部上に設けられるツ
ルダレジス）７０−１伝熱部の一部を露出させて半田付
Ｍｋ可能ならしめる複数の抜きｓｒ有するように形成し
たことを特徴とするプリント配線基板。1. A conductive layer is formed in a predetermined pattern on the surface of the substrate, and a solder resist layer is provided on the conductive layer, leaving lands to which lead wires of electronic components are soldered, and the conductive layer is formed on the surface of the substrate. The layer forms a heat transfer lfB continuous to the land, and has a plurality of cutouts sr that expose a part of the heat transfer part (70-1) and enable soldering Mk provided on the heat transfer part. A printed wiring board characterized by being formed as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21914383A JPS60111498A (en) | 1983-11-21 | 1983-11-21 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21914383A JPS60111498A (en) | 1983-11-21 | 1983-11-21 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111498A true JPS60111498A (en) | 1985-06-17 |
Family
ID=16730889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21914383A Pending JPS60111498A (en) | 1983-11-21 | 1983-11-21 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111498A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016046465A (en) * | 2014-08-26 | 2016-04-04 | Ｎｅｃエンジニアリング株式会社 | Printed board and circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5714476B2 (en) * | 1977-12-12 | 1982-03-24 |
-
1983
- 1983-11-21 JP JP21914383A patent/JPS60111498A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5714476B2 (en) * | 1977-12-12 | 1982-03-24 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016046465A (en) * | 2014-08-26 | 2016-04-04 | Ｎｅｃエンジニアリング株式会社 | Printed board and circuit board |
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