JPS60107848A - Semiconductor device and lead frame used for said device - Google Patents

Semiconductor device and lead frame used for said device

Info

Publication number
JPS60107848A
JPS60107848A JP58213960A JP21396083A JPS60107848A JP S60107848 A JPS60107848 A JP S60107848A JP 58213960 A JP58213960 A JP 58213960A JP 21396083 A JP21396083 A JP 21396083A JP S60107848 A JPS60107848 A JP S60107848A
Authority
JP
Japan
Prior art keywords
leads
lead
lead frame
semiconductor device
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58213960A
Other languages
Japanese (ja)
Inventor
Yukio Tamaki
玉木　幸雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58213960A priority Critical patent/JPS60107848A/en
Publication of JPS60107848A publication Critical patent/JPS60107848A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To miniaturize a semiconductor device by arranging a plurality of leads constituting a lead frame at two steps in zigzag manner, bending the leads in sections projected to the outside to a L shape and bringing both bottoms of the leads arranged at two steps to the same planes as the bottom of a resin package in the semiconductor device having a shape in which a semiconductor element is fixed onto the lead frame and the lead frame is received in the resin package. CONSTITUTION:A semiconductor element is fastened to a semiconductor loading section for a lead frame, and the semiconductor loading section is sealed in a resin package 2 while projecting lead end sections in the frame, thus manufacturing a semiconductor device 1. In the constitution, leads 3 are formed in two-step structure while being zigzag arranged, and the end sections of each lead 3 are bent downward to a L shape in external projecting sections, and the bottoms of the external projecting sections are aligned with the bottom of the package 2 and formed in the same surface. Accordingly, the size of the package 2 may be small, and the device 1 is miniaturized by that much.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置およびその製造におい℃用いられる
リードフレームに関し、特化半導体装置の小型化が達成
できる技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device and a lead frame used in its manufacture, and relates to a technology that can achieve miniaturization of specialized semiconductor devices.

〔背景技術〕[Background technology]

半導体装置の高郷積化、多機能化によりて外部端子（リ
ード）の数は増大し、半導体装置は大型となる傾向にあ
るが、半導体装置を組み込む電子機器群の小型化に伴な
って半導体装置の小型化が強く望まれている。チップ等
の主要部をレジンパッケージで被りたレジンモールド型
半導体装置においても、たとえば電子材料１９８０年１
０月号１２１〜１２４頁［ミニフラットＩＯＪにも記載
されているように、より小型化が図られている。As semiconductor devices become more dense and multi-functional, the number of external terminals (leads) increases and semiconductor devices tend to become larger. There is a strong desire for miniaturization. Even in resin molded semiconductor devices in which the main parts such as chips are covered with a resin package, electronic materials 1980 1
October issue, pages 121-124 [As described in the mini-flat IOJ, further miniaturization has been attempted.

ところで、従来のレジンモールド型半導体装置は、たと
えば、電子材料１９８２年８月号６９〜７４頁「リード
フレーム」にも記載されているように、板状のリードフ
レームを用いて製造されている。By the way, conventional resin molded semiconductor devices are manufactured using plate-shaped lead frames, as described in "Lead Frame", pages 69-74 of Electronic Materials, August 1982, for example.

しかし、このようなリードフレームによる半導体装置の
製造では、リード数の多い製品群の小型化は、以下の理
由から難しいということが本発明者によってあきらかと
された。However, in manufacturing semiconductor devices using such lead frames, the inventors have found that it is difficult to miniaturize a product group with a large number of leads for the following reasons.

すなわち、リードフレームは一枚の平面板によって形成
されているため、リードは同一平面上に並んでいる。リ
ード数の増大によってリードピッチはより小さく設計さ
れるが、ショート防止等の観点から限度がある。また、
リードフレームの小型化という点から考えれば、前記リ
ードピッチを小さくする以外に、リード幅を小さくする
ことが考えられる。しかし、リード数が多くなるにつれ
て、レジンパッケージの寸法が大きくなるため、レシン
パッケージ内を延在するリード（インナーリード）の長
さが長くなり、リードの強度低下を引き起こす。この結
果、インナーリードの幅の縮小化にも限度があり、リー
ド数増加に伴なってパッケージ寸法は順次増大すること
になる。That is, since the lead frame is formed from one plane plate, the leads are arranged on the same plane. As the number of leads increases, the lead pitch is designed to be smaller, but there is a limit from the viewpoint of preventing short circuits. Also,
From the point of view of miniaturizing the lead frame, it is conceivable to reduce the lead width in addition to reducing the lead pitch. However, as the number of leads increases, the dimensions of the resin package increase, and the length of the leads (inner leads) extending inside the resin package increases, causing a decrease in the strength of the leads. As a result, there is a limit to the reduction in the width of the inner leads, and as the number of leads increases, the package dimensions gradually increase.

一方、レジンパッケージにおいては、パッケージが大き
くなる忙つれて、レジンモールド時のモールド型のキャ
ピテイ内へのレジンの流入が複雑となり、ボイド（気泡
）等の欠陥の発生が増大し易くなって製品品質の低下を
招くことも本発明者によってあきらかとされた。On the other hand, in the case of resin packages, as the size of the package increases, the flow of resin into the cavity of the mold during resin molding becomes complicated, which increases the likelihood of defects such as voids (bubbles), resulting in poor product quality. The inventors have also found that this may lead to a decrease in .

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体装置の不調化を図ることにある。 An object of the present invention is to prevent malfunctions of semiconductor devices.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明はリードフレームを平行に重ね合わせ
た２枚の副リードフレームで構成しておき、このリード
フレームを用いて半導体装置を製造するものである。副
リードフレームのリードは他の副リードフレームのリー
ド間の上方するいは下方に位置して千鳥状に２段に配列
されている。That is, in the present invention, a lead frame is constructed of two sub-lead frames superimposed in parallel, and a semiconductor device is manufactured using these lead frames. The leads of the sub-lead frame are arranged in two stages in a staggered manner, located above or below the leads of other sub-lead frames.

また、リードは内端近傍部分で上方あるいは下方に一段
折れ曲がり、内端のワイヤ接続部分はすべて同一平面上
になっ℃いる。したがって、このようなリードフレーム
によって製造された半導体装置はリードがパッケージの
内外で千鳥状に二段となって配列されていることから、
従来のようにリードが一段に配列された半導体装置より
も小型となる。Further, the leads are bent one step upward or downward near the inner end, and the wire connection portions at the inner end are all on the same plane. Therefore, in a semiconductor device manufactured using such a lead frame, the leads are arranged in two stages in a staggered manner inside and outside the package.
It is smaller than a conventional semiconductor device in which leads are arranged in one row.

〔実施例〕〔Example〕

第４図は本発明の一実施例による半導体装置の正面図、
第２図は同じく平面図、第３図は同じく側面図、第４図
（ａｔ　ｔ　（ｂ）は前記半導体装置の組立に用いるリ
ードフレームを構成する副リードフレームの平面図、第
５図（ａ）、　（ｂ）は同じく一部の断面図、第６図は
同じくリードフレームの要部を示す斜視図である。FIG. 4 is a front view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a plan view, FIG. 3 is a side view, FIG. ) and (b) are partially sectional views, and FIG. 6 is a perspective view showing the main parts of the lead frame.

レジンモールド型の半導体装置１は第１図〜第３図で示
すようにレジンパッケージ２の両側面からリード３が千
鳥状に２段になって突出した構造となっている。また、
各リード３は途中で階段状に一段折れ曲がり、先端部下
面はレジンパッケージ２の下面と略同−面となるように
形成され、いわゆる面実装構造となっている。各リード
３はその延在方向に垂直となる面における配列はいずれ
も千鳥状に２段となる配列となっている。これは、後述
するがレジンパッケージ２内においても、内端部を除い
て同様な配列と・なっている。なお、隣接するリード相
互のピッチ（リードピッチ）はリードを線材と考えた場
合ともにａと同一にすることにより、レジンパッケージ
２の平面方向およびこれに垂直となる高さ方向の寸法を
最小に抑えることができる。As shown in FIGS. 1 to 3, a resin mold type semiconductor device 1 has a structure in which leads 3 protrude in two stages in a staggered manner from both sides of a resin package 2. Also,
Each lead 3 is bent one step in the middle, and the lower surface of the tip is formed to be approximately flush with the lower surface of the resin package 2, forming a so-called surface mount structure. Each lead 3 is arranged in two stages in a staggered manner in a plane perpendicular to its extending direction. As will be described later, this arrangement is similar within the resin package 2, except for the inner end. In addition, by making the pitch between adjacent leads (lead pitch) the same as a when considering the leads as wire rods, the dimensions of the resin package 2 in the plane direction and the height direction perpendicular thereto are minimized. be able to.

このような半導体装置１はリード配列方向の寸法が従来
のリードが一列の半導体装置に比較して半分となる。し
たがって、レジンパッケージ２の両側からり−ド３’２
突出させる本実施例の半導体装置ではレジンパッケージ
２の大きさく面積）が従来の半導体装置の半分となる。Such a semiconductor device 1 has a dimension in the lead arrangement direction that is half that of a conventional semiconductor device with a single line of leads. Therefore, from both sides of the resin package 2,
In the protruding semiconductor device of this embodiment, the size and area of the resin package 2 is half that of a conventional semiconductor device.

つぎに、このような半導体装置１の製造（組立）方法に
ついて説明し、あわせてレジンパッケージ２内部の説明
とする。半導体装置ｌの組立にあっては、第６図に示す
ようなリードフレーム４が用いられる。このリードフレ
ーム４は第４図（ａｌ、　（ｂｌで示すような２枚の副
リードフレーム５，６によって構成されている。副リー
ドフレーム５，６は平行に重ねられ、かつ両側リードフ
レーム５，６のフレーム枠７，８の突出した接続部９，
１００溶接によって固定され一体化構造となっている。Next, a method for manufacturing (assembling) such a semiconductor device 1 will be explained, and the inside of the resin package 2 will also be explained. In assembling the semiconductor device 1, a lead frame 4 as shown in FIG. 6 is used. This lead frame 4 is composed of two sub lead frames 5 and 6 as shown in FIGS. 6, the protruding connecting portions 9 of the frame frames 7, 8,
It is fixed by 100% welding and has an integrated structure.

副リードフレーム５，６の一方は第４図（ａ）に示すよ
うに、タブ１１．タブ１１をフレーム枠７に接続するタ
ブ吊りリード１２．タブ１１に内端を臨ませる複数のり
−ド３．リード３をフレーム枠７に支持スるタイバー１
３．レジンモールド時のレジン流を止める役割を果たす
ダム１４とからなっている。また、このタブ有り副リー
ドフレーム５はタブ１１およびリード３の内端が第５図
（ａ）に示すように低くなっている。このため、タブ吊
りリード１２およびリード３は途中部分で一段階段状に
折れ曲がっている。なお、タブ１１の上面には半導体素
子（チップ）１５が固定され、チップ１５の電極とり−
ド３の内端のワイヤ接続部１６はワイヤ１７で接続され
る。この際、ワイヤ１７が垂れてチップ１５の緑化接触
して生じるショート不良が起き易い。そこで、この例で
はチップ１５の上面とり−ド３のワイヤ接続部１６の面
とが略一致するように、タブ１１はリード３の内端部よ
りもさらに単りなっている。As shown in FIG. 4(a), one of the sub lead frames 5 and 6 has a tab 11. A tab suspension lead 12 for connecting the tab 11 to the frame frame 7. A plurality of glue boards with their inner ends facing the tabs 11 3. Tie bar 1 that supports lead 3 on frame frame 7
3. It consists of a dam 14 that plays a role in stopping the flow of resin during resin molding. Further, in this sub-lead frame 5 with tabs, the inner ends of the tabs 11 and leads 3 are lowered as shown in FIG. 5(a). For this reason, the tab suspension lead 12 and the lead 3 are bent in one step in the middle. Note that a semiconductor element (chip) 15 is fixed on the upper surface of the tab 11, and the electrodes of the chip 15 are fixed to the upper surface of the tab 11.
A wire connection portion 16 at the inner end of the card 3 is connected with a wire 17. At this time, the wire 17 hangs down and contacts the chip 15 with green contact, which tends to cause a short circuit failure. Therefore, in this example, the tab 11 is made even more slender than the inner end of the lead 3 so that the upper surface of the chip 15 substantially coincides with the surface of the wire connection portion 16 of the lead 3.

一方、前記タブ有り副リードフレーム５の下側に位置す
る第４図（ｂｌで示すタブ無し副リードフレーム６はタ
ブ有り副リードフレーム５のフレーム枠７．タイ゛バー
１３．ダム１４と対面するフレーム枠８．タイバー１８
．ダム１９を有している。On the other hand, the tab-less sub-lead frame 6 located below the tab-equipped sub-lead frame 5 shown in FIG. Frame frame 8. Tie bar 18
．． It has a dam 19.

しかし、タブ有り副リードフレーム５のようなタブ１１
およびタブリード１２は有していない。また、リード３
はタブ有り副リードフレーム５と同様に有しているが、
その位置は平面的に見てタブ有り副ＩＪ−ドフレーム５
の各リード３の中間位置に１本ずつ位置するように配設
されている。また、タブ無し副リードフレーム６は第５
図（ｂ）に示すように、リード３の内端が上方に一段階
段状に折れ曲がっている。折れ曲がって水平となるリー
ド内端部分はワイヤ接続部２０となる。このワイヤ接続
部２０は、タブ有り副リードフレーム５とタブ無し副リ
ードフレーム６を重ねて一体化した際には、タブ有り副
リードフレーム５のワイヤ接続部１６と同一平面−ヒに
位置するようになっている。However, the tab 11 like the tab-equipped sub lead frame 5
And the tab lead 12 is not included. Also, lead 3
has the same structure as the tab-equipped sub-lead frame 5, but
Its position is 5th sub IJ-de frame with tab when viewed from above.
The leads 3 are arranged such that one lead is located in the middle of each lead 3. In addition, the sub lead frame 6 without tabs is the fifth
As shown in Figure (b), the inner end of the lead 3 is bent upward in one step. The inner end portion of the lead that is bent and becomes horizontal becomes a wire connection portion 20 . When the sub-lead frame 5 with tabs and the sub-lead frame 6 without tabs are stacked and integrated, this wire connection part 20 is positioned on the same plane as the wire connection part 16 of the sub-lead frame 5 with tabs. It has become.

これは、特に限定はされないが、ワイヤボンディング時
にリード側のワイヤ接続部の高さが高くなったり低くな
ったりすると接続し難いことによる。This is because, although not particularly limited, it is difficult to connect when the height of the wire connection portion on the lead side increases or decreases during wire bonding.

したがって、リード側のワイヤ接続部高さが一定でなく
とも確実にワイヤ接続ができるワイヤボンディング装置
である場合には、両側リードフレーム５，６におけるリ
ード内端部の同一平面化は必要ではなくなる。なお、リ
ード３が千鳥状に二段に配列されることによつ℃はじめ
てリードフレーム４およびレジンパッケージ２の小型化
が達成できる。これに対して、実施例ではリード内端部
分が一段となっているが、これはリード内端部はワイヤ
接続部１６．２０となることから、ワイヤ接続に必要な
面積（太さ）があればよく、他のＩＪ　−ド部分のよう
に大きな機械的強度を必要としないことによって他のリ
ード部分よりも細くできることによる。本発明はこの点
の着眼によって小型化が達成できたものである。Therefore, in the case of a wire bonding apparatus that can reliably connect wires even if the height of the wire connection portion on the lead side is not constant, it is not necessary to make the inner ends of the leads in both lead frames 5 and 6 on the same plane. Note that by arranging the leads 3 in two stages in a staggered manner, the lead frame 4 and the resin package 2 can be made smaller. On the other hand, in the embodiment, the inner end of the lead is one step, but this is because the inner end of the lead becomes the wire connection part 16.20, so if there is an area (thickness) necessary for wire connection, then This is often due to the fact that it does not require as much mechanical strength as other IJ-lead parts, so it can be made thinner than other lead parts. The present invention has achieved miniaturization by focusing on this point.

このようなリードフレーム４はタブ１１上にチップ１５
が接続される。また、チップ１５の電極とこれに対応す
るり、−ド３の内端のワイヤ接続部１６．２０はワイヤ
１７で電気的に接続される。Such a lead frame 4 has a chip 15 on the tab 11.
is connected. Further, the electrodes of the chip 15 and corresponding wire connection portions 16 and 20 at the inner end of the negative electrode 3 are electrically connected by wires 17.

つぎに、第６図で示すように、フレーム枠７，８および
ダム１４，１９によって取り囲まれる領域がレジンモー
ルドによるレジンパッケージ２によって被われる。その
後、不要となるリードフレーム部分は切断除去され、レ
ジンノ（・ノケージ２から突出するリード部分は成形さ
れ℃第」図〜第３図で示されるような半導体装置が製造
される。Next, as shown in FIG. 6, the area surrounded by the frames 7, 8 and the dams 14, 19 is covered with a resin package 2 made of resin mold. Thereafter, unnecessary lead frame portions are cut and removed, and lead portions protruding from the resin cage 2 are molded to produce a semiconductor device as shown in FIGS.

〔効果〕〔effect〕

（１）、本発明はレジンパッケージの内外に亘ってリー
ドが千鳥状に２段に配列されているため、半導体装置の
小型化が達成できる。(1) In the present invention, since the leads are arranged in two stages in a staggered manner both inside and outside the resin package, it is possible to achieve miniaturization of the semiconductor device.

（２）、本発明はリードフレームのリードはレジンモー
ルドされるインナーリード部分およびレジンモールドさ
れないアウターリード部分はともに千鳥状に２段となる
ように配列されている。この結果、レジンモールド領域
は大型化せず、大型化に伴なうレジンモールド時のレジ
ン流入状態の悪化が防止でき、たとえば、レジンパッケ
ージ内のボイド（気泡）の発生が低減でき、耐湿性の向
上が図れる。(2) In the present invention, the leads of the lead frame are arranged in two stages in a staggered manner, including an inner lead portion that is resin-molded and an outer lead portion that is not resin-molded. As a result, the resin mold area does not become large, and deterioration of resin inflow conditions during resin molding due to enlargement can be prevented.For example, the generation of voids (bubbles) in the resin package can be reduced, and moisture resistance can be improved. Improvements can be made.

（３）、本発明は組立加工設備の点から考えれば、リー
ド数の増大が図られてもリードフレームは大幅の大型化
とはならない。この結果、組立加工設備は大型化せず設
備費を安くできる。(3) Considering the present invention from the point of view of assembly processing equipment, even if the number of leads is increased, the lead frame will not be significantly enlarged. As a result, the assembly processing equipment does not need to be large-sized, and equipment costs can be reduced.

（４）、また、同様にリードフレームはリード数増大に
よっても大型とはなり難いことから取り扱いも容易で作
業性も高くなる。(4) Similarly, even if the number of leads increases, the lead frame does not become large in size, making it easy to handle and highly workable.

（５）、上記（１）〜（４）により、小型で品質が優れ
た半導体装置を安価に提供することができるという相乗
効果が得られる。(5) Due to the above (1) to (4), a synergistic effect can be obtained in that a compact and high quality semiconductor device can be provided at a low cost.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、前記実施例
ではリード内端部を同一平面に揃えるために、両方の副
リードフレームのリードを折り曲げたが、これはどちら
か−万のみを折り曲げる構造としてもよい。第７図はタ
ブ有り副す−ドフーーム５はリード３Ｙ折り曲げず、タ
ブ無し副リードフレーム６のリード３を折り曲げた例を
示す。この構造でも前記実施例と同様な効果が得られる
。Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment described above, the leads of both sub-lead frames were bent in order to align the inner ends of the leads on the same plane, but this may be structured so that only one of the leads is bent. FIG. 7 shows an example in which the leads 3Y of the sub-frame 5 with tabs are not bent, but the leads 3 of the sub-lead frame 6 without tabs are bent. Even with this structure, the same effects as in the above embodiment can be obtained.

また、本発明は第８図（ａ）、　（ｂ）に示すように、
レジンパッケージ２の４側面からり一ド３を突出させた
半導体装置ｌ、あるいは第１０図（ａｌｔ　（ｂｌに示
すように、プーアルインライン構造の半導体装置１にも
同様に適用でき前記実施例と同様な効果力玉得られる。Further, as shown in FIGS. 8(a) and (b), the present invention
It can be similarly applied to a semiconductor device 1 in which the resin package 2 has a gate 3 protruding from its four sides, or a semiconductor device 1 having a pull-in-line structure as shown in FIG. You can get an effective power ball.

特に４１１面からリード３’Ｌ’突出する半導体装置１
の場合には、レジンパッケージ２は面積的な小型化が図
れるので小型化の効果は大きい。In particular, a semiconductor device 1 with leads 3'L' protruding from the 411 plane.
In this case, the resin package 2 can be made smaller in terms of area, so the effect of smaller size is greater.

なお、第９図（ａ）、　（ｂ）は第８図（ａ）、　（ｂ
）ｋ示す半導体装置１の組立に用いる副リードフレーム
５，６であるが、リード３が４方向からタブ１１に向か
って延在する点だけが第６図で示すリードフレーム４と
異なるだけで他は同じであることからその説明は省略す
る。Note that Figures 9(a) and (b) are similar to Figures 8(a) and (b).
)K are the sub-lead frames 5 and 6 used for assembling the semiconductor device 1 shown in FIG. 6, but the only difference from the lead frame 4 shown in FIG. Since they are the same, their explanation will be omitted.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
ｌその背景となった利用分野であるレジンモールド型半
導体装置製造技術に適用した場合について説明したが、
それに限定されるものではなく、たとえば、パッケージ
から多数の棒体を突出するような物品の製造技術におい
ても、物品の小型化という面で適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the resin mold type semiconductor device manufacturing technology, which is the field of application that is the background of the invention.
The present invention is not limited thereto, and can be applied, for example, to manufacturing techniques for articles in which a large number of rods protrude from a package in terms of miniaturization of articles.

また、セラミック封止型半導体装置、又は、ガラス封止
型半導体装置にも適用できる。Furthermore, the present invention can also be applied to ceramic-sealed semiconductor devices or glass-sealed semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による半導体装置の正面図、 第２図は同じく平面図、 第３図は同じ（側面図、 第４図（ａｌｔ　（ｂ）は前記半導体装置の組立に用い
るリードフレームを構成する副リードフレームの平面図
、 第５図（ａｒｅ　（ｂｌは同じ（一部の断面図、第６図
は同じくリードフレームの要部を示す斜視図、 第７図は他の実施例による半導体装置の模式図、第８図
（ａ）、　（ｂ）は他の実施例による半導体装置の正面
図および平面図、 第９図（ａＬ　（ｂ）は同じく副リードフレームの要部
を示す模式的平面図、 第１０図（ａ）、　（ｂ）は他の実施例による半導体装
置の正面図および平面図である。 １・・・半導体装置、２・・・レジンパッケージ、３・
・・リード、４・・・リードフレーム、５，６・・・副
リードフレーム、７，８・惨・フレーム枠、９．ｌＯ・
・・接続部、１１・・・タブ、１２・・・タブ吊りリー
ド、１３・・・タイバー、１４・・・ダム、１５・・・
半導体素子（チップ）、１６・・・ワイヤ接続部、１７
・・・ワイヤ、１８・・・タイバー、１９・・・ダム、
２０・・・ワイヤ接続部。 第　３　図FIG. 1 is a front view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view, FIG. 3 is a side view, and FIG. FIG. 5 is a plan view of the sub-lead frame constituting the lead frame, FIG. FIGS. 8(a) and 8(b) are schematic diagrams of a semiconductor device according to an example, and FIGS. 8(a) and 8(b) are a front view and a plan view of a semiconductor device according to another embodiment. FIG. The schematic plan view shown in FIGS. 10(a) and 10(b) are a front view and a plan view of a semiconductor device according to another embodiment. 1... Semiconductor device, 2... Resin package, 3.
・・Lead, 4・Lead frame, 5, 6・Sub-lead frame, 7, 8・Disastrous・Frame frame, 9. lO・
...Connection part, 11...Tab, 12...Tab suspension lead, 13...Tie bar, 14...Dam, 15...
Semiconductor element (chip), 16... wire connection part, 17
...Wire, 18...Tie bar, 19...Dam,
20...Wire connection part. Figure 3

Claims (1)

【特許請求の範囲】 １、パッケージと、このパッケージの内部および外部に
亘って延在する複数のリードと、を有する半導体装置で
ありて、前記リードはパッケージの内外にあって千鳥状
に二段に配列されていることを特徴とする半導体装置。 ２、前記リードの内端部分は同一平面上に位置している
ことを特徴とする特許請求の範囲第１項記載の半導体装
置。 ３、半導体装置におけるパッケージの内外部に亘って延
在するリードフレームの一部に有するリードフレームで
あって、前記リードフレームは相互に重ね合されかつ一
体化された２枚の副リードフレームからなり、各副リー
ドフレームのリードは他の副リードフレームのリード間
の上方あるいは下方に位置し、リードフレームのリード
としては千鳥状に二段に配列され又いることを特徴とす
るリードフレーム。 ４、前記リードフレームのリードの内端部分は同一平面
上に位置していることｔ特徴とする特許請求の範囲第３
項記載のリードフレーム。[Claims] 1. A semiconductor device having a package and a plurality of leads extending inside and outside the package, the leads being arranged in two stages in a staggered manner inside and outside the package. A semiconductor device characterized by being arranged in. 2. The semiconductor device according to claim 1, wherein inner end portions of the leads are located on the same plane. 3. A lead frame included in a part of a lead frame extending inside and outside of a package in a semiconductor device, the lead frame consisting of two sub-lead frames that are overlapped and integrated with each other. A lead frame characterized in that the leads of each sub-lead frame are located above or below the leads of other sub-lead frames, and the leads of the lead frame are arranged in two stages in a staggered manner. 4. The third aspect of the present invention is characterized in that the inner end portions of the leads of the lead frame are located on the same plane.
Lead frame as described in section.
JP58213960A 1983-11-16 1983-11-16 Semiconductor device and lead frame used for said device Pending JPS60107848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58213960A JPS60107848A (en) 1983-11-16 1983-11-16 Semiconductor device and lead frame used for said device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58213960A JPS60107848A (en) 1983-11-16 1983-11-16 Semiconductor device and lead frame used for said device

Publications (1)

Publication Number Publication Date
JPS60107848A true JPS60107848A (en) 1985-06-13

Family

ID=16647909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58213960A Pending JPS60107848A (en) 1983-11-16 1983-11-16 Semiconductor device and lead frame used for said device

Country Status (1)

Country Link
JP (1) JPS60107848A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023700A (en) * 1988-06-17 1991-06-11 Ngk Insulators, Ltd. Minutely patterned structure
US5031024A (en) * 1989-09-05 1991-07-09 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-functions
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
WO2009004878A1 (en) * 2007-07-04 2009-01-08 Fujitsu Ten Limited Electronic part package, package parts and electronic device having the package, and package part manufacturing method
DE102020109493A1 (en) 2020-04-06 2021-10-07 Infineon Technologies Ag A SEMICONDUCTOR COMPONENT PACKAGE WITH TWO STACKED LEADFRAMES

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5023700A (en) * 1988-06-17 1991-06-11 Ngk Insulators, Ltd. Minutely patterned structure
US5100498A (en) * 1988-06-17 1992-03-31 Ngk Insulators, Ltd. Method of producing a minutely patterned structure
US5031024A (en) * 1989-09-05 1991-07-09 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-functions
US5557143A (en) * 1993-09-16 1996-09-17 Rohm Co., Ltd. Semiconductor device having two staggered lead frame stages
WO2009004878A1 (en) * 2007-07-04 2009-01-08 Fujitsu Ten Limited Electronic part package, package parts and electronic device having the package, and package part manufacturing method
JP2009016572A (en) * 2007-07-04 2009-01-22 Fujitsu Ten Ltd Package for electronic component, package component provided with the same, electronic device, and manufacturing method of package component
DE102020109493A1 (en) 2020-04-06 2021-10-07 Infineon Technologies Ag A SEMICONDUCTOR COMPONENT PACKAGE WITH TWO STACKED LEADFRAMES

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