JPS60107830A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60107830A JPS60107830A JP21662583A JP21662583A JPS60107830A JP S60107830 A JPS60107830 A JP S60107830A JP 21662583 A JP21662583 A JP 21662583A JP 21662583 A JP21662583 A JP 21662583A JP S60107830 A JPS60107830 A JP S60107830A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- ion implantation
- mask
- implantation layer
- metal material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000007769 metal material Substances 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract 3
- 239000002131 composite material Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 201000010099 disease Diseases 0.000 description 1
- 208000037265 diseases, disorders, signs and symptoms Diseases 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特にＣＭＱＳ半
導体装置のイオン注入層の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an ion implantation layer of a CMQS semiconductor device.
従来、ＣＭＯ８半導体装置のイオン注入層の形成方法は
、半得体基板表面に素子分離用絶縁膜を形成し、配線及
び電極用の多結晶シリコン層を成長、／＜ Ｊ −＝ン
グｌ ｐルリ訊スｈ’Ａ’ ｈＪ （Ｅ’ｌ ＋ハフ：
ｊｄｔｊ Ｂ６ｎ ？仝金属材料るいはホトレジスト
をマスクとしてイオン注入し、形成していた。Conventionally, the method for forming an ion implantation layer in a CMO8 semiconductor device is to form an insulating film for element isolation on the surface of a semiconductor substrate, grow a polycrystalline silicon layer for wiring and electrodes, sh'A' hJ (E'l + huff:
jdtj B6n? It is formed by ion implantation using a metal material or photoresist as a mask.
ところが、イオン注入にホトレジストをマスクとして使
用するよ場合は、ホトレジストから有機溶剤がイオン注
入による温度上昇によシでてきて、イオン注入機内の真
空度を恵くする為、イオン注入機の能力を大巾にダウン
させる問題があった。However, when a photoresist is used as a mask for ion implantation, organic solvent is released from the photoresist due to the temperature rise caused by ion implantation, and the performance of the ion implanter must be reduced in order to maintain a good vacuum inside the ion implanter. There was a problem with it being brought down to the hood.
また、金属材料をリスクとする場合は、貰方性のエツチ
ングをすると、エツチング後のオーバーエッチの間に、
下地にダメージを力えて、ＣＭＯ８の場合に規格が厳し
１７？電流のリークの原因となる為、等方性のエツチン
グ（エツチング液による）が実施されている。ところが
、等方性エツチングによシマスフをエツチングすると、
金属材料の膜、厚分だけ、ホトレジストのパターンより
（黄方同に金属羽村のエツチング液が広がってしまい、
パターンの微細化の防げとなっていた。また、金属材料
の膜厚を薄くすると、イオン注入の際に金属をイオンが
つき抜けて、イオン注入のマスクとしての機能を果せな
くなってしまう為、膜厚を薄くして、パターンの横方向
への広がシを防ぐこともできないでいた。In addition, if the metal material is a risk, if etching is performed with a high acceptability, during the over-etching after etching,
In the case of CMO8, the standard is stricter than 17, which can cause damage to the base. Isotropic etching (using an etching solution) is performed to prevent current leakage. However, when etching the stripe surface using isotropic etching,
Due to the thickness of the metal film, the etching solution of Metal Hamura spreads in the same direction as the photoresist pattern.
This prevented the pattern from becoming finer. In addition, if the film thickness of the metal material is made thin, the ions will penetrate through the metal during ion implantation and will no longer function as a mask for ion implantation. They were also unable to prevent the spread of the disease.
本発明は、かかるイオン注入層形成の際の問題を解決し
、金属材料の膜厚を薄くしないで、金属材料のエツチン
グ部の広がシを少なくシ、パターンの微細化を実現する
ことができる。イオン注入層の形成方法を提供するもの
である。The present invention solves such problems when forming an ion-implanted layer, reduces the spread of the etched portion of the metal material, and realizes a finer pattern without reducing the thickness of the metal material. . A method for forming an ion implantation layer is provided.
本発明によれば、イオン注入のマスクに金属材料を使用
し、Ｐ型あるいはＮ型のイオン注入層を形成する際に、
マスク金属材料のパターニングを異方性エツチングを実
施した後に等方性エツチングを実施して行なう。According to the present invention, when forming a P-type or N-type ion implantation layer using a metal material as an ion implantation mask,
The mask metal material is patterned by performing anisotropic etching and then isotropic etching.
この為に、異方性エツチングによシ横方向の広がシなく
金属材料をエツチングした後に、残ヤの膜厚を等方性エ
ツチングでエツチングすることによシ、横方向への広が
ｐが少なく、また、金属材料の膜厚を博くしなく −Ｃ
ｍ１ｌｌ良くなる。For this reason, after etching the metal material without spreading in the lateral direction by anisotropic etching, by etching the remaining film thickness by isotropic etching, it is possible to prevent the spread in the lateral direction. -C
m1ll gets better.
以下、図面を用いて本発明の実施例について説明する。Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明の実施例の金属材料をパターニングし
た後にイオン注入層を形成する工程の断面図である。第
２図は、本発明の詳細な説明する為の金属材料のパター
ンの断面図である。FIG. 1 is a cross-sectional view of a step of forming an ion implantation layer after patterning a metal material according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a pattern of metal material for explaining the present invention in detail.
第２図囚は、従来のパターニング形状、第２図（Ｂ）は
本発明のパターニング形状を示す図である。第１図半導
体基板１の表面に素子分離用絶縁膜２を形成し、配線４
、電極３を多結晶シリコン層を成長、パターニングし、
その上に金属材料５を付着させ、ホトレジストをパター
ニングし、そのホトレジストをマスクとして金属材料を
エツチングし、ホトレジストを剥離後、金属材料をマス
クとしてイオン注入して、Ｐ／型あるいはＮ型のイオン
注入層を形成する第２図（５）でホトレジスト６の開口
部７を通して、等方性エツチングを行なうと、金属材料
の膜厚χをエツチングする間に、横方向にχ＝ａなるａ
だけエツチングが進んでしまう。ところが、本発明の第
２図（Ｂ）は、異方性エツチングで開口部の直下の金属
材料をｙｃ＋願厚分だけエツチングする為、横方向へは
異方性エツチングの間は殆どエツチングが進まない。そ
の後に、金Ｊ（４何科Ｚの膜厚分だけ等方性エツチング
すると横方向へはｚ−ｂのｂだけエツチングが進む。こ
の局、従来の等方性エツチングだけの場合よりａ −ｂ
＝ ｃのＣだけ横方向へのエツチングが少なくて俗、
パターンの微細化が可能となる。また、異方性エツチン
グで直接素子面をエツチングすることがカいのでエツチ
ングによるダメージで電流リークが増加することも防ぐ
ことができる。FIG. 2(B) shows a conventional patterning shape, and FIG. 2(B) shows a patterning shape of the present invention. FIG. 1: An insulating film 2 for element isolation is formed on the surface of a semiconductor substrate 1, and wiring 4 is formed on the surface of a semiconductor substrate 1.
, growing and patterning a polycrystalline silicon layer for the electrode 3;
A metal material 5 is deposited thereon, the photoresist is patterned, the metal material is etched using the photoresist as a mask, and after the photoresist is peeled off, ions are implanted using the metal material as a mask to implant P/type or N type ions. When isotropically etching is performed through the opening 7 of the photoresist 6 in FIG.
The etching progresses accordingly. However, in FIG. 2(B) of the present invention, since the metal material directly under the opening is etched by yc+desired thickness by anisotropic etching, almost no etching progresses in the lateral direction during anisotropic etching. do not have. After that, if isotropic etching is performed by the film thickness of gold J (4 families Z), the etching progresses in the lateral direction by b of z-b.
= C of c has less etching in the lateral direction, so it is common.
It becomes possible to miniaturize the pattern. Furthermore, since it is advantageous to directly etch the element surface using anisotropic etching, it is possible to prevent an increase in current leakage due to damage caused by etching.
第１図は本発明の実施例の金属材料をパターニングした
後にイオン注入層を形成する工程の断面図、第２図（ｋ
）Ｉｔよ従来の金属材料パターニング形状、第２図（Ｂ
）は本発明の金属利料のパターニング形状を示す図であ
る。
尚、図において、
１・・・・・・半導体基板、２・・・・・・素子分離用
絶縁膜、３・・・・・・電極、４・・・・・・配線、５
・・・・・・マスク用金属材料、６・・・・・・ホトレ
ジスト、７・・・・・・ホトレジスト用口部、ｘ、ｙ、
ｚ・・・・・・金属材料の膜厚、ａｔ ｂｅＣ・・・・
・・金属材料のサイドエツチング量である。Figure 1 is a cross-sectional view of the process of forming an ion implantation layer after patterning a metal material according to an embodiment of the present invention, and Figure 2 (k
) It is conventional metal material patterning shape, Fig. 2 (B
) is a diagram showing the patterning shape of the metal alloy of the present invention. In the figure, 1... Semiconductor substrate, 2... Insulating film for element isolation, 3... Electrode, 4... Wiring, 5
...metal material for mask, 6...photoresist, 7...mouth for photoresist, x, y,
z...Film thickness of metal material, at beC...
...This is the amount of side etching of the metal material.
Claims (1)
Ｎ型のイオン注入層を形成する際に、マスク金属材料の
パターニングを異方性エツチングを実施した後に等方性
エツチングを実施して行なうことを特徴とする半導体装
置の製造方法。When using a metal material as an ion implantation mask and forming a P-type or N-type ion implantation layer, patterning the mask metal material by performing anisotropic etching followed by isotropic etching. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21662583A JPS60107830A (en) | 1983-11-17 | 1983-11-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21662583A JPS60107830A (en) | 1983-11-17 | 1983-11-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60107830A true JPS60107830A (en) | 1985-06-13 |
Family
ID=16691362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21662583A Pending JPS60107830A (en) | 1983-11-17 | 1983-11-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60107830A (en) |
-
1983
- 1983-11-17 JP JP21662583A patent/JPS60107830A/en active Pending
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