JPS6010769A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6010769A JPS6010769A JP58119271A JP11927183A JPS6010769A JP S6010769 A JPS6010769 A JP S6010769A JP 58119271 A JP58119271 A JP 58119271A JP 11927183 A JP11927183 A JP 11927183A JP S6010769 A JPS6010769 A JP S6010769A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- transistor
- conductivity type
- type
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 230000001133 acceleration Effects 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 abstract description 3
- 230000003213 activating effect Effects 0.000 abstract description 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 18
- 229910052796 boron Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- -1 arsenic ions Chemical class 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置及びその製造方法に係）、特１ｃＩ
、−トチャネルに適した相補形ＭＩＳ ＩＣ（以下では
代表的なＭＯＳ ＩＣで説明する）の構造及びその製造
方法に関する。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a semiconductor device and its manufacturing method), especially 1cI
The present invention relates to the structure of a complementary MIS IC (described below with reference to a typical MOS IC) suitable for a MOS channel, and a method for manufacturing the same.
（ｂ） 従来技術と問題点
相補形ＭＯ８、ＩＣ（以下ＣＭＯ８と称す）にはｐ型半
導体基板上にｎチャネルＭＯ８）ランジスタを形成しｎ
ウェル上にｐチャネルＭＯ８）ランジスタを形成する構
造と、ｎ型半導体基板上にｐチャネルＭＯＳトランジス
タを形成しｐウェル上にｎチャネルＭＯ８）ランジスタ
を形成する構造とがあるが、いずれの構造に於ても該Ｃ
ＭＯ８に配設されるトランジスタをショートチャネル化
しようとする場合、比較的不純物濃度の高いウェル側に
はショートチャネル・トランジスタを形成し易いが、不
純物濃度の低い基板側にはショートチャネル・トランジ
スタが形成しにくいという問題がある。これは不純物濃
度の低い基板側でパンチスルー現象によるソース、ドレ
イン間耐圧の劣化が起るためである。この問題は基板の
不純物濃度を高めることによって解決できるが、この場
合基板側に形成される総てのトランジスタの接合容量が
増加すること、該基板の不純物をコンペンセートして形
成されるウェルの総不純物量が増し該ウェルに於けるキ
ャリアの易動度が小さくなａ等によシ該ＩＣの動作速度
が低下するという問題を生ずる０
そこで従来はツインタブと呼ばれる構造が用いられてい
た。これは両導電型のウェルを形成し、それぞれのウェ
ル上にウェルと逆導電のチャネルを有するショートチャ
ネルＭＯ８）ランジスタを形成するものである。第１図
はその一例の要部を示したもので、図中１はｐ−型シリ
コン（Ｓｔ）半導体左：板、２はｎウェル、３はｐウェ
ル、４１叶フイールド酸化膜、５けｎ十型チャネルカッ
ト領域、６はｐ生型チャネルカッ） ９Ｍ域、７はゲー
ト酸化膜、８はゲート電極、９ａ、９ｂはｐ十型ソース
、ドレイン領域、１０ａ、１０ｂはｎ生型ソース、ドレ
イン領域、ｐ−ｃｈはｐチャネルＭＯ８）ランジスタ、
ｎ−ｃｈはｎチャネルＭＯ８）ランジスタを示している
０
しかし該ツインタブ構造に於ては、基板と同導Ｎ、型の
ウェル（上記例に於てはｐウェル３）を形成する際に余
分な高温ランニング処理のために製造設備の消耗が増す
という問題や、該ウェル（上記例に於てはｐウェル３）
内に形成されるｎチャネル・トランジスタの接合容量が
基板上に形成される場合よシも増し、その動作速度が低
下すると １いう問題があった。(b) Prior art and problems Complementary MO8, IC (hereinafter referred to as CMO8) has an n-channel MO8) transistor formed on a p-type semiconductor substrate.
There is a structure in which a p-channel MO8) transistor is formed on the well, and a structure in which a p-channel MOS transistor is formed on an n-type semiconductor substrate and an n-channel MO8) transistor is formed on the p-well. Even if the C
When trying to short-channel the transistor arranged in MO8, it is easy to form a short-channel transistor on the well side where the impurity concentration is relatively high, but it is easy to form a short-channel transistor on the substrate side where the impurity concentration is low. The problem is that it is difficult to do. This is because the breakdown voltage between the source and drain deteriorates due to the punch-through phenomenon on the substrate side where the impurity concentration is low. This problem can be solved by increasing the impurity concentration of the substrate, but in this case, the junction capacitance of all transistors formed on the substrate side increases, and the total amount of wells formed by compensating for the impurities in the substrate increases. As the amount of impurities increases and the mobility of carriers in the well decreases, a problem arises in that the operating speed of the IC decreases.Therefore, a structure called a twin tub has conventionally been used. In this method, wells of both conductivity types are formed, and a short channel MO8) transistor having a channel of conductivity opposite to that of the well is formed on each well. Figure 1 shows the main parts of an example. In the figure, 1 is a p-type silicon (St) semiconductor left: plate, 2 is an n-well, 3 is a p-well, 41 is a field oxide film, and 5 is a n-type semiconductor. 9M region, 7 is gate oxide film, 8 is gate electrode, 9a and 9b are p-type source and drain regions, 10a and 10b are n-type source and drain area, p-ch is a p-channel MO8) transistor,
n-ch indicates an n-channel MO8) transistor 0 However, in this twin-tub structure, when forming a well of the same conductivity as the substrate (p-well 3 in the above example), There is the problem of increased wear and tear on manufacturing equipment due to high-temperature running processing, and the problem that the well (p-well 3 in the above example)
There is a problem in that the junction capacitance of the n-channel transistor formed inside the device increases compared to when it is formed on the substrate, and its operation speed decreases.
（Ｃ）発明の目的
本発明は上記問題点に鑑み、高温ラン二ングエ３−
程を増やさず、しかも接合容量を増大せしめ千に’／
ｗ−トチャネル化した際のソース、ドレイン間耐圧の劣
化を防止する０ＭＯ８構造及びその製造方法を提供する
ものである。(C) Purpose of the Invention In view of the above-mentioned problems, the present invention is designed to increase the junction capacity without increasing the amount of high-temperature running energy.
The present invention provides an OMO8 structure that prevents deterioration of breakdown voltage between the source and drain when it is made into a w-channel, and a method for manufacturing the same.
（ｄ） 発明の構成
即ち本発明は、−導電型半導体基板上に逆導電型チャネ
ルを有する第１のＭＩＳ）ランジスタが配設され、該半
導体基板に設けられた逆導電型ウェル上に一導電型チャ
ネルを有する第２のＭＩＳトランジスタが配設されてな
シ、該第１のＭＩＳトランジスタのゲート電極直下部及
びその近傍の該半導体基板に選択的に、該半導体基板よ
υ高不純物濃度を有し、且つソース、ドレイン領域よシ
深い一導電型領域が設けられてなることを特徴とする半
導体装置、及び−導電型半導体基板に高温ランニングに
よシ選択的に逆導電型ウェルを形成し、該半導体基板の
該基板上に配設されるＭＩＳトランジスタのゲート電極
の直下にあたる領域及びその近傍に選択的に、高加速電
圧によるイオン注入によシ該基板より高不純物濃度で、
且つ該ト４−
ランジスタのソース、ドレインよシも關い一導電型領域
を形成し、しかる後該−導電型半導体基板上に、前記−
導電型領域上にゲート電極が位置する逆導電型チャネル
１■ＩＳ）ランジスタを、又該逆導電型ウェル上に一導
電型チャネルＭ工Ｓトランジスタを形成する工程を有す
ることを特徴とする半導体装置の製造方法に関するもの
である。(d) Structure of the Invention, that is, the present invention is such that a first MIS transistor having an opposite conductivity type channel is disposed on a -conductivity type semiconductor substrate, and one conductivity type transistor is disposed on an opposite conductivity type well provided in the semiconductor substrate. If a second MIS transistor having a type channel is not disposed, the semiconductor substrate directly below the gate electrode of the first MIS transistor and in the vicinity thereof is selectively treated with an impurity concentration higher than that of the semiconductor substrate. and a semiconductor device characterized in that a region of one conductivity type is provided deeper than the source and drain regions, and - a well of an opposite conductivity type is selectively formed in a conductivity type semiconductor substrate by high temperature running, A region of the semiconductor substrate immediately below the gate electrode of the MIS transistor disposed on the substrate and its vicinity is selectively implanted with ions at a high acceleration voltage, with a higher impurity concentration than the substrate.
In addition, one conductivity type region is formed on the source and drain of the transistor, and then the - conductivity type semiconductor substrate is formed.
A semiconductor device comprising a step of forming an opposite conductivity type channel transistor (IS) with a gate electrode located on a conductivity type region, and a one conductivity type channel M transistor on the opposite conductivity type well. The present invention relates to a manufacturing method.
（ｅ） 発明の実施例 以下、不発明を実施例について図を用いて説明する。(e) Examples of the invention Hereinafter, the non-invention will be described with reference to the drawings with regard to embodiments.
第２図及び第３図は本発明の半導体装置に於けの工程断
面図である。FIGS. 2 and 3 are cross-sectional views of steps in the semiconductor device of the present invention.
ｐ型シリコン（Ｓｉ ）半導体基板を用いて形成された
本発明のＣＭＯ８は、例えば第２図に示すような構造を
有してなっている。同図に於て、１１はｐ−型Ｓｉ基板
、１２はｎウェル、１３はｎ生型チャネル・カット領域
、１４はｐ生型チャネル・カット領域、１５はフィール
ド酸化膜、１６はｐ型領域、１７はゲート酸化膜、１８
ａ、１．８ｂはゲート電極、１９ａ、１９ｂはｐ生型ソ
ース、ドレイン領域、２０ａ。The CMO 8 of the present invention formed using a p-type silicon (Si) semiconductor substrate has a structure as shown in FIG. 2, for example. In the figure, 11 is a p-type Si substrate, 12 is an n-well, 13 is an n-type channel cut region, 14 is a p-type channel cut region, 15 is a field oxide film, and 16 is a p-type region. , 17 is a gate oxide film, 18
a, 1.8b are gate electrodes, 19a, 19b are p-type source and drain regions, and 20a.
２０ｂはｎ生型ソース、ドレイン領域、ｐ−ｃｈはｐチ
ャネルＭＯ８）ランジスタ、ｎ−ｃｈはｎチャネルＭＯ
Ｓ）ランジスタを示している。20b is an n-type source and drain region, p-ch is a p-channel MO8) transistor, and n-ch is an n-channel MO
S) Shows a transistor.
該本発明の構造に於て基板と同導電型のチャネルを有す
るＭＯＳトランジスタは基板からの分離を完全にするた
めに従来同様深い逆導電型ウェルに形成される。即ち上
記実施例に於て基板と同導電型のｎチャネルを有するト
ランジスタ（ｐ−ｃｈ）は基板濃度全コンペンセートし
て形成された比較的高不純物濃度のｎウェルに形成され
る。従って該ｐ−ｃｈに於てソース、ドレイン領域１９
ａ、１９ｂ間に電圧が印加された際のウェル内への空乏
層の延びは小さく、パンチスルー現象によるソース。In the structure of the present invention, a MOS transistor having a channel of the same conductivity type as the substrate is formed in a deep opposite conductivity type well, as in the prior art, in order to completely isolate it from the substrate. That is, in the above embodiment, a transistor (p-ch) having an n-channel of the same conductivity type as the substrate is formed in an n-well having a relatively high impurity concentration, which is formed by compensating the entire substrate concentration. Therefore, in the p-ch, the source and drain regions 19
When a voltage is applied between a and 19b, the extension of the depletion layer into the well is small, resulting in a punch-through phenomenon.
ドレイン間耐圧の劣化は起きにくい。そして本発明の構
造に於ては同図に示すようにｐ−＾ＩＪ Ｓ ｉ基板１
１上に形成される基板と逆導電型チャネルを有するＭＯ
Ｓ）ランジスタ即ちｎチャネル・トランジスタ（ｎ−ａ
ｈ）のゲート電極１８ｂの直下部及びその近傍即ちｎ（
−ｉ１１ソース、ドレイン領域２０ａと２０ｂの間に選
択的に該ソース、ドレイン領域２０ａ、 ２０ｂより深
く、且つ基板より高不純物誹度のｐ型領域１６が設けら
力、る。そして該ｐ型領域１６によシルー型基板１１側
に形成されるトランジスタ（ｎ−ｃｈ）のｎ生型ソース
、ドレイン領域２０ａ、２Ｏｂ間の空乏層の伸びは小さ
く抑えられ、従って該トランジスタ（ｎ−ａｈ）がショ
ートチャネル化された際のパンチスルー現象によるソー
ス、ドレイン間耐圧の劣化が防止される。又該ｐ型領域
１６はソース。Deterioration of drain-to-drain breakdown voltage is unlikely to occur. In the structure of the present invention, as shown in the same figure, the p-^IJ Si substrate 1
MO having a substrate formed on 1 and a channel of opposite conductivity type.
S) transistor or n-channel transistor (n-a
h) directly below the gate electrode 18b and its vicinity, i.e. n(
-i11 A p-type region 16 is selectively provided between the source and drain regions 20a and 20b, which is deeper than the source and drain regions 20a and 20b and has a higher impurity concentration than the substrate. The p-type region 16 suppresses the extension of the depletion layer between the n-type source and drain regions 20a and 2Ob of the transistor (n-ch) formed on the side of the transparent substrate 11 to a small extent. -ah) is prevented from deteriorating the withstand voltage between the source and drain due to the punch-through phenomenon when the transistor is short-channeled. Further, the p-type region 16 is a source.
ドレイン領域２０ａ、２０ｂの全域を覆うように形成さ
れず、前記のようにゲート電極１８ｂ直下部及びその近
傍にのみ選択的に形成されるので、ソース。The source is not formed so as to cover the entire area of the drain regions 20a and 20b, but is selectively formed only directly under and in the vicinity of the gate electrode 18b as described above.
ドレイン領域２０ａ、２０ｂの接合容量は従来のツイン
タブに比して充分に小さく（低濃度基板に直に形成され
る場合に近い値）抑えられ、該トランジスタ（ｎ−ｃｈ
）の動作速度は向上する。The junction capacitance of the drain regions 20a and 20b is suppressed to a sufficiently small value (close to the value when formed directly on a low concentration substrate) compared to the conventional twin tub, and the transistor (n-ch
) operation speed will be improved.
暑
第３図は上記と逆の即ちｎ−型基板を用いた場合の一実
施例を示したもので、２１はｎ−型Ｓｔ基板、２２はｐ
ウェル、１３はｎ＋型チャネル・カット領７−
域、１４はｐ型チャネル・カット領域、】５けフィール
ド酸化膜、２３はｎ型領域、１７はゲート酸化膜、１８
ａ、 １８ｂはゲート電極、１９ａ、 １９ｂはｐ＋型
ソース、ドレイン領域、２０ａ、２０ｂはｎ＋ｍソース
、ドレイン領域、ｐ−ｃｈはｎチャネルＭＯＳトランジ
スタ、ｎ−ｃｈはｎチャネルＭＯＳ）ランジスタを示し
ている。そして該構造に於ては、基板側に形成されるｐ
−ｃｈ）ランジスタがショートチャネル化された際、前
記実施例同様の理由によ’） ｐ”Ｗ、ソース、ドレイ
ン領域１９ａ、１９ｂ間の耐圧劣化は防止され、且つ該
ｐ生型ソース、ドレイン領域１９ａ、１９ｂの接合容量
が抑えられるので動作速度の向上が図れる。Figure 3 shows an example in which an n-type substrate is used, which is the opposite of the above, 21 is an n-type St substrate, and 22 is a p-type substrate.
Well, 13 is an n+ type channel cut region, 14 is a p type channel cut region, ]5 is a field oxide film, 23 is an n type region, 17 is a gate oxide film, 18
a and 18b are gate electrodes, 19a and 19b are p+ type source and drain regions, 20a and 20b are n+m source and drain regions, p-ch is an n-channel MOS transistor, and n-ch is an n-channel MOS) transistor. . In this structure, p formed on the substrate side
-ch) When the transistor is made into a short channel, for the same reason as in the above embodiment, breakdown voltage deterioration between the p''W, source and drain regions 19a and 19b is prevented, and the p-type source and drain regions are Since the junction capacitance between 19a and 19b is suppressed, the operating speed can be improved.
以下、本発明の構造を有する０ＭＯ８の製造方法を、ｐ
型基板を用いて形成する場合の一例について、第４図を
参照して説明する。Hereinafter, a method for manufacturing 0MO8 having the structure of the present invention will be described.
An example of forming using a mold substrate will be described with reference to FIG. 4.
第４図（イ）参照
ｐ−型Ｓｉ基板１１上にイオン注入に際してのダメージ
を防止する機能を持つ薄い酸化膜３１ａを形成し、該薄
い酸化膜３１ａ上に通常の化学気相成琵二８−
フすトリソゲラフイエ程を経てトランジスタ形成領域３
２ａ、 ３２ｂを覆う耐酸化膜パターン例えば９化シリ
コン（ＳｔｓＮ４）膜パターン３３ａ、 ３３ｂを形成
し、該基板上に、ウェル形成碩域上にイオン注入窓３４
を有する第１のレジストマスク膜３５を形成し、該イオ
ン注入窓３４からＳｉ８Ｎ４膜パターン３２ａを通して
ｐ−型Ｓｔ基板１１面にシん（Ｐ＋）を所定ドーズ量で
イオン注入する。（Ｐ＋はシんイオン、Ｐ＋ｉａはシん
イオン注入領域を示す）第４図←）参照
次いで第１のレジストマスク膜３５を除去し、１２００
［ｔｌ］程度の所定の高温ランニング処理を施して所定
深さのｎウェル１２を形成する。Refer to FIG. 4(a), a thin oxide film 31a having a function of preventing damage during ion implantation is formed on the p-type Si substrate 11, and a normal chemical vapor deposition process is performed on the thin oxide film 31a. - Transistor formation region 3 after the fusutrisogera layering process
An oxidation-resistant film pattern 33a, 33b, for example, silicon 9ide (StsN4) film pattern 33a, 33b is formed to cover the substrate 2a, 32b, and an ion implantation window 34 is formed on the well formation area on the substrate.
A first resist mask film 35 is formed, and ions of phosphorus (P+) are implanted at a predetermined dose into the surface of the p- type St substrate 11 from the ion implantation window 34 through the Si8N4 film pattern 32a. (P+ indicates a thin ion implantation region, P+ia indicates a strong ion implantation region) Refer to FIG. 4 ←) Next, the first resist mask film 35 is removed, and
A predetermined high temperature running process of approximately [tl] is performed to form an n-well 12 of a predetermined depth.
第４図（ハ）参照
次いで該基板上にｎウェル１２の上部領域を表出するイ
オン注入窓を有する第２のレジストマスク膜３６を形成
し、該第２のレジストマスク膜３６及び５ｉＢＮ４膜パ
ターン３３ａをマスクにし、薄い酸化膜３１ａを通して
ｎウェル表面に選択的にひ素（Ａｓ＋）を高濃度にイオ
ン注入する。（Ａｓはひ素イオン、Ａｓ；ａはひ素イオ
ン注入頌域を示す）第４図に）参照
次いで第２のレジストマスク膜３６を除去して後ｎウェ
ル１２上を選択的に第３のレジストマスク膜３７で覆い
、該第３のレジストマスク膜３７及びＳ ｉ Ｂ Ｎ４
膜パターン３３ｂをマスクにし、薄い酸化膜３１を通し
てｐ−型基板１１面に選択的に硼素（Ｂ＋）を高濃度に
イオン注入する。（Ｂ＋は硼素イオンＢＩｍは硼素イオ
ン注入領域を示す）第４図（ホ）参照
次いで第３のレジストマスク膜３７を除去して後５１ｓ
Ｎａ膜パターン３３ａ及び３３ｂをマスクにしＳｉ面を
選択的に熱酸化し素子間を分離するフィールド酸化膜１
５を形成する。（通常の選択酸化法）
なお、この際前記ひ素注入領域Ａ’ｓｌ、及び硼素注入
領域昭、は活性化再分布し、フィールド酸化膜１５の下
部にｎ十型チャネルカット領域１３及びｐ＋型チャネル
カット領域１４が形成される。Referring to FIG. 4(c), a second resist mask film 36 having an ion implantation window exposing the upper region of the n-well 12 is then formed on the substrate, and a pattern of the second resist mask film 36 and the 5iBN4 film is formed. Using 33a as a mask, ions of arsenic (As+) are selectively implanted at a high concentration into the n-well surface through the thin oxide film 31a. (As stands for arsenic ions, As; a stands for arsenic ion implantation area) (see FIG. 4) Next, after removing the second resist mask film 36, a third resist mask is selectively applied over the n-well 12. covered with a film 37, and the third resist mask film 37 and S i B N4
Using the film pattern 33b as a mask, boron (B+) ions are selectively implanted at a high concentration into the surface of the p- type substrate 11 through the thin oxide film 31. (B+ indicates a boron ion implantation region BIm indicates a boron ion implantation region) Refer to FIG. 4(E) Next, 51 seconds after removing the third resist mask film 37
Field oxide film 1 is selectively thermally oxidized on the Si surface using the Na film patterns 33a and 33b as a mask to isolate the elements.
form 5. (Ordinary selective oxidation method) At this time, the arsenic implanted region A'sl and the boron implanted region A'sl are activated and redistributed, and an n+ type channel cut region 13 and a p+ type channel are formed under the field oxide film 15. A cut area 14 is formed.
なお、以上は通常行われるＣＭＯ８基板の形成方法に準
じて行われる。Note that the above steps are performed in accordance with a commonly used method for forming a CMO8 substrate.
第４図（へ）参照
次いで本発明の方法て於ては、前記Ｓｉ、Ｎ、膜パター
ン３３ａ、３３ｂおよび薄い酸化膜３１ａを除去した後
ゲート酸化膜１７を成長し、次いで該基板上をｐ−型Ｓ
ｔ基板１１上に形成されるｎ−ｃｈ）ランジスタのゲー
ト電極が配設される領域に該ゲート電極よシ僅かに大き
めのイオン注入窓３８を有する第４のレジストマスク膜
３９で覆い、該イオン注入窓３８７５＼らゲート酸化膜
１７を通して選択的に硼素Ｂ＋を高加速電圧でイオン注
入し、該基板面にバンチスルーを防止し得るような所定
の濃度を有し、且つソース、ドレイン領域よυ深い硼素
注入領域Ｂ４ｒ、ｆ形成する０
第４図（ト）参照
次いで該領域を活性化させてｐ型領域１６とす、６．
＆：Ｔｈ・ＣＯ？ｉ′″性“１１１稜１程ＫＰ？ ７−
ｘ、 ］ドレイン領域を活性化する際同時に行っても
良い。Referring to FIG. 4(f), in the method of the present invention, after removing the Si, N, film patterns 33a, 33b and thin oxide film 31a, a gate oxide film 17 is grown, and then a p-oxide film is grown on the substrate. -Type S
The region where the gate electrode of the n-ch transistor formed on the T substrate 11 is disposed is covered with a fourth resist mask film 39 having an ion implantation window 38 slightly larger than the gate electrode, and the ion implantation window 38 is covered with a fourth resist mask film 39. Boron B+ is ion-implanted selectively at a high acceleration voltage through the gate oxide film 17 through the implantation window 3875\, and has a predetermined concentration that can prevent bunch-through on the substrate surface, and υ from the source and drain regions. 6. Form deep boron implanted regions B4r and f. See FIG. 4(g). Then activate the regions to form p-type regions 16.
&: Th・CO? i'″ sex “111 ridge 1 KP? 7-
x, ] may be performed simultaneously when activating the drain region.
以後、通常のＣＭＯ８の製造方法に従う。Thereafter, the usual method for manufacturing CMO8 is followed.
第４図（ト）参照 ゛
１１−
次いで通常のＣＶＤ工程及びフォトリソグラフィ工程を
経て該ゲート酸化膜１７上に多結晶Ｓｉ等よυなるゲー
ト電極１８ａ、１８ｂを形成し、次いで核基板上に例え
ば先ずｎ−ｃｈ）ランジスタ形成領域３９ｂを表出する
窓を有する第５のレジストマスク膜４０を形成し、該レ
ジストマスク膜４０゜フィールド酸化膜１５及びゲート
電極１８ｂをマスクにし、ゲート酸化膜１７を通して前
記ｐ型領域１６の縁部を含むｐ−型基板１１面に選択的
に高ドーズ量でひ素（Ａ Ｂ＋）を所定の深さにイオン
注入する。（Ａｓ’ｉ、はひ素イオン注入領域）第４図
（男参照
次いで第５のレジストマスク膜４０を除去した後、ゲー
ト電極１８ａ、１８ｂの外に表出しているゲート酸化膜
１７を除去し、次いで再び該領域面に後に形成するＰＳ
Ｇ絶縁膜からのりんの拡散を阻止するための薄い酸化膜
３１ｂを形成し、次いで該基板上にｎ−ａｈ）ランジス
タ形成領域３９ａを表出する窓を有する第６のレジスト
マスク膜４１を形成し、該レジスト膜４１ｐフイールド
酸化膜１５１２−
及びゲート電極１８ａをマスクにし、薄い酸化膜３Ｔ。Refer to FIG. 4(g). ゛11- Next, gate electrodes 18a and 18b made of polycrystalline Si or the like are formed on the gate oxide film 17 through a normal CVD process and a photolithography process, and then, for example, gate electrodes 18b are formed on the nuclear substrate. First, a fifth resist mask film 40 having a window exposing the n-ch) transistor formation region 39b is formed, and the resist mask film 40 is exposed through the gate oxide film 17 using the field oxide film 15 and the gate electrode 18b as a mask. Arsenic (AB+) ions are selectively implanted at a high dose into the surface of the p- type substrate 11 including the edge of the p-type region 16 to a predetermined depth. (As'i means arsenic ion implantation region) FIG. 4 (See Figure 4) Next, after removing the fifth resist mask film 40, the gate oxide film 17 exposed outside the gate electrodes 18a and 18b is removed. Next, PS to be formed later on the area surface again.
A thin oxide film 31b is formed to prevent diffusion of phosphorus from the G insulating film, and then a sixth resist mask film 41 having a window exposing the n-ah) transistor formation region 39a is formed on the substrate. Then, using the resist film 41p field oxide film 1512- and the gate electrode 18a as a mask, a thin oxide film 3T is formed.
を通してｎウェル１２面に選択的に硼素（Ｂ＋ｆ高濃度
に且つ所定の深さにイオン注入する。０六、は硼素イオ
ン注入領域）
第４図し）参照
次いで第６のレジストマスク膜４１を除去した後、所定
のアニール処理を施して、前記硼素イオン注入領域ＣＢ
＋１．）及びひ素イオン注入領域（Ａｓ’ｉａ）を活性
化再分布せしめ、ｎウェル１２面にｐ＋型ソース、ドレ
イン領域１９ａ、１９ｂを、又ｐ−型基板１１面にゲー
ト側端部が前記ｐ型領域１６内に僅かに入り込んだｎ十
型ソース、ドレイン領域２０ａ、 ２０ｂを形成する。Boron (B+f) ions are selectively implanted into the n-well 12 surface at a high concentration and at a predetermined depth. 06 indicates the boron ion implantation region (see Fig. 4). Then, the sixth resist mask film 41 is removed. After that, a predetermined annealing process is performed to form the boron ion implanted region CB.
+1. ) and arsenic ion-implanted regions (As'ia) are activated and redistributed, p+ type source and drain regions 19a and 19b are formed on the n-well 12 surface, and gate side end portions are formed on the p- type substrate 11 surface. N10 type source and drain regions 20a and 20b slightly extending into the region 16 are formed.
次いで図示しないが、絶縁膜の形成、電極コンタクト窓
の形成、配線形成等がなされて０ＭＯ８ＩＣが完成する
。Although not shown, an insulating film, an electrode contact window, wiring, etc. are then formed to complete the 0MO8 IC.
ここで本発明のＣＭＯ８構造をｐ−型基板を用いて形成
した際の一数値例を述べると、ｐ−型Ｓ１基板１１の不
純物濃度６．５Ｘ １０１４（ａｔｍ／ｃｒｉｔ） ＃
ｎウェル１２の不純物濃度１０１’（ａ憧Ｖｃｒ／ｌ
） 、深さａ Ｃ””）ｔゲート酸化膜１７の厚さ３ｓ
ｏｒＡ’＋、ｐ型領域１６の不純物濃度１０ ）’ （
ａｔｍ／ｃｌ ’ｌ ＊深さ０．７（μｍ）。Here, an example of numerical values when the CMO8 structure of the present invention is formed using a p-type substrate is as follows: The impurity concentration of the p-type S1 substrate 11 is 6.5X 1014 (atm/crit) #
Impurity concentration 101' of n-well 12 (aVcr/l
), depth a C””)t Thickness of gate oxide film 17 3s
orA'+, impurity concentration of p-type region 16 10 )' (
atm/cl'l *depth 0.7 (μm).
ソース、ドレイン領域１９ａ、１９ｂの深さ０．６ｒ
ｐ ｍ ’Ｊ２０ａ、 ２０ｂの深さく１３（μｍ）、
ｎ−Ｃｈ ）ランジスタチャネル畏１．７〔μｍ）、
ｐ−ｃｈトランジスタチャネル長２．２〔μｍ〕であシ
、これによって得られたｎ−ｃｈ）ランジスタの閾値電
圧ｏ、７［Ｖ）、ソース、ドレイン間耐圧１４〔ｖ〕で
、ｐ−ｃｈ）ランジスタの閾値電圧−０，８［Ｖ］、ソ
ース、ドレイン間耐圧−１５（Ｖ）であった。そしてこ
の結果は、基板と逆導電型チャネルを有するＭＯＳ）ラ
ンジスタのソース、ドレイン耐圧が、低濃度基板を使用
した従来法（要求閾値電圧に従って基板表面近傍のみを
高濃度とし次男法）では、チャネル長１．７〔μｍ〕程
度においてはすヘテハンチスルー現象を示していたもの
が、本方法に於ては接合のブレークダウンを示す寸で完
全に耐圧を保証できることを示している０又基板と逆チ
ャネルを有するＭＯＳ）ランジスタの接合容量が従来の
ツインタブ方式に比べて１７ａ程度に減少することを示
している。Depth of source and drain regions 19a and 19b: 0.6r
p m 'J20a, 20b depth 13 (μm),
n-Ch) transistor channel size 1.7 [μm],
The p-ch transistor channel length is 2.2 [μm], the threshold voltage o of the resulting n-ch transistor is 7 [V], the source-drain breakdown voltage is 14 [V], and the p-ch ) The threshold voltage of the transistor was -0.8 [V], and the breakdown voltage between the source and drain was -15 (V). This result shows that the source and drain breakdown voltage of a MOS transistor (MOS) transistor with a channel of conductivity type opposite to that of the substrate is lower than that of the channel in the conventional method using a lightly doped substrate (Tsugi's method in which only the near substrate surface is highly doped according to the required threshold voltage). In the case of a length of about 1.7 [μm], the phenomenon of uneven haunch-through was exhibited, but with this method, it is possible to completely guarantee withstand voltage at the point where the breakdown of the junction occurs. This shows that the junction capacitance of a MOS) transistor having a MOS transistor is reduced to about 17a compared to the conventional twin-tub type.
そして父上記製造方法例から明らかなように、本発明に
於ては基板と逆チャネルを有するＭＯＳトランジスタの
ソース、ドレイン耐圧を高めるための不純物導入領域（
実施例に於てはｐ型領埴６）がイオン注入及び該注入領
域の活性化処理によっ分の高温ランニング工程を省くこ
とができる。As is clear from the above manufacturing method example, in the present invention, impurity-introduced regions (
In this embodiment, the p-type region 6) is ion-implanted and the implanted region is activated, thereby eliminating a high-temperature running step.
なお、本発明はｎ−型基板を用いて０ＭＯ８を形成する
際にも勿論適用され、又ＭＯＳ以外のＭＩＳ構造にも適
用できる。Note that the present invention can of course be applied to forming an 0MO8 using an n-type substrate, and can also be applied to MIS structures other than MOS.
（ｆ） 発明の詳細
な説明したように本発明によれば高温ランニング工程を
ふやすことなく、接合容量を抑え、且つソース、ドレイ
ン間耐圧の劣化を防止した０ＭＯ８ＩＣのショートチャ
ネル化、高速化に対して極めて有効である。 、）(f) As described in detail, according to the present invention, it is possible to reduce the junction capacitance and prevent deterioration of the breakdown voltage between the source and drain without increasing the high temperature running process, and to shorten the channel and increase the speed of the 0MO8IC. It is extremely effective. ,)
第１図は従来の０ＭＯ８構造の要部断面図、第２図及び
第３図は本発明の半導体装置に於ける異な１５−
る実施例の要部断面図で、第４図（−１）乃至（功は本
発明の製造方法に於ける一実施例の工程断面図でちる０
図に於て、１１けｐ−型シリコン基板、１２はｎウェル
、１５はフィールド酸化膜、１６はｐ型領域、１７はゲ
ート酸化膜、１８ａ、１８ｂはゲート電接、１９ａ、１
９ｂはｐ生型ソース、ドレイン領域、２ｏａ２０ｂはｎ
生型ソース、ドレイン領域、２１はｎ−型シリコン基板
、２２はｐウェル、２３はｎ型領壊３１ａ、 ３１ｂは
薄い酸化膜、３２ａ、 ３２ｂはトランジスタ形成領域
、３３ａ、３３ｂは窒化シリコン膜パターン、３５，３
６，３７，３９，４０．４１はレジストマスク膜、針は
シんイオン、Ｂ＋は硼素イオン、Ａｓ＋はひ素イオン、
ＰＨ＠ ｅ Ｂｌａ ｔ Ａｓｌ、は各イオンの注入領
域、ｎ−ｃｈはｎチャネルＭＯＳ）ランジスタ、ｐ−ｃ
ｈはｐチャネルＭＯ８）ランジスタを示す〇１６−FIG. 1 is a sectional view of a main part of a conventional 0MO8 structure, FIGS. 2 and 3 are sectional views of main parts of different embodiments of the semiconductor device of the present invention, and FIG. (0) In the figure, 11 is a p-type silicon substrate, 12 is an n-well, 15 is a field oxide film, and 16 is a p-type silicon substrate. 17 is a gate oxide film, 18a and 18b are gate electrical contacts, 19a and 1
9b is p raw source and drain region, 2oa20b is n
Raw source and drain regions, 21 is an n-type silicon substrate, 22 is a p-well, 23 is an n-type region 31a, 31b is a thin oxide film, 32a and 32b are transistor formation regions, 33a and 33b are silicon nitride film patterns ,35,3
6, 37, 39, 40. 41 are resist mask films, needles are ions, B+ is boron ions, As+ is arsenic ions,
PH@e Blat Asl is the implantation region of each ion, n-ch is n-channel MOS) transistor, p-c
h indicates p-channel MO8) transistor 〇16-
Claims (1)
第１のＭＩＳ）ランジスタが配設され、該半導体基板に
設けられた逆導電型フェル上に一導電型チャネルを有す
る第２のＭＩＳ）ランジスタが配設されてなシ、該第１
のＭＩＳトランジスタのゲート電極直下部及びその近傍
の該半導体基板に選択的に、該半導体基板よシ高不純物
濃度を有艮 し、ハつソース、ドレイン領域よシ深い一導電型領域が
設けられてなることを特徴とする半導体装置０ ２、−導電型半導体基板に高温ランニングによシ選択的
に逆導電型ウェルを形成し、該半導体基板の該基板上に
配設されるＭＩＳ）ランジスタのゲート電極の直下にあ
たる領域及びその近傍に選択的に、高加速′底圧による
イオン注入によシ該基板よシ高不純物濃度で、且つ該ト
ランジスタのソース、ドレイン領域よシも深い一導電型
領域を形成し、しかる後膣−導電型半導体基板上に、前
記−導電型領域上にゲート電極が位置する逆導電型チャ
ネルＭＩＳ）ランジスタを、又該逆導電型ウェル上に一
導電型チャネルＭＩＳ）ランジスタを形成する工程を有
することを特徴とする半導体装置の製造方法。[Claims] 1.-A first MIS transistor having an opposite conductivity type channel is disposed on a conductivity type semiconductor substrate, and one conductivity type channel is provided on an opposite conductivity type fell provided on the semiconductor substrate. If the first MIS transistor is not disposed, the first
A region of one conductivity type, which has a higher impurity concentration than the semiconductor substrate and is deeper than the source and drain regions, is selectively provided in the semiconductor substrate immediately below the gate electrode of the MIS transistor and in the vicinity thereof. Semiconductor device 02, - A gate of an MIS transistor disposed on the semiconductor substrate, in which a reverse conductivity type well is selectively formed in a conductivity type semiconductor substrate by high-temperature running. A region of one conductivity type is selectively implanted into the region directly under the electrode and its vicinity by ion implantation using high acceleration and bottom pressure, and the impurity concentration is higher than that of the substrate and deeper than the source and drain regions of the transistor. After that, an opposite conductivity type channel MIS) transistor having a gate electrode located on the conductivity type region is formed on the conductivity type semiconductor substrate, and a one conductivity type channel MIS) transistor is formed on the opposite conductivity type well. 1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119271A JPS6010769A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119271A JPS6010769A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010769A true JPS6010769A (en) | 1985-01-19 |
| JPH0343787B2 JPH0343787B2 (en) | 1991-07-03 |
Family
ID=14757225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119271A Granted JPS6010769A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010769A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5994731A (en) * | 1996-07-19 | 1999-11-30 | Nec Corporation | Semiconductor device and fabrication method thereof |
| US6373106B2 (en) | 1996-09-10 | 2002-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
-
1983
- 1983-06-30 JP JP58119271A patent/JPS6010769A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5994731A (en) * | 1996-07-19 | 1999-11-30 | Nec Corporation | Semiconductor device and fabrication method thereof |
| US6373106B2 (en) | 1996-09-10 | 2002-04-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0343787B2 (en) | 1991-07-03 |
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