JPS599973A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS599973A JPS599973A JP11945082A JP11945082A JPS599973A JP S599973 A JPS599973 A JP S599973A JP 11945082 A JP11945082 A JP 11945082A JP 11945082 A JP11945082 A JP 11945082A JP S599973 A JPS599973 A JP S599973A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fet
- drain
- source
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 238000000926 separation method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明（弓２、半導体集積回路装置、特にＧａＡ ｓな
との化合物半導体を用いたＭＥＳＦＥＴ 集積回路に関
し、１５号の漏えいを防き、歪特性を改善することを目
的とする。。DETAILED DESCRIPTION OF THE INVENTION The present invention (bow 2) relates to semiconductor integrated circuit devices, particularly MESFET integrated circuits using compound semiconductors such as GaAs, and aims to prevent leakage of No. 15 and improve distortion characteristics. Let's say.
Ｇ ａ Ａ ｓ電界効果トランジスタ（以下ＧａＡｓ
ＦＥＴと記す）は、その優れた高周波数特性とともに、
近年はその多機能、高安定、高利得性が注目され、Ｇａ
Ａｓ ＭＥＳ ＦＥＴを用いた集積回路が開発されてい
る。実用回路、特にチューナあるいは受信フロントエン
ドへの応用に際しては、単に利得制御幅や入出力離調度
だけでなく、利得制御時における混変調（歪）特性が重
要である。しかしながら、ＧａＡｓ Ｆ Ｅ Ｔを集積
化するにあたって、これらの重要な問題に対する対策は
まだ報告されていない。GaAs field effect transistor (hereinafter referred to as GaAs)
FET), along with its excellent high frequency characteristics,
In recent years, Ga
Integrated circuits using As MES FETs have been developed. When applied to practical circuits, especially tuners or reception front ends, not only the gain control width and input/output detuning degree, but also the cross-modulation (distortion) characteristics during gain control are important. However, in integrating GaAs FETs, no measures have been reported yet to address these important problems.
一般に、集積回路で最も基本的なことは個々の素子の分
離である。この分離が不完全であると、信号が漏えいし
、歪の原因となり、実用回路としての特性が著しく低下
する。In general, the most fundamental aspect of integrated circuits is the isolation of individual elements. If this separation is incomplete, signals will leak, causing distortion, and the characteristics as a practical circuit will be significantly degraded.
ＧａＡｓ ＭＥＳ ＦＥＴ集積回路においては、基板と
して半絶縁性のＧａＡ ｓ基板を使うことが出来るので
、従来は、第１図に示すＧａＡｓ ＭＥ Ｓ Ｆ Ｅ
Ｔ集積回路において活性層３をメサ・エツチングするこ
とによって、個々のＦＥＴ間の境界の活性層の部分を除
去し、個々のＦＥＴは半絶縁性ＧａＡ Ｆｌ基板１の上
の高比抵抗のバッファ層２０表面に島状として形成され
る。なお、第１図において、４はゲート、５はソース又
はドレインである。In a GaAs MES FET integrated circuit, a semi-insulating GaAs substrate can be used as the substrate, so conventionally the GaAs MES FET shown in FIG.
By mesa-etching the active layer 3 in the T integrated circuit, parts of the active layer at the interface between the individual FETs are removed, and the individual FETs are separated by a high resistivity buffer layer on a semi-insulating GaA Fl substrate 1. 20 is formed as islands on the surface. In FIG. 1, 4 is a gate, and 5 is a source or drain.
ところで特に集積回路化した場合、こうして分離された
ＦＥＴのゲート間においても、電位の相互影響が見られ
ることがある。これは、ＦＥＴの入力抵抗が数ＭＱ以上
とかなり高いので、高抵抗のバッファ層および半絶縁性
ＧａＡｓ基板たけでつながっていても、二個のＦＥＴが
近接されて形成された場合、これらのたがいに近接して
配置されたＦＥＴ０間の分離抵抗は、前記のＦＥＴの入
力抵抗と同程度の大きさとなり、その結果一方のＦＥＴ
のゲートへの入力信号により他方のＦＥＴのゲートの電
位が影響されて変化するためである。By the way, especially in the case of an integrated circuit, mutual influence of potentials may be observed even between gates of FETs separated in this way. This is because the input resistance of the FET is quite high, at several MQ or more, so if two FETs are formed close to each other even if they are connected only by a high-resistance buffer layer and a semi-insulating GaAs substrate, their resistance will be high. The isolation resistance between FET0, which is placed close to
This is because the potential of the gate of the other FET is influenced by the input signal to the gate of the other FET and changes.
丑だこのような２つのＦＥＴのゲート電位の相互の影響
は、層間絶縁膜のリークによって生じることもある。か
かるゲート電位の相互影響は、歪特性の悪化、および信
号の漏えいなどの原因となり、集積回路化の問題点とな
る。This mutual influence of the gate potentials of the two FETs may be caused by leakage in the interlayer insulating film. Such mutual influence of gate potentials causes deterioration of distortion characteristics and signal leakage, and becomes a problem in integrated circuits.
漏えいを防いだ半導体集積回路装置、特に化合物半導体
４ＭＥＳＦＥＴ集積回路を提供するものである。The present invention provides a semiconductor integrated circuit device that prevents leakage, particularly a compound semiconductor 4MESFET integrated circuit.
以下、図面によって本発明の実施例の半導体集積回路装
置を説明する。第２図は本発明の実施例の半導体集積回
路装置を示しており、ゲート６ａ。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be explained below with reference to the drawings. FIG. 2 shows a semiconductor integrated circuit device according to an embodiment of the present invention, with a gate 6a.
ドレインγａ、共通ソース８よりなる第１のＦＥＴとゲ
ート６ｂ、ドレイン７ｂ、共通ソース８よりなる第２０
ＦＥＴの２個のＦＥＴが示されている。同装置の特徴は
、前記第１０ＦＥＴと第２０ＦＥＴの境界の活性層を除
去して溝を形成し、この溝に、ソース、ドレイン電極と
同じオーミック電極またはゲート電極と同じ金属を付着
して分離帯９を形成し、この分離帯９をわく状接地電極
１０で接地するものである。この分離帯９は２個のＦＥ
Ｔのそれぞれのグー）６ａと６ｂ間のインピーダンスが
一個のＦＥＴのゲート・ソース間あるいはゲートドレイ
ン間のインピーダンスよりも高くなるように形成される
。A first FET consisting of a drain γa and a common source 8, and a 20th FET consisting of a gate 6b, a drain 7b and a common source 8.
Two FETs are shown. The feature of this device is that the active layer at the boundary between the 10th FET and the 20th FET is removed to form a groove, and the same ohmic electrode as the source and drain electrodes or the same metal as the gate electrode is attached to the groove to form an isolation band. 9 is formed, and this separation strip 9 is grounded by a frame-shaped ground electrode 10. This separation strip 9 has two FEs.
The impedance between each FET 6a and 6b is higher than the impedance between the gate and source or between the gate and drain of one FET.
このような本発明の構成により、高抵抗バッファ層を介
しての素子間の影響は著しく減少し、その結果歪特性が
格段に向」ニし、特性を安定化させることができる。With such a structure of the present invention, the influence between elements via the high-resistance buffer layer is significantly reduced, and as a result, the strain characteristics are significantly improved and the characteristics can be stabilized.
第１図は従来の半導体集積回路装置の断面図、第２図は
本発明の一実施例の半導体集積回路装置の断面図である
。
１ ｓｅｍｍａｎ ＧａＡｓ基板、２８＠＠＠＠ｍパン
フ７層、３・・・・・・活性層、４・・・・・・ゲート
、５・・・・・・ソース又はドレイン、ｓａ、ｅｂ ・
・・・・・ゲート、７ａ、７ｂ・・０・・ドレイン、８
ＩＩ・・・・・共通ソース、９・・・曝・・分離帯、１
Ｑ・・・・・・接地電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図FIG. 1 is a sectional view of a conventional semiconductor integrated circuit device, and FIG. 2 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 semman GaAs substrate, 28@@@@m pamphlet 7 layers, 3... active layer, 4... gate, 5... source or drain, sa, eb ・
...Gate, 7a, 7b...0...Drain, 8
II...Common source, 9...Exposure...Separation zone, 1
Q... Ground electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (2)
る複数個の電界効果トランジスタが、前記高抵抗基板に
よって連続されて配置され、たがいに隣接した２個の電
界トランジスタのそれぞれゲートの間に、接地電位を有
する導体領域が記載された半導体集積回路装置。(1) A plurality of field effect transistors each having a source, a drain, and a gate on a high resistance substrate are arranged in series by the high resistance substrate, and between each gate of two adjacent field effect transistors, A semiconductor integrated circuit device including a conductor region having a ground potential.
はゲート・ドレイン間のインピーダンスよりも、たがい
に隣接した２個の電界効果トランジスタのそれぞれのゲ
ート間のインピーダンスが高くなるように記載された特
許請求の範囲第１項記載の半導体集積回路装置。(2) Claims that are written in such a way that the impedance between the respective gates of two adjacent field effect transistors is higher than the impedance between the gate and source or between the gate and drain of the field effect transistors. 2. The semiconductor integrated circuit device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945082A JPS599973A (en) | 1982-07-08 | 1982-07-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11945082A JPS599973A (en) | 1982-07-08 | 1982-07-08 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS599973A true JPS599973A (en) | 1984-01-19 |
Family
ID=14761688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11945082A Pending JPS599973A (en) | 1982-07-08 | 1982-07-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599973A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4666010A (en) * | 1984-09-05 | 1987-05-19 | Mitsubishi Denki Kabushiki Kaisha | Power steering apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914797A (en) * | 1972-06-09 | 1974-02-08 |
-
1982
- 1982-07-08 JP JP11945082A patent/JPS599973A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914797A (en) * | 1972-06-09 | 1974-02-08 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4666010A (en) * | 1984-09-05 | 1987-05-19 | Mitsubishi Denki Kabushiki Kaisha | Power steering apparatus |
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